JP3342995B2 - Image display device and projector using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device having pixels arranged in a matrix, such as a liquid crystal display device, and more particularly to a plurality of types of image signals having different frequencies of a vertical synchronization signal and a horizontal synchronization signal. The present invention relates to an image display device that can display the image.

[0002]

2. Description of the Related Art Conventionally, among image display devices having a plurality of pixels arranged in a matrix, a liquid crystal display device has portability as an image display device having excellent features such as light weight, light weight, and low power consumption. It is widely used in notebook-type personal computers and the like that are valued. Also,
The liquid crystal display device is used not only as a direct-view type display such as the above-mentioned computer monitor, but also for a projection type projector.

FIG. 25 shows a schematic configuration of a conventional liquid crystal display device. As shown in FIG. 1, a conventional liquid crystal display device has an image display unit 5 in which pixels (not shown) are arranged in a matrix.
03, a scanning signal line driving circuit 501 for driving a scanning signal line for selecting a pixel row in which an image signal is to be written, and a data signal line driving circuit 502 for driving a data signal line for transferring data to be written to a pixel. ing.

[0006] The scanning signal line driving circuit 501 is provided with a shift register for sequentially selecting a plurality of scanning signal lines. Similarly, the data signal line driving circuit 502
A shift register for sequentially sampling and supplying an input image signal to each data signal line is provided. These shift registers are configured to operate sequentially according to the input of a timing signal.

[0005]

When the liquid crystal display device is used as a monitor of a computer or the like as described above, it is required that a plurality of types of image signals having different resolutions can be displayed. Further, even when used in the projector as described above, it is desirable to be able to display video signals having different resolutions such as NTSC signals and high-vision signals.

However, in the above-described conventional configuration, the scanning signal line driving circuit 501 and the data signal line driving circuit 50
The resolution of an image that can be displayed is fixed by the device as the shift registers provided in 2 sequentially operate. Accordingly, when a video signal having a resolution different from the resolution of the image display unit 503 is input, the following inconvenience occurs.

For example, it is assumed that the image display unit 503 has a resolution of 768 lines × 1024 dots. In this case, for example, when an image signal having a resolution of 480 lines × 640 dots is input, as shown in FIG.
3, a part of the same video is repeatedly displayed. That is, the conventional liquid crystal display device has a problem that it is impossible to appropriately display a video signal having a resolution different from the resolution of the image display unit.

The present invention has been made in view of the above problems, and has as its object to provide an image display device capable of inputting a plurality of types of image signals having different resolutions from each other and displaying the signals appropriately. .

[0009]

According to a first aspect of the present invention, there is provided an image display apparatus comprising: an image display unit having a plurality of pixels arranged in a matrix; A scanning signal line group provided along a row and selecting a pixel row to which an image signal is written, and an image display device including a data signal line group provided along a pixel column and transferring data to be written to a pixel, The scanning signal line group and the data signal line group are each divided into a plurality of blocks, the resolution of the image signal is determined, and a determination means for generating and outputting a control signal corresponding to the resolution; The scanning signal line block is classified into an operation block and a non-operation block in accordance with the scanning signal line driving means for driving the scanning signal line in the operation block, and the data signal line block in response to the control signal. The click classified into the operation block and a non-operation block, e Bei a data signal line drive circuit for driving the data signal lines of operation blocks, one of the scanning signal line group
Nth from the end (n: any number equal to or less than the number of blocks of the scanning signal line)
) And the n-th block from the other end
It consists of the same number of scanning signal lines as
M-th block from one end of signal line group and m-th block from other end
(M: any natural number less than or equal to the number of blocks of the data signal line)
Blocks consist of the same number of data signal lines.
That is, whether the scanning signal line driving means is a block of scanning signal lines.
When selecting a non-operation block from both ends of the scanning signal line group
From the block located at
In addition, the data signal line driving means
When selecting a non-operation block from blocks,
The same number is not operated from the blocks located at both ends of the line group
It is characterized by a block .

According to the first aspect of the present invention, when an image signal is input, the determination means determines the resolution of the image signal, and generates and outputs a control signal corresponding to the resolution.
The scanning signal line driving unit and the data signal line driving unit should receive the control signal and drive according to the input control signal from the scanning signal line group and the data signal line group divided into a plurality of blocks. Select a block. That is,
If the number of blocks of the scanning signal line group and the data signal line group and the number of scanning signal lines or data signal lines included in each block are set in advance according to a plurality of types of image signals having different resolutions, the input image An image can be displayed by driving only pixels necessary for displaying a signal. Pixels not required for displaying an image are not driven to form a non-display area. As a result, it is possible to display an image in an appropriate state for all of the plurality of types of image signals.

When an image signal having a resolution corresponding to an area smaller than that of the image display section is input, the scanning signal line driving means may be, for example, two blocks from one end of the scanning signal line group and two blocks from the other end. In other words, the same number of blocks located at both ends of the scanning signal line group are set as non-operation blocks, such that a total of four blocks are selected. Further, since the n-th block from one end of the scanning signal line group and the n-th block from the other end include the same number of scanning signal lines, the same number of scanning signal lines from both ends of the scanning signal line group. Is set to the non-operation state. Similarly, for the data signal lines, the same number of data signal lines from both ends of the data signal line group are brought into a non-operation state. Thus, the input image signal is displayed as an image in the center of the image display unit, and the area outside the image becomes a non-display area. Set the number of scanning signal lines and data signal lines in blocks and the number of scanning signal lines or data signal lines included in each block in advance according to the resolution of image signals that may be input to the device. Accordingly, it is possible to appropriately display an image in the central portion of the image display unit for all of a plurality of types of image signals having different resolutions.

[0012] The image display device according to the second aspect is the first aspect.
In the above-described device, the image display unit includes a liquid crystal display panel, and a display mode of the liquid crystal display panel is normally black.

According to the configuration of the second aspect, the non-display area of the image display section is a black display section as a light shielding section that does not transmit light. Since a constant voltage is not applied to the black display portion, it is possible to prevent the seizure phenomenon of the liquid crystal,
Power consumption in a portion that does not contribute to display is reduced. As a result, it is possible to provide a liquid crystal display device capable of appropriately displaying a plurality of types of image signals having different resolutions and reducing power consumption.

A projector according to a third aspect of the present invention is characterized in that the image display device according to the second aspect is provided as a light valve.

According to the third aspect of the invention, the center of gravity of the displayed image always coincides with the center of gravity of the image display unit regardless of the resolution of the input image signal. Enlargement or reduction can be easily performed. In addition, since the image display unit is configured with a liquid crystal display panel whose display mode is normally black,
The light from the light source inside the projector is shielded, and the quality of the projected image can be improved. Furthermore, since a steady voltage is not applied to the non-display area of the liquid crystal display panel, the burning phenomenon of the liquid crystal is prevented, and the power consumption in a portion that does not contribute to the display can be reduced.

[0016]

[Embodiment 1] One embodiment of the present invention will be described below with reference to FIGS.

The image display device according to the present embodiment includes a liquid crystal display panel in which pixels are arranged in a matrix as an image display section, and a scanning signal line group and a data signal line group are provided by being divided into a plurality of blocks, respectively. The liquid crystal display device is characterized by determining the resolution of an input image signal and operating only blocks necessary for displaying an image according to the resolution.

Hereinafter, the configuration and operation of the liquid crystal display device will be described in detail with reference to the drawings. FIG.
FIG. 3 is a block diagram illustrating a schematic configuration of the liquid crystal display device.
As shown in FIG. 1, the liquid crystal display device includes an image display unit 1 having a matrix pixel array. In the present embodiment, the image display unit 1 is assumed to be composed of a liquid crystal display panel. The present liquid crystal display further includes a resolution discriminating circuit 2, a timing generating circuit 3, a drive control circuit 4, a scanning signal line driving circuit 5 (scanning signal line driving means), and a data signal line driving circuit 6 (data signal line driving circuit). Driving means). Note that the resolution determination circuit 2 and the drive control circuit 4 correspond to a determination unit. The internal configuration and operation of each of these units will be described later.

The pixel arrangement of the image display unit 1 is 1024
Line x 1280 dots. That is, the liquid crystal display device includes 1024 scanning signal lines and 1280 data signal lines. The image signal input to the image display unit 1 is
VESA is a computer signal having monitor timing set as a standard specification and has four resolutions of 1024 lines × 1280 dots, 768 lines × 1024 dots, 600 lines × 800 dots, and 480 lines × 600 dots.

The resolution discriminating circuit 2 discriminates the resolution of the image signal based on the input vertical synchronizing signal and horizontal synchronizing signal, and generates a resolution discriminating signal in accordance with the resolution.
FIG. 2 is a block diagram showing a schematic configuration of the resolution determination circuit 2. As shown in FIG. As shown in FIG.
Is a counter 21 for receiving a vertical synchronizing signal and a horizontal synchronizing signal and calculating the number of horizontal synchronizing signals in one vertical period.
And a decoder 22. Further, the memory 23
And a comparator 24. The comparator 24 compares the output signal from the decoder 22 with the resolution information stored in the memory 23 to determine the resolution of the image signal. The result of this determination is the resolution determination signal c _1.
It is output as c _2.

FIG. 3 shows the resolution of the input image signal,
The resolution determination signal c ₁ · output by the resolution determination circuit 2
shows an example of the relationship between c _2. As shown in the figure, each of the resolution determination signals c ₁ and c ₂ is a 1-bit signal.
The above four types of resolutions are expressed by these combinations.

Further, the timing generation circuit 3 generates a timing signal (SP) necessary for the scanning signal line driving circuit 5.
G), a clock signal (CLKG), and a timing signal (SPS) and a clock signal (CLKS) necessary for the data signal line driving circuit 6 are generated and output.

As shown in FIG. 4, the drive control circuit 4 outputs a resolution determination signal c output from the resolution determination circuit 2.
₁ · c ₂ and four control signals a ₁ · a ₂ · a ₃ ·
to generate a ₄ outputs. These control signals a ₁ and a ₂
According to a ₃ and a ₄ , the operations of the scanning signal line driving circuit 5 and the data signal line driving circuit 6 are controlled as described later.

FIG. 5 shows the internal configuration of the scanning signal line driving circuit 5. The scanning signal line drive circuit 5 includes
Block 3 for displaying image signals of different resolutions
It is divided into seven blocks 1 to 37. Each of these blocks 31 to 37 includes a signal selection circuit 38, while each of them includes a scanning signal line selection circuit 45 to 51, respectively.

The signal selection circuit 38, as shown in FIG.
A control signal input terminal 59, and a terminal T ₁ and the terminal T _2. The control signal input terminal 59 is connected to the drive control circuit 4. The terminal T ₁ of the signal selection circuit 38 in to Blocks 31 34 timing generating circuit 3
And a timing signal (SPG) output from the timing generation circuit 3 as shown in FIG. On the other hand, the terminal T ₁ of the signal selection circuit 38 at 37 to block 35 without being grounded. In addition, terminal T
_{For 2} , the signal selection circuit 38 in the block 31
Terminal T ₂ are connected to ground, the terminal T ₂ of the signal selection circuit 38 at 37 to block 32 without being connected to the scanning signal line selection circuit of the previous block.

_{One of the} control signals a ₁ , a ₂ , a ₃ and a ₄ output from the drive control circuit 4 is input to the signal selection circuit 38 via the control signal input terminal 59 described above. More specifically, as shown in FIG. 5, the control signal a ₁ to the signal selection circuit 38 of the block 31 is input, the control signal a ₂ to the signal selection circuit 38 of the block 32 and 37, signal selection circuit blocks 33 and 36 Control signal a at 38
_3, the control signal a ₄ is input to the signal selection circuit 38 of the block 34 and 35. The signal selection circuit 38 switches the switch 60 shown in FIG.
Is switched between the terminals T ₁ and T ₂ . That is, the switch 60, if the control signal is "0" to the terminal T ₂ side, if the control signal is "1" is connected to the terminal T ₁ side.

Here, the scanning signal line selection circuits 45 to 5
1 will be described. As shown in FIG. 7, the scanning signal line selection circuit 45 includes a C signal for inputting a clock signal (CLKG) output from the timing generation circuit 3.
LKG input terminal 57 and signal selection circuit 3 in the same block
And a timing signal input terminal 65 for inputting an output signal from the control signal 8. Also, the output terminals 64, 64 ...
, And a scanning signal line is connected to each output terminal 64. In addition, a plurality of delay flip-flops 6
.. Are provided, and these constitute a shift register. The output from each delay flip-flop 62 is output to each scanning signal line via an amplifier 63 and an output terminal 64. Although the configuration of the scanning signal line selection circuit 45 has been illustrated and described above, the scanning signal line selection circuits 46 to 51 have a delay flip-flop 62, an amplifier 6
The other configurations are the same except for the number of output terminals 3 and the number of output terminals 64, and a detailed description thereof will be omitted.

The scanning signal line selection circuits 45 to 51
, Ie, the number of scanning signal lines connected to each of the blocks 31 to 37, is shown in FIG.
As shown in FIG. That is, the liquid crystal display device of the present embodiment includes 1024 scanning signal lines as described above, and these scanning signal lines are distributed as shown in FIG.
Scanning signal line selection circuit 4 included in blocks 31 to 37
5 to 51 are connected. As is clear from the figure, the number of scanning signal lines included in the blocks 31 and 37 is the same, and similarly, the blocks 32 and 3
6, blocks 33 and 35 are set to include the same number of scanning signal lines, respectively. Each of the scanning signal line selection circuits 45 to 51 has the same number of delay flip-flops 62 as the number of scanning signal lines shown in FIG.
An amplifier 63 and an output terminal 64 are provided.

Next, the configuration of the data signal line drive circuit 6 will be described. As shown in FIG. 9, the data signal line drive circuit 6 is divided into seven blocks 101 to 107, similarly to the above-described scan signal line drive circuit 5. The blocks 101 to 107 are all composed of the signal selection circuit 1
15 each of which has a data signal line selection circuit 1
08 to 114 are provided.

The signal selection circuit 115, as shown in FIG. 10, a control signal input terminal 146, the terminal T ₃ and terminal T
₄ and have. The control signal input terminal 146 is connected to the drive control circuit 4. The terminal T ₃ of the signal selection circuit 115 in the 104 to not block 101 is connected to the timing generation circuit 3, as shown in FIG. 9,
Timing signal (SPS) from timing generation circuit 3
Enter On the other hand, the terminal T ₃ of the signal selection circuit 115 in to Blocks 105 107 is grounded as shown in FIG. Also, the terminal T _4, the terminal T ₄ of the signal selection circuit 115 in the block 101 is grounded, the terminal T ₄ of the signal selection circuit 115 in to block 102 no 107 is connected to the data signal line selection circuit of the previous block I have.

The signal selection circuit 115 receives _{one of the} control signals a ₁ , a ₂ , a _3, and a ₄ output from the drive control circuit 4 through the control signal input terminal 146. More specifically, as shown in FIG.
The control signal a _{1 is} supplied to the signal selection circuit 115 of
The control signal a ₂ is input to the signal selection circuit 115 of blocks 107 and 107, the control signal a ₃ is input to the signal selection circuit 115 of blocks 103 and 106, and the control signal a ₄ is input to the signal selection circuit 115 of blocks 104 and 105.

The signal selection circuit 115 switches the connection of the switch 148 between the terminals T ₃ and T ₄ according to the content of the control signal input from the control signal input terminal 146. That is, the switch 148, if the control signal is "0" to the terminal T ₄ side, the control signal is in the case of "1" is connected to the terminal T ₃ side.

Here, the internal configuration of the data signal line selection circuits 108 to 114 will be described with reference to FIG. As shown in FIG.
Reference numeral 8 denotes a CLKS input terminal 12 for inputting a clock signal (CLKS) output from the timing generation circuit 3.
3 and the output terminal 1 of the signal selection circuit 115 in the same block.
And a timing signal input terminal 145 for inputting an output signal from the H.47.

The data signal line selection circuit 108 includes a plurality of delay flip-flops 141, 141,..., Which constitute a shift register.
Further, the data signal line selection circuit 108 includes switching circuits 142, 142,... Provided corresponding to the delay flip-flops 141, 141, respectively.
The image signal input via the image signal line 124 is sequentially sampled according to the switching operation of the switching circuit 142, and output to each data signal line via the amplifier 143 and the output terminal 144.

In the above description, the data signal line selection circuit 10
8, the data signal line selection circuits 109 to 114 are provided with the delay flip-flop 14
1, except that the numbers of the switching circuits 142, the amplifiers 143, and the output terminals 144 are different from those of the data signal line selection circuit 108, and a detailed description thereof will be omitted.

The number of data signal lines connected to the data signal line selection circuits 108 to 114 is as shown in FIG. That is, the liquid crystal display device of the present embodiment includes 1280 data signal lines as described above, and these data signal lines are connected to the data signal line selection blocks included in the blocks 101 to 107 as shown in FIG. It is distributed to each of the circuits 108-114. As can be seen from the figure, blocks 101 and 107, blocks 102 and 106, blocks 103 and 105
Are divided so that each of them includes the same number of data signal lines. Each of the data signal line selection circuits 108 to 114 has the same number of delay flip-flops 14 as the number of data signal lines shown in FIG.
1, a switching circuit 142, an amplifier 143, and an output terminal 144 are provided.

Next, the control signals a ₁ , a ₂ , a ₃ and a ₄ output from the drive control circuit ₄ and the scanning signal line selection circuit 4
The relationship between 5 and 51 and the operation of the data signal line selection circuits 108 to 114 will be described with reference to FIG.

For example, when the image signal input to the liquid crystal display device has a resolution of 768 lines × 1024 dots, the control signals a ₁ and a ₂ output from the drive control circuit 4
The combination of a ₃ and a ₄ is (0, 1,
0,0). In this case, the switch 60 of the signal selection circuit 38 is connected to the terminal T ₂ side in the block 31, it is connected to the terminal T ₁ side in block 32. That is, the input of the timing signal (SPG) is started from the block 32. Also, at block 37, the switch 60 of the signal selection circuit 38 is connected to the terminal T ₁ side or ground potential, the scanning signal line selection circuit 51 of the block 37 does not operate. That is, FIG.
As shown in (1), the blocks 31 and 37 of the scanning signal line driving circuit 5 are deactivated, and the blocks 32 to 36 are inactive.
Is in the operating state.

On the other hand, the blocks 101 to 107 of the data signal line driving circuit 6 are similarly set to the blocks 101 to 107.
And 107 are inactive and blocks 102 through 106 are active. That is, one block at each end of the scanning signal line driving circuit 5 and the data signal line driving circuit 6 is in a non-operating state. As a result, as shown in FIG. 14, the display state of the image display unit 1 is a non-display area of 128 pixels at both ends in the vertical and horizontal directions of the screen, and an image of 768 lines × 1024 dots is displayed in the image. It is displayed at the center of the display unit 1.

The resolution of the image signal is 600 lines × 8
Also in the case of 00 dots or 480 lines × 640 dots, as shown in FIG. 13, two or three blocks at both ends of the scanning signal line driving circuit 5 and the data signal line driving circuit 6, respectively, are in the non-operating state. As a result, the image is displayed at the center of the image display unit 1.

As described above, in the configuration of the present embodiment, the plurality of scanning signal lines and data signal lines are
2 are divided into a plurality of blocks with the distribution shown in FIG. Further, the resolution determining circuit 2 determines the resolution of the input image signal and outputs a resolution determining signal to the drive control circuit 4, and the drive control circuit 4 responds to the resolution determining signal as shown in FIG. Combination control signals a ₁ and a ₂
· A a _{3-a 4} outputs to the scan signal line driving circuit 5 and the data signal line drive circuit 6. In the scanning signal line driving circuit 5 and the data signal line driving circuit 6, the scanning signal line selection circuit 45 of each block is provided by the signal selection circuits 38 and 38 and the signal selection circuits 115 and 115 provided corresponding to each block. To 51 and the data signal line selection circuit 10
The operating states of 8 to 114 are determined as shown in FIG. As a result, only the pixels necessary for displaying the image in the image display unit 1 are driven to display the image, and the other pixels are not driven to form a non-display area. As a result, appropriate display can be performed for all of a plurality of types of image signals having different resolutions.

[Embodiment 2] FIGS. 15 to 18 mainly show an embodiment of the present invention.
The description will be made based on the following. For convenience of explanation, members having the same functions as those described in the first embodiment will be denoted by the same reference numerals as those used in the first embodiment, and detailed description will be omitted.

The liquid crystal display device as an image display device according to the present embodiment is characterized in that a clock to be supplied to a delay flip-flop is controlled in accordance with the resolution of an image signal to select a block to be operated. The liquid crystal display device according to the first embodiment includes the drive control circuit 4 and the scanning signal line drive circuit 5 shown in FIG.
In place of the data signal line drive circuit 6, a drive control circuit 7, a scan signal line drive circuit 8, and a data signal line drive circuit 9 having internal structures as shown in FIGS. The configuration is the same as in the first embodiment.
This is the same as the liquid crystal display device described above.

First, the configuration of the drive control circuit 7 provided in the present liquid crystal display device will be described with reference to FIG.
As shown in the figure, the drive control circuit 7 has two input terminals 201 and 202, to which resolution determination signals c ₁ and c ₂ from the resolution determination circuit 3 are input.
Further, the drive control circuit 7 includes a control signal output terminal 203
Through 209, and control signals a ₁ , a ₂ , a ₃ , a ₄ , b ₁ , b ₂ ,... For controlling the scanning signal line driving circuit 8 and the data signal line driving circuit 9 from these output terminals.
b ₃ is output.

Further, the scanning signal line driving circuit 8 is provided in the circuit shown in FIG.
As shown in FIG. 6, it is divided into seven blocks 210 to 216. The blocks 210 to 213 all include the signal selection circuit 38, while each includes the scanning signal line selection circuits 45 to 48, respectively. The blocks 214 to 216 are not provided with the signal selection circuit 38, but are provided with only the scanning signal line selection circuits 49 to 51, respectively.

_{One of the} control signals a ₁ , a ₂ , a _3, and a ₄ output from the drive control circuit 7 is input to the signal selection circuit 38 provided in each of the blocks 210 to 213. More specifically, as shown in FIG. 16, the control signal a ₁ is input to the signal selection circuit 38 of the block 210, the control signal a ₂ is input to the signal selection circuit 38 of the block 211, and the control signal a ₂ is input to the signal selection circuit 38 of the block 212. a
_{3. The} control signal a _{4 is} supplied to the signal selection circuit 38 of the block 213
Is entered.

As described above, blocks 210 through 21
By 3 is provided with a signal selection circuit 38, according to the combination of the control signal _{a 1 · a 2 · a 3} · a 4 from the drive control circuit 7, a timing generation to any of the blocks of the block 210 to 213 It is determined whether the timing signal (SPG) from the circuit 3 is input. That is, the block to which the SPG is input is the scanning start block.

The clock signal (CLKG) output from the timing generation circuit 3 is input to the scanning signal line selection circuits 45 to 51 by the control signals b ₁ , b ₂ , b ₃ from the drive control circuit 7. Is controlled. More particularly, the block 213 is input CLKG is intact, a logical product signal of the logical product signal between CLKG and the control signal b ₁ in block 212 and 214, and CLKG the block 211 and 215 and the control signal b _2, Block 2
The 10 and 216 logical product signal of the control signal b ₃ and CLKG are input. Thus, block 2
The operating state of each of 10 to 216 is determined.

Next, the configuration and operation of the data signal line drive circuit 9 will be described. As shown in FIG. 17, the data signal line driving circuit 9 includes seven blocks 230 to 23.
It is divided into six. Blocks 230 through 233
All of them have signal selection circuits 115, while each of them has data signal line selection circuits 108 to 111, respectively. Blocks 234 through 23
6, the signal selection circuit 115 is not provided, and the data signal line selection circuits 112 to 114 are provided.

_{One of the} control signals a ₁ , a ₂ , a _3, and a ₄ output from the drive control circuit 7 is input to the signal selection circuit 115 provided in each of the blocks 230 to 233. More specifically, as shown in FIG. 17, the control signal a ₁ to the signal selection circuit 115 of the block 230 is input, the control signals a _2, a control signal to the signal selection circuit 115 of the block 232 to the signal selection circuit 115 of the block 231 a ₃ , the control signal a ₄ is input to the signal selection circuit 115 of the block 233.

As described above, blocks 230 through 23
By 3 is provided with a signal selection circuit 115, in accordance with the combination of the control signal _{a 1 · a 2 · a 3} · a 4 from the drive control circuit 7, the block 230 to the timing generating circuit to the 233 throat block 3 is input. The block to which the SPS is input is a start block.

The clock signal (CLKS) output from the timing generation circuit 3 is input to the data signal line selection circuits 108 to 114 by the control signals b ₁ , b ₂ and b ₃ from the drive control circuit 7. Is controlled. More particularly, the block 233 is input CLKS is intact, a logical product signal of CLKS and the control signal b ₁ in block 232 and 234, blocks 231 and 23
Logical product signal of the 5 and CLKS and the control signal b _2, a logical product signal of the control signal b ₃ and CLKS in block 230 and 236 are input. Thereby, the operation state of each of the blocks 230 to 236 is determined.

Here, the resolution of the image signal and the control signal a
₁ · a ₂ · a ₃ · a ₄ · b ₁ · b ₂ · b ₃ and the operation states of the blocks 210 to 216 of the scanning signal line driving circuit 8 and the blocks 230 to 236 of the data signal line driving circuit 9 FIG. 18 shows the relationship. For example, if the image signal is
In the case of having a resolution of 768 lines × 1024 dots, since only the control signal a ₂ is “1”, scanning is started from the block 211 of the scanning signal line driving circuit 8, and the scanning of the data signal line driving circuit 9 is started. Block 231 is the start block for data transfer. Also, as is clear from FIG. 7, the blocks 210 and 216 of the scanning signal line driving circuit 8 and the blocks 230 and 236 of the data signal line driving circuit 9 are in a non-operation state.

As a result, as shown in FIG. 14, the display state of the image display section 1 is a non-display area of 128 pixels at both ends in the vertical and horizontal directions of the screen.
An image of 768 lines × 1024 dots is displayed at the center of the image display unit 1. Also, if the resolution of the image signal is 6
Even in the case of 00 lines × 800 dots or 480 lines × 640 dots, as is clear from FIG. 18, two or three blocks at both ends of the scanning signal line driving circuit 8 and the data signal line driving circuit 9 do not operate. By being in the state, the image is displayed at the center of the image display unit 1.

As described above, in the configuration of this embodiment, the signal selection circuit 38 or 115 provided in each block is used.
However, according to the control signal output from the drive control circuit 4 according to the resolution of the image signal, the block for inputting the timing signal and the clock signal output from the timing generation circuit 3 is controlled. In other words, according to the resolution of the image signal, the start block of scanning and the start block of data transfer are determined and the timing signal is input to the block, while the clock signal is not input to the block that should be inactive. Control is performed. Thus, only the pixels necessary to display the input image signal are driven to display an image, and the other pixels are not driven to form a non-display area. As a result,
Appropriate display can be performed for all of a plurality of types of image signals having different resolutions. Furthermore, by not inputting a clock signal to a block that does not contribute to image display, power consumption due to unnecessary clock operation can be suppressed.

Embodiment 3 An embodiment of the present invention will be described mainly with reference to FIGS.
3 will be described below. In addition,
For convenience of explanation, members having the same functions as those described in the above embodiments will be denoted by the same reference numerals as those used in the above embodiments, and detailed description will be omitted.

The liquid crystal display device as the image display device according to the present embodiment is characterized in that a power supply voltage is supplied only to blocks required for displaying an image in accordance with the resolution of an image signal. The present liquid crystal display device has a scanning configuration having an internal configuration as shown in FIG. 19 and FIG. 21 instead of the scanning signal line driving circuit 5 and the data signal line driving circuit 6 shown in FIG. The liquid crystal display includes a signal line driving circuit 11 and a data signal line driving circuit 12, and the other configuration is the same as that of the liquid crystal display device described in the first embodiment.

First, the configuration of the scanning signal line driving circuit 11 provided in the present liquid crystal display device will be described with reference to FIGS. The scanning signal line driving circuit 11 includes:
As shown in FIG. 19, seven blocks 310 to 31
It is divided into six. Blocks 310 through 313
All of them include the signal selection circuits 38, while each of them includes the scanning signal line selection circuits 317 to 320, respectively. The blocks 314 to 316 are not provided with the signal selection circuit 38 but provided with the scanning signal line selection circuits 321 to 323, respectively.

The signal selection circuit 38 of each of the blocks 310 to 313 includes a control signal a output from the drive control circuit 7.
Either _{1 · a 2 · a 3 ·} a 4 is input. More specifically, as shown in FIG. 19, the control signal a ₁ is input to the signal selection circuit 38 of the block 310 and the block 311
Signal selection circuit 38 to the control signal a ₂ of the control signal a ₃ in the signal selection circuit 38 of the block 312, the control signal a ₄ to the signal selection circuit 38 of the block 313 is input.

As described above, blocks 310 through 31
By 3 is provided with a signal selection circuit 38, according to the combination of the control signal _{a 1 · a 2 · a 3} · a 4 from the drive control circuit 7, the block 310 to the timing generating circuit to the 313 throat block 3 is input. That is, the block to which the SPG is input is the scanning start block.

As shown in FIG. 19, the control signal a _{1 is} supplied to the scanning signal line selection circuits 317 and 323, the control signal a _{2 is} supplied to the scanning signal line selection circuits 318 and 322, and the control signal a _{2 is} supplied to the scanning signal line selection circuits 319 and 321. the signal a _3, are input.

Here, the configuration and operation of the scanning signal line selection circuits 317 to 323 will be described. Each of the scanning signal line selection circuits 317 to 323 is the same as that of the first embodiment.
In addition to the configuration shown in FIG. 7, a power supply voltage switching circuit as shown in FIG. 20 is provided to switch the voltage supplied to the delay flip-flops 62. The number of scanning signal lines connected to each of the scanning signal line selection circuits 317 to 323,
That is, the number of scanning signal lines connected to each of the blocks 310 to 316 is the same as that of the blocks 31 to 37 shown in FIG.

This power supply voltage switching circuit includes a control signal input terminal 330, a switch 332, and a voltage output terminal 331, as shown in FIG. _One of the control signals a ₁ , a _2, and a ₃ is input to the control signal input terminal 330 as described above, and the switch 332 switches the power supply voltage (V _cc ) or the power supply voltage (V _cc ) according to the input control signal. Select the ground voltage side. The selected voltage is supplied to the delay flip-flop via the voltage output terminal 331. That is, when the switch 332 is switched to the GND side, the block becomes inactive.

Next, the configuration and operation of the data signal line drive circuit 12 will be described. The data signal line drive circuit 12
Is divided into seven blocks 340 to 346 as shown in FIG. Blocks 340 to 343
All have a signal selection circuit 115, while each of them has data signal line selection circuits 347 to 350, respectively. Also, blocks 344 through 34
6, the signal selection circuit 115 is not provided, and data signal line selection circuits 351 to 353 are provided.

Each of the signal selection circuits 115 provided in the blocks 340 to 343 receives _{one of the} control signals a ₁ , a ₂ , a ₃ and a ₄ output from the drive control circuit 7. More specifically, as shown in FIG. 21, the control signal a ₁ is input to the signal selection circuit 115 of the block 340, the control signal a ₂ is supplied to the signal selection circuit 115 of the block 341, and the control signal a _{2 is} supplied to the signal selection circuit 115 of the block 342. a ₃ , the control signal a ₄ is input to the signal selection circuit 115 of the block 343.

As described above, blocks 340 through 34
By 3 is provided with a signal selection circuit 115, in accordance with the combination of the control signal _{a 1 · a 2 · a 3} · a 4 from the drive control circuit 7, the block 340 to the timing generating circuit to the 343 throat block 3 is input. That is, the block to which the SPS is input is a data transfer start block.

As shown in FIG. 21, control signal a _{1 is applied} to data signal line selection circuits 347 and 353, control signal a _{2 is applied} to data signal line selection circuits 348 and 352, and control signal a _{2 is applied} to data signal line selection circuits 349 and 351. Signal a
₃ is input respectively. The control signal a ₄ is input to the data signal line selection circuit 350.

Here, the data signal line selection circuit 347
Through 353 will be described. Each of the data signal line selection circuits 347 to 353 is provided in addition to the configuration shown in FIG.
In order to switch the voltage supplied to the delay flip-flops 141 shown in FIG. 1, a power supply voltage switching circuit as shown in FIG. 20 is provided. Since the function of the power supply voltage switching circuit is the same as that of the scanning signal line selection circuits 317 to 323 of the scanning signal line driving circuit 11 described above, detailed description is omitted. The number of data signal lines connected to each of the data signal line selection circuits 347 to 353, that is, the number of data signal lines connected to each of the blocks 340 to 346 is the same as that of the first embodiment shown in FIG. Are the same as the blocks 101 to 107 shown in FIG.

Control signals a ₁ , a ₂ , a ₃ when image signals of various resolutions are input in the above configuration.
- and a _4, blocks 310 through 316 of the scanning signal line drive circuit 11, and the relationship between each of the operating states of the blocks 340 through 346 of the data signal line drive circuit 12, shown in FIG. 22. For example, if the image signal input to the liquid crystal display device has a resolution of 768 lines × 1024 dots, the control signal since only a ₂ becomes "1", the scanning start block scanning signal line drive circuit Eleven blocks 311
And the data transfer start block is the block 341 of the data signal line drive circuit 12. Also, as is apparent from FIG.
And 316 and the blocks 340 and 346 of the data signal line drive circuit 12 are brought into a non-operating state.

In this case, as shown in FIG. 14, the display state of the image display section 1 is a non-display area of 128 pixels at both ends in the vertical and horizontal directions of the screen.
An image of 768 lines × 1024 dots is displayed at the center of the image display unit 1. Also, if the resolution of the image signal is 6
Even in the case of 00 lines × 800 dots or 480 lines × 640 dots, as is clear from FIG. 22, two or three blocks at both ends of the scanning signal line driving circuit 11 and the data signal line driving circuit 12 do not operate. In this state, the image is displayed at the center of the image display unit 1.

As described above, in the configuration of this embodiment, the signal selection circuit 38 or 115 provided in each block is used.
However, according to the control signal output from the drive control circuit 4 according to the resolution of the image signal, the block to which the timing signal is input from the timing generation circuit 3 and the block to which the power supply voltage is supplied are selected. It has become so. That is, the above configuration is configured such that the timing signal is input to each of the scanning start block and the data transfer start block according to the resolution of the image signal, and the power supply voltage is not supplied to the block to be set to the non-operation state. ing.

As a result, only the pixels necessary to display the input image signal are driven to display an image, and the other pixels are not driven to form a non-display area. As a result, appropriate display can be performed for all of a plurality of types of image signals having different resolutions. Furthermore, by not supplying the power supply voltage to the blocks that do not contribute to the display of an image, the effect that the power consumption in the drive circuit can be reduced can be achieved.

In the above description including the first and second embodiments, the case of displaying an image signal having a display area equal to or smaller than the pixel arrangement of the image display unit 1 has been described. Conversely, a case where an image signal having a display area larger than the pixel array of the image display unit 1 is displayed will be described below.

For example, an image signal equivalent to the area 401 shown in FIG. 23A is input, and the pixel arrangement of the image display unit 1 is smaller than the area 401 (or 4).
Consider the case where the size is equivalent to 03). In such a case, the region 402 or 40 which is a part of the region 401
It is necessary that an arbitrary area such as 3 can be displayed.

For this reason, for example, when displaying the area 402 which is a part of the area 401, the scanning signal line driving circuit 11
Is the signal SP shown in the middle part of FIG.
G1 and the data signal line driving circuit 1
2 is the signal S shown in the middle part of FIG.
Set as PS1. When the region 403 is displayed, the timing signal of the scanning signal line driving circuit 11 is
The timing signal of the data signal line drive circuit 12 is set like the signal SPG2 shown in the lower part of FIG. Note that the signals shown at the top of FIGS. 7B and 7C are a vertical synchronizing signal and a horizontal synchronizing signal.

As described above, by arbitrarily setting the generation position of the timing signal in the timing generation circuit 3 with respect to the synchronizing signal of the image signal, an arbitrary area of the image larger than the pixel array of the image display unit 1 can be obtained. Can be displayed.

Embodiment 4 An embodiment of the present invention is described below with reference to FIG. For the sake of convenience, members having the same functions as those described in the above embodiments will be denoted by the same reference numerals as those used in the above embodiments, and detailed description will be omitted.

The liquid crystal display device as the image display device according to the present embodiment is characterized in that the display mode of the liquid crystal display device described in the first to third embodiments is normally black. The liquid crystal display device of the present embodiment can be suitably used as a light valve of a projector.

For example, assume that the resolution of the image display unit 1 of the present liquid crystal display device is 768 lines × 1024 dots, and the resolution is
When an image signal of 480 lines × 640 dots is input and displayed, the display of the image display unit 1 is as shown in FIG.
The area 411 is a display area where an image signal is displayed, and the area 412 is a non-display area. In addition, as shown in the figure, the area 411 is displayed at the center of the image display unit 1.

When the present liquid crystal display device is used as a light valve of a projector, since the display area is located at the center of the image display section 1 as described above, the optical system inside the projector can be made uniaxial. It is possible to easily realize a zoom function such as enlargement / reduction. Also,
Since the display mode is normally black, this area 412 is displayed in a black state, and has a function of blocking light from a light source inside the projector. Furthermore, since a steady voltage is not applied to the non-display portion, it is possible to prevent image sticking of the liquid crystal in the image display section 1 and to reduce power consumption in a portion that does not contribute to display. .

Each of the above embodiments is intended to clarify the technical contents of the present invention, and should not be construed as being limited to each of the above specific examples. Within the above, various changes can be made. For example, in the above-described embodiment, the image display device in which the image display unit is configured by the liquid crystal display panel is described. However, the configuration of the image display unit is not limited thereto, and various configurations can be used. Further, the circuit configuration, types of various signals, and the like are not limited to the above examples, and may be configured by other methods. Furthermore, various changes are made to the number of divided blocks of the scanning signal line driving circuit and the data signal line driving circuit, the number of scanning signal lines or data signal lines included in each block, and the detailed circuit configuration of each unit. Accordingly, it is possible to cope with image signals of various specifications.

[0082]

As described above, in the image display device according to the first aspect, the scanning signal line group and the data signal line group are each divided into a plurality of blocks, and the resolution of the image signal is determined. Determining means for generating and outputting a control signal according to the control signal, and a scanning signal line for driving the scanning signal line of the operation block by classifying the block of the scanning signal line into an operation block and a non-operation block in accordance with the control signal Driving means, and data signal line driving means for classifying the data signal line blocks into operation blocks and non-operation blocks according to the control signal, and driving the data signal lines of the operation blocks.
In addition, an n-th block (n: an arbitrary natural number equal to or smaller than the number of blocks of the scanning signal line) from one end of the scanning signal line group and an n-th block from the other end are composed of the same number of scanning signal lines, and The m-th block from one end of the data signal line group and the m-th (m: any natural number equal to or smaller than the number of data signal line blocks) block from the other end are composed of the same number of data signal lines. When the driving unit selects a non-operation block from the scanning signal line blocks, the same number of blocks as the non-operation blocks from the blocks located at both ends of the scanning signal line group are used, and the data signal line driving unit selects the non-operation block. When a non-operation block is selected from the blocks, the same number of blocks from both ends of the data signal line group are set as non-operation blocks.

As a result, the resolution of the input image signal
Only the pixels required to display the image
Different types of images with different resolutions
Display images in proper condition for all signals.
This makes it possible to achieve the above. Further, there is an effect that an image can be displayed at the center of the image display unit regardless of the resolution of the input image signal.

According to a second aspect of the present invention, the image display section comprises a liquid crystal display panel, and the display mode of the liquid crystal display panel is normally black. Accordingly, it is possible to provide a liquid crystal display device capable of appropriately displaying a plurality of types of image signals having different resolutions and reducing power consumption.

The projector according to the third aspect is the second aspect of the invention.
The image display device described above is provided as a light valve. Thereby, regardless of the resolution of the input image signal, the center of gravity of the displayed image always matches the center of gravity of the image display unit, so that the image can be easily enlarged or reduced by the zoom function or the like. A projector can be provided. In addition, since the power consumption of the light valve is reduced, the power consumption of the entire projector can be reduced.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, and is a block diagram illustrating a schematic configuration of a liquid crystal display device.

FIG. 2 is a block diagram illustrating a schematic configuration of a resolution determining circuit illustrated in FIG. 1;

FIG. 3 is an explanatory diagram illustrating an example of a resolution determination signal output by the resolution determination circuit according to a resolution of an image signal.

FIG. 4 is a circuit diagram illustrating a schematic configuration of a drive control circuit illustrated in FIG. 1;

FIG. 5 is a block diagram illustrating a schematic configuration of a scanning signal line driving circuit illustrated in FIG. 1;

6 is an explanatory diagram illustrating a schematic configuration of a signal selection circuit illustrated in FIG. 5;

FIG. 7 is a block diagram illustrating a schematic configuration of a scanning signal line selection circuit illustrated in FIG. 5;

8 is an explanatory diagram showing the number of scanning signal lines connected to each block of the scanning signal line driving circuit shown in FIG.

FIG. 9 is a block diagram illustrating a schematic configuration of a data signal line drive circuit illustrated in FIG. 1;

FIG. 10 is an explanatory diagram showing a schematic configuration of a signal selection circuit shown in FIG. 9;

FIG. 11 is a block diagram showing a schematic configuration of a data signal line selection circuit shown in FIG. 9;

12 is an explanatory diagram showing the number of data signal lines connected to each block of the data signal line drive circuit shown in FIG.

FIG. 13 is an explanatory diagram showing a relationship between resolution of an input image signal, a control signal output by the drive control circuit, and operation states of each block of a scan signal line drive circuit and a data signal line drive circuit. .

FIG. 14 is an explanatory diagram illustrating an example of a state where an image is displayed on an image display unit of the liquid crystal display device.

FIG. 15 is a circuit diagram illustrating a schematic configuration of a drive control circuit included in a liquid crystal display device according to another embodiment of the present invention.

FIG. 16 is a block diagram illustrating a schematic configuration of a scanning signal line driving circuit included in the liquid crystal display device.

FIG. 17 is a block diagram illustrating a schematic configuration of a data signal line driving circuit included in the liquid crystal display device.

FIG. 18 shows a relationship between the resolution of an input image signal, the control signal output from the drive control circuit, and the operation state of each block of the scan signal line drive circuit and the data signal line drive circuit in the liquid crystal display device. FIG.

FIG. 19 is a block diagram showing a schematic configuration of a scanning signal line driving circuit provided in a liquid crystal display device according to still another embodiment of the invention.

20 is an explanatory diagram illustrating a schematic configuration of a power supply voltage switching circuit included in the signal selection circuit illustrated in FIG. 19;

FIG. 21 is a block diagram illustrating a schematic configuration of a data signal line driving circuit included in the liquid crystal display device.

FIG. 22 shows a relationship between a resolution of an input image signal, a control signal output from the drive control circuit, and an operation state of each block of a scan signal line drive circuit and a data signal line drive circuit in the liquid crystal display device. FIG.

FIG. 23 shows a method for displaying an image signal larger than the pixel array of the image display unit, and FIG.
FIG. 4 is an explanatory diagram showing an example of a region that is a part of the image signal and displayed on the image display unit. FIG. 4B is a waveform diagram showing an example of a timing signal of the scanning signal line driving circuit. FIG. 3C is a waveform diagram showing an example of a timing signal of the data signal line driving circuit.

FIG. 24 is a diagram illustrating still another mode according to the embodiment of the present invention, and is an example of a display state of the image display unit when the display mode is set to normally black.

FIG. 25 is a block diagram illustrating a schematic configuration of a liquid crystal display device as an example of a conventional image display device.

FIG. 26 is an explanatory diagram showing an example of a display state of the image display unit when an image signal having a resolution different from the pixel arrangement of the image display unit is input to the conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image display part 2 Resolution discrimination circuit 4 Drive control circuit 5 Scan signal line drive circuit (scan signal line drive means) 6 Data signal line drive circuit (data signal line drive means)

Claims (3)

(57) [Claims] An image display unit having a plurality of pixels arranged in a matrix, a scanning signal line group provided along a pixel row of the image display unit and selecting a pixel row for writing an image signal, A data signal line group provided along a column and transferring data to be written to the pixel, wherein the scanning signal line group and the data signal line group are divided into a plurality of blocks, respectively. Determining means for determining the resolution of the signal, generating and outputting a control signal according to the resolution, and classifying the block of the scanning signal line into an operation block and a non-operation block according to the control signal, and scanning the operation block. Scanning signal line driving means for driving the signal lines; classifying the data signal line blocks into an operation block and a non-operation block according to the control signal; E Bei a data signal line drive means for driving the line, n-th from one end of the scanning signal line group (n: the scanning signal lines
(Any natural number less than or equal to the number of blocks)
Whether the n-th block has the same number of scanning signal lines as each other
And the m-th block from one end of the data signal line group.
(M: number of data signal line blocks)
Number of blocks equal to each other)
Data signal lines, and the scanning signal line driving means is not connected to the scanning signal line block.
When selecting an operation block, place both ends of the scanning signal line group.
If the same number of inactive blocks are
In both cases, the data signal line driving means blocks the data signal line.
When selecting a non-operation block from the block, the data signal line
The same number of non-operation blocks from the blocks located at both ends of the group
The image display apparatus characterized by a click. 2. An image display comprising a liquid crystal display panel.
The display mode of the liquid crystal display panel is normally black.
The image display device according to claim 1, wherein: 3. An image display device according to claim 2, wherein
Projector provided as a