JP3342322B2 - Method for manufacturing LED element display device - Google Patents
Method for manufacturing LED element display deviceInfo
- Publication number
- JP3342322B2 JP3342322B2 JP31668896A JP31668896A JP3342322B2 JP 3342322 B2 JP3342322 B2 JP 3342322B2 JP 31668896 A JP31668896 A JP 31668896A JP 31668896 A JP31668896 A JP 31668896A JP 3342322 B2 JP3342322 B2 JP 3342322B2
- Authority
- JP
- Japan
- Prior art keywords
- led
- electrode
- led element
- chip
- type layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Landscapes
- Led Devices (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Led Device Packages (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、複数のLED(Li
ght Emitting Diode;発光ダイオード)素子を含んで構
成されるLED表示装置の製造方法に関し、とくにLE
D素子の実装に特徴を有するLED表示装置の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention
ght Emitting Diode; a method for manufacturing an LED display device including a light emitting diode (LED) device
The present invention relates to a method for manufacturing an LED display device having a feature in mounting a D element.
【0002】[0002]
【従来の技術】LED素子は、一般にpn接合のダイオ
ードであり、材料や製造方法により様々な色の発光を呈
するものがある。この様々な発光色のLED素子を用い
て表示画素を構成することによって、単色表示やカラー
表示のLED表示装置が製造される。LED表示装置
は、他のCRT(Cathode Ray Tube;ブラウン管)や液
晶などの表示装置に比べて、表示単位すなわちLED素
子が大きく、100インチ以上の大画面表示として用い
られることが多い。2. Description of the Related Art LED elements are generally pn junction diodes, and some of them emit light of various colors depending on materials and manufacturing methods. By configuring display pixels using the LED elements of various emission colors, an LED display device for monochromatic display or color display is manufactured. The LED display device has a large display unit, that is, an LED element, as compared with other display devices such as a CRT (Cathode Ray Tube; CRT) or a liquid crystal, and is often used as a large screen display of 100 inches or more.
【0003】一方で、100インチ以下の表示装置を製
造して、CRTや液晶の表示装置と同等かそれ以上の品
位を得るために、すなわち画素の精細度、輝度またはコ
ントラストなどの品位を得るために、LED素子を小さ
くするか、またはLED素子を密集させて実装する必要
がある。LED表示装置の構成画素となるLED素子
は、たとえば500μm×500μm×500μm以下
の大きさにする必要がある。On the other hand, in order to manufacture a display device having a size of 100 inches or less and obtain a quality equal to or higher than that of a CRT or liquid crystal display device, that is, to obtain a quality such as pixel definition, brightness or contrast. In addition, it is necessary to reduce the size of the LED elements or to mount the LED elements densely. The LED element serving as a constituent pixel of the LED display device needs to have a size of, for example, 500 μm × 500 μm × 500 μm or less.
【0004】実装の方法については、LED素子の電極
がpn接合の両側にあるようなものは、通常、一方の電
極が導電性接着剤で固定接続され、もう一方の電極はワ
イヤボンディングされて実装される。また、pn接合の
片側だけに電極が形成されたLED素子は、以下のよう
にして実装される。[0004] Regarding the mounting method, when the electrodes of the LED element are on both sides of the pn junction, usually, one electrode is fixedly connected with a conductive adhesive, and the other electrode is wire-bonded and mounted. Is done. An LED element having an electrode formed only on one side of a pn junction is mounted as follows.
【0005】図14(a)は従来技術のLED表示装置
を構成するLED素子20の構造を示す平面図であり、
図14(b)は図14(a)の切断面線A−Aから見た
断面図である。LED素子20は、基板1上にn型層2
およびp型層3がこの順番に積層され、n型層2および
p型層3の一部がエッチングによって除去されて、n型
層2が露出している。露出したn型層2上には電極5が
形成され、残余のp型層3上には電極6が形成されてお
り、電極5および電極6の表面は、ともに基板1に関し
て同じ側を向いている。FIG. 14A is a plan view showing the structure of an LED element 20 constituting a conventional LED display device.
FIG. 14B is a cross-sectional view taken along line AA of FIG. 14A. The LED element 20 includes an n-type layer 2 on a substrate 1.
Then, the p-type layer 3 is laminated in this order, a part of the n-type layer 2 and a part of the p-type layer 3 are removed by etching, and the n-type layer 2 is exposed. An electrode 5 is formed on the exposed n-type layer 2 and an electrode 6 is formed on the remaining p-type layer 3. The surfaces of the electrode 5 and the electrode 6 face the same side with respect to the substrate 1. I have.
【0006】図15は図14のLED素子20のワイヤ
ボンディングによる実装構造を示す断面図である。LE
D素子20の電極5および電極6は、配線基板7に対面
する向きと反対向きに配置され、電極5および電極6は
配線基板7のカソード電極9およびアノード電極10
に、Au線などを用いてそれぞれワイヤボンディングさ
れる。FIG. 15 is a sectional view showing a mounting structure of the LED element 20 of FIG. 14 by wire bonding. LE
The electrode 5 and the electrode 6 of the D element 20 are arranged in the direction opposite to the direction facing the wiring board 7, and the electrode 5 and the electrode 6 are connected to the cathode electrode 9 and the anode electrode 10 of the wiring board 7.
Then, wire bonding is performed using an Au wire or the like.
【0007】図16はLED素子20のバンプ15およ
びバンプ16による実装構造を示す断面図である。バン
プ15およびバンプ16はAuなどから成り、電極5お
よび電極6上に、個々のLED素子20ごとに蒸着した
り、ボール状に成型したものを接着したりした後に、配
線基板7上のカソード電極9およびアノード電極10に
接続される。接続は、異方導電性樹脂または絶縁性樹脂
などから成る接着剤13を隙間に塗布して加圧固定する
ことによって行われる。LED素子20が配線基板7上
に配置される向きは図15とは逆向きで、バンプ15お
よびバンプ16が配線基板7に対面するように配置され
る。FIG. 16 is a sectional view showing a mounting structure of the LED element 20 using the bumps 15 and 16. The bumps 15 and 16 are made of Au or the like, and are deposited on the electrodes 5 and 6 for each individual LED element 20 or bonded in a ball shape, and then the cathode electrode on the wiring board 7 is formed. 9 and the anode electrode 10. The connection is performed by applying an adhesive 13 made of an anisotropic conductive resin, an insulating resin, or the like to the gap and fixing it by pressing. The direction in which the LED elements 20 are arranged on the wiring board 7 is opposite to that in FIG. 15, and the bumps 15 and 16 are arranged so as to face the wiring board 7.
【0008】[0008]
【発明が解決しようとする課題】図15のワイヤボンデ
ィングによる実装構造では、個々のLED素子20ごと
にワイヤボンディングする必要があり、LED表示装置
の製造工程において非能率的である。また、ワイヤボン
ドが2本も必要であり、かなりの場所をとるのでスペー
スの利用効率が悪い。In the mounting structure by wire bonding shown in FIG. 15, it is necessary to perform wire bonding for each LED element 20, which is inefficient in the manufacturing process of the LED display device. In addition, two wire bonds are required, which takes up a considerable amount of space, resulting in poor space utilization efficiency.
【0009】図16のバンプ15およびバンプ16を介
在させた実装構造では、ワイヤボンディングが不要で、
スペースの利用効率が良い反面、バンプ15およびバン
プ16を含むLED素子20の厚み、すなわち基板1底
面からバンプ15およびバンプ16表面までの長さを高
精度に制御できない。この長さが制御できないと、確実
な実装が困難である。また、図16のLED素子20を
複数個用いて、LED表示装置を製造しようとしても、
LED素子の厚みを制御できないと、これらを同時に実
装できなくなり、製造工程は非能率的である。In the mounting structure in which the bumps 15 and 16 shown in FIG. 16 are interposed, wire bonding is unnecessary.
Although the space utilization efficiency is high, the thickness of the LED element 20 including the bumps 15 and 16, that is, the length from the bottom surface of the substrate 1 to the surfaces of the bumps 15 and 16 cannot be controlled with high accuracy. If this length cannot be controlled, reliable mounting is difficult. Further, even if an attempt is made to manufacture an LED display device using a plurality of the LED elements 20 of FIG.
If the thickness of the LED elements cannot be controlled, they cannot be mounted at the same time, and the manufacturing process is inefficient.
【0010】本発明の目的は、簡易な構成で、能率的に
製造できるLED表示装置の製造方法を提供することで
ある。An object of the present invention is to provide a method of manufacturing an LED display device which can be manufactured efficiently with a simple configuration.
【0011】[0011]
【0012】[0012]
【0013】[0013]
【0014】[0014]
【課題を解決するための手段】本発明は、接合したn型
層およびp型層を基板に形成した後、一方の層の一部を
除去して、接合方向の一方側にそれぞれ露出する各層の
チップ接続面を有するLEDチップ部を形成する工程
と、各チップ接続面上に所定形状の上部空間を残し、電
気絶縁部を形成する工程と、前記電気絶縁部を覆いかつ
前記各チップ接続面上の前記上部空間を埋めて導電性樹
脂を塗布する工程と、前記電気絶縁部上の前記導電性樹
脂の一部を除去して前記電気絶縁部の一部を露出させる
とともに接続電極を形成する工程と、基板を分割して、
複数のLED素子を形成する工程と、各LED素子の接
続電極を、配線基板上の配線に対面させて接続する工程
とを含むことを特徴とするLED表示装置の製造方法で
ある。SUMMARY OF THE INVENTION According to the present invention, after forming a bonded n-type layer and a p-type layer on a substrate, a part of one of the layers is removed to expose each layer exposed on one side in the bonding direction. Forming an LED chip portion having a chip connection surface, forming an electrical insulation portion while leaving an upper space of a predetermined shape on each chip connection surface, and covering the electrical insulation portion and forming each of the chip connection surfaces. A step of filling the upper space above with a conductive resin and removing a part of the conductive resin on the electric insulating part to expose a part of the electric insulating part and form a connection electrode. Process and the substrate,
A method for manufacturing an LED display device, comprising: a step of forming a plurality of LED elements; and a step of connecting a connection electrode of each LED element so as to face a wiring on a wiring board.
【0015】[0015]
【0016】また本発明は、前記導電性樹脂の塗布が印
刷の方法によるものであることを特徴とする。本発明に
従えば、印刷の方法により導電性樹脂を塗布するので塗
布厚にばらつきがなくなる素子としての厚みの精度が向
上する。Further, the present invention is characterized in that the application of the conductive resin is performed by a printing method. According to the present invention, since the conductive resin is applied by a printing method, the accuracy of the thickness of the element which does not vary in the applied thickness is improved.
【0017】また本発明は、p型層およびn型層の材料
が異なり青、赤および緑の3色発光用のLEDチップ部
を個々に形成した後、各LEDチップ部のチップ接続面
上に、それぞれ素子接続面の高さが等しい接続電極を形
成して、各LED素子を形成して、配線基板上に配置す
ることを特徴とする。本発明に従えば、材料を様々に変
えて発光色の異なる3種類のLED素子を形成して、3
種類ともに素子接続面の高さを等しくする。すなわち、
材料等の違いによってLEDチップ部の厚みが異なるこ
とが多いが、素子接続面の高さが等しい接続電極を形成
するので、これに合わせて素子電極の厚みが調整され
る。よって、3種類のLED素子の素子接続面の高さを
揃えることができ、複数のLED素子を配線基板に一括
して接続でき、能率的にLED表示装置を製造すること
ができる。Further, according to the present invention, the p-type layer and the n-type layer are made of different materials, and the LED chips for emitting three colors of blue, red and green are individually formed. A connection electrode having the same element connection surface height is formed, and each LED element is formed and arranged on a wiring board. According to the present invention, three kinds of LED elements having different emission colors are formed by changing materials in various ways,
For all types, the height of the element connection surface is made equal. That is,
Although the thickness of the LED chip portion often differs depending on the difference in materials and the like, since the connection electrodes having the same height of the element connection surface are formed, the thickness of the element electrodes is adjusted accordingly. Therefore, the heights of the element connection surfaces of the three types of LED elements can be made uniform, a plurality of LED elements can be collectively connected to the wiring board, and an LED display device can be efficiently manufactured.
【0018】[0018]
【発明の実施の形態】本発明の一実施形態であるLED
表示装置の製造方法を、以下のように図1〜図13を用
いて説明する。まず図1〜図8を用いて、LED表示装
置を構成するLED素子の製造方法とその構造を説明す
る。このうち、図1〜図5を用いて青色のLED素子5
0を説明し、図6〜図8を用いて赤色のLED素子90
を説明する。つぎに図9〜図13を用いて、LED素子
を実装してLED表示装置を製造する方法とその構造を
説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS LED according to one embodiment of the present invention
A method of manufacturing a display device will be described with reference to FIGS. First, a method for manufacturing an LED element included in an LED display device and a structure thereof will be described with reference to FIGS. Among them, the blue LED element 5 will be described with reference to FIGS.
0 and the red LED element 90 will be described with reference to FIGS.
Will be described. Next, a method of manufacturing an LED display device by mounting LED elements and a structure thereof will be described with reference to FIGS.
【0019】なお、本実施形態のLED表示装置は、
青、赤および緑の3色発光用のLED素子から成り、カ
ラー表示が可能である。緑色のLED素子については、
青色のLED素子50と同じ構造でもよいし、赤色のL
ED素子90と同じ構造でもよい。各LED素子の大き
さは、たとえば300μm×300μm×300μmほ
どである。Note that the LED display device of the present embodiment
It is composed of LED elements for emitting three colors of blue, red and green, and is capable of color display. For the green LED element,
The same structure as the blue LED element 50 may be used, or the red L
It may have the same structure as the ED element 90. The size of each LED element is, for example, about 300 μm × 300 μm × 300 μm.
【0020】(青色LED素子)図1は、青色LED素
子50の製造に用いられる半導体ウエハ30の層構造を
示す断面図である。半導体ウエハ30は、サファイア基
板31上にGaNバッファ層36、n型GaN層37、
n型GaAlN層38、GaInN発光層34、p型G
aAlN層39およびp型GaN層40がこの順に積層
されたものであり、厚みはW1である。(Blue LED Element) FIG. 1 is a sectional view showing a layer structure of a semiconductor wafer 30 used for manufacturing a blue LED element 50. The semiconductor wafer 30 has a GaN buffer layer 36, an n-type GaN layer 37 on a sapphire substrate 31,
n-type GaAlN layer 38, GaInN light-emitting layer 34, p-type G
The aAlN layer 39 and the p-type GaN layer 40 are laminated in this order, and the thickness is W1.
【0021】なお、これ以降は説明の簡略化のために、
GaNバッファ層36、n型GaN層37およびn型G
aAlN層38をまとめてn型層32とし、p型GaA
lN層39およびp型GaN層40をまとめてp型層3
3とする。図2〜図13においても同様に、n型層32
およびp型層33だけを描き、発光層34はn型層32
およびp型層33に比べて極めて薄いので、省略する。From now on, for simplicity of explanation,
GaN buffer layer 36, n-type GaN layer 37 and n-type G
The aAlN layer 38 is put together to form the n-type layer 32, and the p-type GaAs
The 1N layer 39 and the p-type GaN layer 40 are put together to form the p-type layer 3
3 is assumed. 2 to 13, similarly, the n-type layer 32
And only the p-type layer 33 is drawn, and the light-emitting layer 34 is the n-type layer 32
Since it is extremely thin compared to the p-type layer 33, the description is omitted.
【0022】図2(a)〜図2(e)は、半導体ウエハ
30を用いて青色LED素子50を製造する工程を段階
的に示す断面図である。図2(a)では、半導体ウエハ
30の所定の領域をp型層33から発光層34を越えて
n型層32の内部までエッチングで取り除き、またはダ
イヤモンドブレードなどで切削することによって取り除
き、n型層32のチップ接続面132を露出させ、残っ
たp型層33の表面をチップ接続面133とする。チッ
プ接続面132上に、オーミックな金属薄膜のチップ電
極45を蒸着することによって形成し、チップ接続面1
33上に同じくオーミックな金属薄膜のチップ電極46
を蒸着して形成する。両電極ともに全面にわたる電極と
して、可能な限り電気抵抗の小さい特性を実現すること
が望ましい。FIGS. 2A to 2E are sectional views showing steps of manufacturing the blue LED element 50 using the semiconductor wafer 30. In FIG. 2A, a predetermined region of the semiconductor wafer 30 is removed by etching from the p-type layer 33 to the inside of the n-type layer 32 beyond the light-emitting layer 34 or by cutting with a diamond blade or the like. The chip connection surface 132 of the layer 32 is exposed, and the surface of the remaining p-type layer 33 is used as a chip connection surface 133. On the chip connecting surface 132, a chip electrode 45 of an ohmic metal thin film is formed by vapor deposition, and the chip connecting surface 1 is formed.
A chip electrode 46 of an ohmic metal thin film on 33
Is formed by vapor deposition. It is desirable that both electrodes have characteristics with as small an electric resistance as possible over the entire surface.
【0023】図2(b)では、図2(a)のエッチング
等によって積層方向の切断面に露出した発光層34、ま
たはn型層32とp型層33との接合面を被覆するよう
に、かつチップ電極45上に所定の形状の上部空間13
4を残し、チップ電極46上に所定の形状の上部空間1
35を残して、電気絶縁部43を形成する。上部空間1
34および上部空間135は、チップ接続面133から
の高さを数10μmとする。電気絶縁部43は、光硬化
型の材料であり、たとえばエポキシアクリレートなどの
モノマに感光剤を適宜混練したペースト状樹脂などから
成る。このような樹脂の所定量をメタルマスクなどを用
いて、一旦、全面に印刷塗布した後に、前述のような形
状の上部空間134および上部空間135が残るよう
に、マスキングして露光して現像するフォトエッチング
によって、電気絶縁部43を形成する。図2(a)およ
び図2(b)の工程によって、半導体ウエハ30の一部
を除去して、チップ電極45とチップ電極46と電気絶
縁部43とを形成したものを半導体ウエハ29とする。In FIG. 2B, the light emitting layer 34 or the bonding surface between the n-type layer 32 and the p-type layer 33 exposed on the cut surface in the stacking direction by the etching or the like in FIG. And an upper space 13 having a predetermined shape on the chip electrode 45.
4 and the upper space 1 having a predetermined shape on the chip electrode 46.
The electric insulating portion 43 is formed except for 35. Upper space 1
The height of the upper space 135 from the chip connection surface 133 is several tens μm. The electrical insulating portion 43 is a photo-curing type material, and is made of, for example, a paste resin obtained by appropriately kneading a photosensitive agent into a monomer such as epoxy acrylate. After a predetermined amount of such a resin is once printed and applied on the entire surface using a metal mask or the like, masking, exposure, and development are performed so that the upper space 134 and the upper space 135 having the above-described shapes remain. The electric insulating portion 43 is formed by photoetching. 2A and 2B, a part of the semiconductor wafer 30 is removed to form the chip electrode 45, the chip electrode 46, and the electrical insulating portion 43, thereby obtaining a semiconductor wafer 29.
【0024】図2(c)では、Agエポキシペーストま
たはAuエポキシペーストなどの導電性樹脂が、半導体
ウエハ29の上部空間134および上部空間135を埋
めて、さらに電気絶縁部43を覆い隠すように印刷塗布
される。塗布された導電性樹脂は加熱硬化されて導電樹
脂層44となるが、このときに、ウエハの反りを誘発し
て後の工程に支障をきたすことがあるので、100℃〜
120℃程度で充分硬化して加熱収縮ができる限り小さ
くなるように、導電性樹脂の組成は厳選される。In FIG. 2C, a conductive resin such as an Ag epoxy paste or an Au epoxy paste is printed so as to fill the upper space 134 and the upper space 135 of the semiconductor wafer 29 and further cover the electrical insulating portion 43. Applied. The applied conductive resin is cured by heating to form the conductive resin layer 44. At this time, since the warpage of the wafer may be induced to hinder the subsequent steps, the temperature may be reduced to 100 ° C.
The composition of the conductive resin is carefully selected so that it is sufficiently cured at about 120 ° C. and the heat shrinkage becomes as small as possible.
【0025】図2(d)では、電気絶縁部43上の導電
性樹脂層44の一部をダイヤモンドブレードなどで切削
して、電気絶縁部43の一部を露出させる。すなわちハ
ーフダイスであるが、このハーフダイスを行うことによ
って、チップ電極45上に残った導電性樹脂層44の一
部を素子電極55とし、チップ電極46上に残った導電
性樹脂層44の一部を素子電極56とする。ここで、チ
ップ電極45と素子電極55とを合わせて接続電極15
5とし、チップ電極46と素子電極56とを合わせて接
続電極156とする。また、素子電極55の表面を素子
接続面136とし、素子電極56の表面を素子接続面1
37とする。In FIG. 2D, a part of the conductive resin layer 44 on the electric insulating part 43 is cut with a diamond blade or the like to expose a part of the electric insulating part 43. That is, a half die is formed. By performing the half die, a part of the conductive resin layer 44 remaining on the chip electrode 45 is used as an element electrode 55, and one part of the conductive resin layer 44 remaining on the chip electrode 46 is formed. The portion is referred to as an element electrode 56. Here, the connection electrode 15 is formed by combining the chip electrode 45 and the device electrode 55.
5, and the connection electrode 156 is formed by combining the chip electrode 46 and the device electrode 56. The surface of the device electrode 55 is defined as the device connection surface 136, and the surface of the device electrode 56 is defined as the device connection surface 1.
37.
【0026】図2(e)では、半導体ウエハ29に電気
絶縁部43と接続電極155と接続電極156とを形成
したものを、フルダイスによって複数のLED素子50
に分割する。分割は、p型層33を切削することなく、
電気絶縁部43の一部が切削面上に露出するように切削
して行う。チップ電極45は素子電極55だけに、チッ
プ電極46は素子電極56だけに電気的に接続される。In FIG. 2E, a semiconductor wafer 29 in which the electrical insulating portion 43, the connection electrode 155, and the connection electrode 156 are formed is combined with a plurality of LED elements 50 by a full die.
Divided into The division is performed without cutting the p-type layer 33,
The cutting is performed so that a part of the electric insulating portion 43 is exposed on the cutting surface. The chip electrode 45 is electrically connected only to the element electrode 55, and the chip electrode 46 is electrically connected only to the element electrode 56.
【0027】なお図2(b)では、チップ接続面132
およびチップ接続面133の電気絶縁部43によって被
覆されない部分の面積を可能な限り広くして、この上に
形成される素子電極55および素子電極56の電気的な
特性を確保することが好ましい。しかし一方で、図2
(e)の工程では、素子電極55および素子電極56
が、それぞれチップ電極45およびチップ電極46だけ
に電気的に接続されるので、ハーフダイスは必ず電気絶
縁部43を切削しながら行われる。その結果、電気絶縁
部43は切削された端面に露出した形状になり、チップ
電極45の電気絶縁部43によって被覆されない部分の
面積はある程度狭くなり、切削のために必要な大きさの
電気絶縁部43が確保される。電気絶縁部43の大きさ
は、素子電極の電気的特性と切削の精度とのバランスを
考慮して、決定する必要がある。In FIG. 2B, the chip connection surface 132
In addition, it is preferable that the area of the portion of the chip connection surface 133 that is not covered by the electrical insulating portion 43 is made as large as possible to secure the electrical characteristics of the element electrode 55 and the element electrode 56 formed thereon. However, on the other hand, FIG.
In the step (e), the device electrode 55 and the device electrode 56
Are electrically connected only to the chip electrode 45 and the chip electrode 46, respectively, so that the half dice is always performed while cutting the electrical insulating portion 43. As a result, the electric insulating portion 43 has a shape exposed to the cut end face, the area of the portion of the tip electrode 45 not covered by the electric insulating portion 43 is reduced to some extent, and the electric insulating portion having a size required for cutting is reduced. 43 is secured. The size of the electrical insulating portion 43 needs to be determined in consideration of the balance between the electrical characteristics of the element electrode and the cutting accuracy.
【0028】また、電気絶縁部43を形成するときの樹
脂の塗布厚については、図2(d)のハーフダイスによ
って、素子電極55と素子電極56とを分離するとき
に、誤ってp型層33を切削しないように、ダイヤモン
ドブレードの位置の精度を考慮する必要がある。たとえ
ば、前述したように、p型層33表面より少なくとも数
10μm以上高くなるような塗布厚が必要である。Regarding the coating thickness of the resin when forming the electric insulating portion 43, when the device electrode 55 and the device electrode 56 are separated by the half die shown in FIG. In order not to cut 33, it is necessary to consider the accuracy of the position of the diamond blade. For example, as described above, a coating thickness that is at least several tens of μm higher than the surface of the p-type layer 33 is required.
【0029】また、図2(c)に示されるように、基板
31の底面から素子接続面136までの長さを、素子接
続面136の高さW2とする。同様に素子接続面137
の高さもW2である。導電性樹脂の塗布厚は、LED素
子50の厚みがW2に一致するように設定しなければな
らない。また、高さW2のばらつきは、±10μm以内
に納まることが望ましい。半導体ウエハ30の厚みW1
は、通常、場所によって±30μm程度のばらつきがあ
るが、後述する図3のスクリーン印刷法によって導電性
樹脂を塗布すれば、このばらつきは吸収されて、素子の
厚みの精度は±10μmに抑えられる。As shown in FIG. 2C, the length from the bottom surface of the substrate 31 to the element connection surface 136 is defined as the height W2 of the element connection surface 136. Similarly, the element connection surface 137
Is also W2. The application thickness of the conductive resin must be set so that the thickness of the LED element 50 matches W2. Further, it is desirable that the variation of the height W2 be within ± 10 μm. Thickness W1 of semiconductor wafer 30
Usually, there is a variation of about ± 30 μm depending on the place. However, if a conductive resin is applied by a screen printing method shown in FIG. 3 described later, this variation is absorbed and the accuracy of the element thickness is suppressed to ± 10 μm. .
【0030】図3(a)〜図3(d)はスクリーン印刷
法によって導電性樹脂を塗布する工程を示す断面図であ
り、これによって図2(c)の導電性樹脂層44を形成
する。図3(a)では、図2(b)の半導体ウエハ29
が吸着ステージ66に固定される。図3(b)では、適
宜な厚さのステンレス製などのメタルマスク67を、半
導体ウエハ29上に形成されたチップ電極46の表面、
または電気絶縁部43に接触させて被覆する。メタルマ
スク67上の片隅に所定量の電極材料としてAgエポキ
シペーストなどの導電性樹脂塊44aを装填する。FIGS. 3A to 3D are cross-sectional views showing a step of applying a conductive resin by a screen printing method, whereby the conductive resin layer 44 shown in FIG. 2C is formed. In FIG. 3A, the semiconductor wafer 29 shown in FIG.
Is fixed to the suction stage 66. In FIG. 3B, a metal mask 67 made of stainless steel or the like having an appropriate thickness is provided on the surface of the chip electrode 46 formed on the semiconductor wafer 29,
Alternatively, it is brought into contact with the electric insulating portion 43 to cover the same. A conductive resin block 44a such as an Ag epoxy paste is loaded as a predetermined amount of electrode material in one corner of the metal mask 67.
【0031】図3(c)では、吸着ステージ66上の半
導体ウエハ29が固定される表面から常に高さW2だけ
離れて、平行に移動できるステンレスブレードなどから
成るスキージ68を用いて、導電性樹脂を半導体ウエハ
29上に印刷塗布して導電性樹脂層44を形成する。な
お、吸着ステージ66とスキージ68との距離、すなわ
ちスキージの高さW2のばらつきは、前述したように±
10μm未満の精度で実現される。図3(d)では、メ
タルマスク67を半導体ウエハ29から分離して印刷を
終了する。In FIG. 3C, a conductive resin is used by using a squeegee 68 made of a stainless steel blade or the like that can move parallel to the surface of the suction stage 66 on which the semiconductor wafer 29 is fixed by a height W2. Is printed on the semiconductor wafer 29 to form the conductive resin layer 44. Note that the distance between the suction stage 66 and the squeegee 68, that is, the variation in the squeegee height W2 is ±
It is realized with an accuracy of less than 10 μm. In FIG. 3D, the metal mask 67 is separated from the semiconductor wafer 29 and printing is completed.
【0032】このように図2および図3に示す製造方法
によって形成されたLED素子50は、次の図4および
図5に示すような構造となる。The LED element 50 formed by the manufacturing method shown in FIGS. 2 and 3 has a structure as shown in FIGS. 4 and 5.
【0033】図4はLED素子50の構成を示す斜視図
であり、図5(a)は断面図であり、図5(b)は素子
電極側から見た平面図であり、図5(c)は基板31側
から見た底面図である。なお図5(a)の断面図は、図
5(b)の切断面線B−Bから見た図である。FIG. 4 is a perspective view showing the structure of the LED element 50, FIG. 5 (a) is a sectional view, FIG. 5 (b) is a plan view from the element electrode side, and FIG. () Is a bottom view as viewed from the substrate 31 side. Note that the cross-sectional view of FIG. 5A is a view taken along the line BB of FIG. 5B.
【0034】図4、図5(a)および図5(b)に示す
ように、素子電極55および素子電極56は電気絶縁部
43によって電気的に絶縁されている。これら2電極は
ともに基板31の一方側に形成されていて、素子接続面
136または素子接続面137の高さは、ともにW2で
ある。基板31の他方側の底面には、図5(c)に示す
ように電極は形成されない。As shown in FIGS. 4, 5A and 5B, the device electrode 55 and the device electrode 56 are electrically insulated by the electric insulating portion 43. These two electrodes are both formed on one side of the substrate 31, and the height of the element connection surface 136 or the element connection surface 137 is W2. No electrode is formed on the bottom surface of the other side of the substrate 31 as shown in FIG.
【0035】上述した図2および図3の製造方法によれ
ば、素子接続面136および素子接続面137が同じ高
さW2であるような、接続電極155および接続電極1
56を有するLED素子50を形成することができる。
また、複数のLED素子50は、半導体ウエハ29にま
とめて形成された後に分割することによって得られるの
で、すべてのLED素子50の素子接続面の高さを等し
くW2とすることができる。According to the manufacturing method of FIGS. 2 and 3 described above, the connection electrode 155 and the connection electrode 1 such that the element connection surface 136 and the element connection surface 137 have the same height W2.
An LED element 50 having 56 can be formed.
In addition, since the plurality of LED elements 50 are obtained by being collectively formed on the semiconductor wafer 29 and then divided, the height of the element connection surfaces of all the LED elements 50 can be equal to W2.
【0036】(赤色LED素子)図6は、赤色LED素
子90に用いられる半導体ウエハ230の層構造を示す
断面図である。半導体ウエハ230は、n型層32、活
性層34およびp型層33がこの順に接合して構成さ
れ、全体の厚みはW3である。図1の半導体ウエハ30
との違いは、各層の構成材料が異なって厚みが異なり、
絶縁性のサファイア基板31が存在しない点である。(Red LED Element) FIG. 6 is a sectional view showing a layer structure of a semiconductor wafer 230 used for the red LED element 90. The semiconductor wafer 230 is configured by joining an n-type layer 32, an active layer 34, and a p-type layer 33 in this order, and has a total thickness of W3. The semiconductor wafer 30 of FIG.
The difference is that the constituent materials of each layer are different and the thickness is different,
The point is that the insulating sapphire substrate 31 does not exist.
【0037】図7(a)〜図7(e)は、半導体ウエハ
230を用いて赤色LED素子90を製造する方法を示
す断面図である。図7(a)および図7(b)では、図
2(a)および図2(b)と同様に半導体ウエハ230
の一部をエッチング等で取り除き、チップ電極45およ
びチップ電極46を形成し、電気絶縁部43を形成し
て、これを半導体ウエハ229とする。図7(c)で
は、図2(c)および図3と同様にスキージ68の高さ
をW2に設定して、導電性樹脂を塗布して導電性樹脂層
44を形成する。図7(d)および図7(e)では、図
2(d)および図2(e)と同様にして、導電性樹脂層
44の一部を除去して、素子電極55および素子電極5
6を形成する。半導体ウエハ229上に電気絶縁部43
と接続電極155と接続電極156とを形成したもの
を、複数のLED素子90に分割する。FIGS. 7A to 7E are cross-sectional views showing a method of manufacturing the red LED element 90 using the semiconductor wafer 230. In FIGS. 7A and 7B, the semiconductor wafer 230 is formed similarly to FIGS. 2A and 2B.
Is partially removed by etching or the like, the chip electrode 45 and the chip electrode 46 are formed, and the electric insulating portion 43 is formed. In FIG. 7C, the height of the squeegee 68 is set to W2 and a conductive resin is applied to form the conductive resin layer 44 as in FIGS. 2C and 3. In FIGS. 7D and 7E, similarly to FIGS. 2D and 2E, part of the conductive resin layer 44 is removed, and the device electrode 55 and the device electrode 5 are removed.
6 is formed. The electric insulating portion 43 is formed on the semiconductor wafer 229.
And the connection electrode 155 and the connection electrode 156 are divided into a plurality of LED elements 90.
【0038】図8は、赤色LED素子90の構造を示し
ており、図8(a)は断面図であり、図8(b)は素子
電極側から見た平面図であり、図8(c)はn型層32
側から見た底面図である。図8(a)は図8(b)の切
断面線C−Cから見た図である。これらはサファイア基
板1を除いて図5と同じ構造になっている。FIG. 8 shows the structure of the red LED element 90. FIG. 8A is a sectional view, FIG. 8B is a plan view seen from the element electrode side, and FIG. ) Indicates the n-type layer 32
It is the bottom view seen from the side. FIG. 8A is a view as seen from a cut line CC of FIG. 8B. These have the same structure as FIG. 5 except for the sapphire substrate 1.
【0039】上述した図7の製造方法によれば、図8に
示すように、半導体ウエハ230の厚みがW3となり、
図1の半導体ウエハ30の厚みW1とは異なることが多
いが、図2の青色LED素子50と同様に、素子接続面
136および素子接続面137のそれぞれの高さをW2
とすることができる。According to the manufacturing method of FIG. 7, the thickness of the semiconductor wafer 230 becomes W3 as shown in FIG.
Although the thickness is often different from the thickness W1 of the semiconductor wafer 30 in FIG. 1, similarly to the blue LED element 50 in FIG. 2, the height of each of the element connection surface 136 and the element connection surface 137 is set to W2.
It can be.
【0040】(緑色LED素子)緑色LED素子につい
ては図示しないが、前述したとおり、青色LED素子5
0または赤色LED素子90と同じ構造を有する。各層
の材料等が異なってLEDチップ部の厚みが異なること
が多いが、素子電極を形成する工程において、スキージ
68の高さをW2に設定して、素子接続面の高さをW2
に揃える。こうして、緑色LED素子の素子接続面の高
さは、青色LED素子50および赤色LED素子90の
素子接続面の高さW2と同一とすることができる。(Green LED Element) Although the green LED element is not shown, as described above, the blue LED element 5
It has the same structure as the zero or red LED element 90. Although the thickness of the LED chip portion is often different due to different materials of each layer, the height of the squeegee 68 is set to W2 and the height of the element connection surface is set to W2
Align with Thus, the height of the element connection surface of the green LED element can be the same as the height W2 of the element connection surface of the blue LED element 50 and the red LED element 90.
【0041】(LED素子の実装)このように製造され
た青色LED素子50、赤色LED素子90および緑色
LED素子を以下に示すように実装してカラーLED表
示装置とする。(Mounting of LED elements) The blue LED element 50, the red LED element 90 and the green LED element thus manufactured are mounted as described below to obtain a color LED display device.
【0042】図9は青色LED素子50および赤色LE
D素子90を実装した状態を示す部分断面図である。本
実施形態のLED表示装置となる部分は、図9のうちの
配線基板77と、配線基板77の上に形成されている配
線79〜配線82と、配線79および配線80に接続さ
れるLED素子50と、配線81および配線82に接続
されるLED素子90と、接着剤75とで構成される。
各LED素子の配線基板77への接続は、フェイスダウ
ン型のボンディングであり、異方導電性樹脂などの接着
剤75によって、LED素子50およびLED素子90
が配線基板77に接着されて行われる。この後、下型7
2上にLED素子50およびLED素子90を搭載した
配線基板77を載せて、上型73を当接させて加圧およ
び加熱して固定する。FIG. 9 shows a blue LED element 50 and a red LE.
FIG. 3 is a partial cross-sectional view showing a state where a D element 90 is mounted. The part that becomes the LED display device of the present embodiment includes the wiring board 77 in FIG. 9, the wirings 79 to 82 formed on the wiring board 77, and the LED elements connected to the wirings 79 and 80. 50, an LED element 90 connected to the wiring 81 and the wiring 82, and an adhesive 75.
The connection of each LED element to the wiring board 77 is a face-down type bonding, and the LED element 50 and the LED element 90 are bonded by an adhesive 75 such as an anisotropic conductive resin.
Is adhered to the wiring board 77. After this, the lower mold 7
A wiring board 77 on which the LED element 50 and the LED element 90 are mounted is mounted on the upper surface 2, and the upper die 73 is brought into contact with the wiring board 77, and is fixed by pressing and heating.
【0043】下型72は、Alなどで加工して平滑な載
置面を有し、加熱用のヒータの役割を有する。上型73
は、同様に平滑な押圧面を有し、LED素子50および
LED素子90に当接する押圧面には緩衝材74が設け
られている。緩衝材74はシリコンラバーなどの耐熱性
の材質から成り、厚さは数10μm〜数100μm程度
である。この緩衝材74は、個々のLED素子の厚みの
ばらつきが±10μm程度であるなら、ばらつきを吸収
して平坦な表示面を形成できるものである。The lower mold 72 has a smooth mounting surface processed by Al or the like, and has a role of a heater for heating. Upper mold 73
Has a similarly smooth pressing surface, and a cushioning member 74 is provided on the pressing surface that contacts the LED element 50 and the LED element 90. The cushioning member 74 is made of a heat-resistant material such as silicon rubber, and has a thickness of several tens μm to several hundreds μm. If the variation of the thickness of each LED element is about ± 10 μm, the buffer 74 can absorb the variation and form a flat display surface.
【0044】このように青、赤色のLED素子は同じ厚
みW2を有しており、互いに平行で平坦な2枚の型に挟
むことで、同時に圧着できる。緑色のLED素子につい
ても、図示していないが、同様に厚みW2が同じなので
同時に圧着できる。また、各色のLED素子が複数であ
っても同様で、すべてのLED素子が同時に圧着でき
る。As described above, the blue and red LED elements have the same thickness W2 and can be pressed simultaneously by being sandwiched between two parallel and flat molds. Although not shown, the green LED element can be pressed at the same time because the thickness W2 is the same. The same applies to a case where there are a plurality of LED elements of each color, and all the LED elements can be pressed at the same time.
【0045】つぎに、配線基板77上での各色のLED
素子の配置関係を、以下の図10〜図13を用いて説明
する。Next, the LED of each color on the wiring board 77
The arrangement relationship of the elements will be described with reference to FIGS.
【0046】図10は各LED素子の配置関係を示すL
ED表示装置の部分平面図である。1個の青色LED素
子50、1個の赤色LED素子90および1個の緑色L
ED素子100は、1個の表示画素95を構成する。こ
れら3種のLED素子はL字状に配置されて、それぞれ
の接続電極の一方は同じ配線94に共通して接続され、
他方は別々の配線91、配線92および配線93に接続
される。このような複数の表示画素95が、配線基板7
7上にマトリクス状に配列される。なお、図9の配線8
0および配線82はともに配線94に相当し、図9の配
線79および配線81はそれぞれ配線91〜配線93の
いずれかに相当するものである。FIG. 10 is a view showing an arrangement relationship of each LED element.
FIG. 3 is a partial plan view of the ED display device. One blue LED element 50, one red LED element 90 and one green L
The ED element 100 forms one display pixel 95. These three types of LED elements are arranged in an L-shape, and one of the connection electrodes is commonly connected to the same wiring 94,
The other is connected to separate wiring 91, wiring 92 and wiring 93. The plurality of display pixels 95 are connected to the wiring substrate 7.
7 are arranged in a matrix. The wiring 8 in FIG.
The line 0 and the line 82 both correspond to the line 94, and the line 79 and the line 81 in FIG. 9 correspond to any of the lines 91 to 93, respectively.
【0047】図11は1個の表示画素95の電気的な構
成を示す回路図である。LED素子50、LED素子9
0およびLED素子100のそれぞれのカソード電極は
共通の配線94に接続され、アノード電極は別々の配線
91、配線92および配線93に接続される。このよう
に、1個の表示画素95内において、各LED素子の一
方の接続電極に接続される配線を共有させることで、表
示装置を簡易な構成としている。FIG. 11 is a circuit diagram showing an electrical configuration of one display pixel 95. LED element 50, LED element 9
The cathode electrodes of the LED 0 and the LED element 100 are connected to a common wiring 94, and the anode electrodes are connected to separate wirings 91, 92 and 93. Thus, the display device has a simple configuration by sharing the wiring connected to one connection electrode of each LED element in one display pixel 95.
【0048】図12は、LED表示装置200の表示面
を示す平面図である。図12中の十文字の位置Pに1個
の表示画素95が配置され、全体ではマトリクス状に3
2×16の表示画素が配列される。FIG. 12 is a plan view showing the display surface of the LED display device 200. One display pixel 95 is arranged at the position P of the cross in FIG.
2 × 16 display pixels are arranged.
【0049】図13は、LED表示装置200の電気的
構成を示す回路図である。X方向およびY方向は、配線
基板77上の互いに直交する2方向である。X方向に3
2個の表示画素、Y方向に16個の表示画素がマトリク
ス状に配列される。X方向に並ぶ1行の表示画素95内
のLED素子のカソード電極は、すべてX方向に延びる
1本の配線94に接続され、Y方向に並ぶ1列の表示画
素95内のLED素子のアノード電極はすべてY方向に
延びる3本の配線91、配線92および配線93にそれ
ぞれ接続される。FIG. 13 is a circuit diagram showing an electrical configuration of the LED display device 200. The X direction and the Y direction are two directions orthogonal to each other on the wiring board 77. 3 in X direction
Two display pixels and 16 display pixels are arranged in a matrix in the Y direction. The cathode electrodes of the LED elements in one row of display pixels 95 arranged in the X direction are all connected to one wiring 94 extending in the X direction, and the anode electrodes of the LED elements in one column of display pixels 95 arranged in the Y direction. Are connected to three wirings 91, 92 and 93, all extending in the Y direction.
【0050】本実施形態では、青、赤および緑の3色の
LED素子から成り、カラー表示を行うLED表示装置
を示したが、青、赤および緑色の組み合わせに限るもの
ではない。また、2色のLED素子から成るLED表示
装置でもよく、単色のものでもよい。2色または3色の
LED表示装置では、単色のものに比べて、各LED素
子の材料等が互いに異なり、各層の厚みも異なることが
多いが、素子接続面の高さはすべて等しくなる。In the present embodiment, the LED display device for displaying a color, which is composed of three color LED elements of blue, red and green, is shown, but the present invention is not limited to the combination of blue, red and green. Further, an LED display device including two-color LED elements or a single-color LED device may be used. In a two-color or three-color LED display device, the materials and the like of each LED element are different from each other and the thickness of each layer is often different from that of a single-color LED display device, but the heights of the element connection surfaces are all equal.
【0051】また、図1の半導体ウエハ30では7層構
造とし、図6の半導体ウエハ230では省略して3層構
造としたが、これに限らず、n型層32およびp型層3
3が含まれて発光する構造であればよい。Although the semiconductor wafer 30 of FIG. 1 has a seven-layer structure, and the semiconductor wafer 230 of FIG. 6 has a three-layer structure by omitting it, the present invention is not limited to this.
3 may be used as long as it emits light.
【0052】さらに、上述した青色以外の構造のLED
素子の材料およびその発光色としては、たとえば下記に
挙げるようなものがある。LED素子90に示したn型
層32/p型層33の材料を、GaP/GaPとすると
赤色、黄緑色または緑色を発光するLED素子となる。
GaP/GaAsPとすると赤色、橙色または黄色を発
光するLED素子となる。また、GaAlAs/GaA
lAsとすると赤色を発光するLED素子となる。ただ
し、GaAlAs/GaAlAsとした場合に限り、L
ED素子のp型層33/n型層32の順とする。Further, an LED having a structure other than the above-mentioned blue color
Examples of the material of the element and its emission color include the following. When the material of the n-type layer 32 / p-type layer 33 shown in the LED element 90 is GaP / GaP, the LED element emits red, yellow-green, or green light.
If GaP / GaAsP is used, the LED element emits red, orange, or yellow light. GaAlAs / GaAs
If it is 1As, it becomes an LED element that emits red light. However, only when GaAlAs / GaAlAs is used, L
The order is p-type layer 33 / n-type layer 32 of the ED element.
【0053】しかし、これに限るものではなく、絶縁基
板上にp型層およびn型層が積層されたもの、n型基板
上にp型層を形成したもの、またはp型基板上にn型層
を形成したものなどであればよい。However, the present invention is not limited to this. One in which a p-type layer and an n-type layer are laminated on an insulating substrate, one in which a p-type layer is formed on an n-type substrate, and one in which an n-type layer is formed on a p-type substrate What is necessary is just to form a layer.
【0054】[0054]
【発明の効果】以上のように本発明によれば、複数のL
ED素子の素子接続面を精度よく一致させ、一括して同
時に全LED素子を実装でき、簡易な構成で効率よく光
を取り出すことができ、装置の信頼性を向上することが
できる。As described above, according to the present invention, a plurality of L
The element connection surfaces of the ED elements can be accurately matched, all the LED elements can be mounted simultaneously and collectively, light can be efficiently extracted with a simple configuration, and the reliability of the device can be improved.
【0055】また本発明によれば、材料を様々に変えて
発光色の異なる3種類のLED素子が形成され、LED
チップ部の厚みが異なっても、接続電極の厚みを調整す
ることで、3種類のLED素子の素子接続面の高さを揃
えることができる。Further, according to the present invention, three kinds of LED elements having different emission colors are formed by changing the materials in various ways.
Even if the chip portions have different thicknesses, the heights of the element connection surfaces of the three types of LED elements can be made uniform by adjusting the thickness of the connection electrodes.
【図1】青色LED素子50に用いられる半導体ウエハ
30の層構造を示す断面図である。FIG. 1 is a cross-sectional view showing a layer structure of a semiconductor wafer 30 used for a blue LED element 50.
【図2】半導体ウエハ30を用いてLED素子50を製
造する工程を示す断面図である。FIG. 2 is a cross-sectional view showing a step of manufacturing the LED element 50 using the semiconductor wafer 30.
【図3】スクリーン印刷法で導電性樹脂を塗布する工程
を示す断面図である。FIG. 3 is a cross-sectional view showing a step of applying a conductive resin by a screen printing method.
【図4】LED素子50の斜視図である。FIG. 4 is a perspective view of the LED element 50.
【図5】図5(a)はLED素子50の構成を示す断面
図であり、図5(b)は素子電極側から見た平面図であ
り、図5(c)は基板31側から見た底面図である。5A is a cross-sectional view showing the configuration of the LED element 50, FIG. 5B is a plan view seen from the element electrode side, and FIG. 5C is a view seen from the substrate 31 side. FIG.
【図6】赤色LED素子90に用いられる半導体ウエハ
230の層構造を示す断面図である。FIG. 6 is a sectional view showing a layer structure of a semiconductor wafer 230 used for a red LED element 90.
【図7】半導体ウエハ230を用いてLED素子90を
製造する方法を示す断面図である。FIG. 7 is a cross-sectional view illustrating a method of manufacturing the LED element 90 using the semiconductor wafer 230.
【図8】図8は赤色LED素子90の構造を示してお
り、図8(a)は断面図であり、図8(b)は素子電極
側から見た平面図であり、図8(c)はn型層32側か
ら見た底面図である。8 shows a structure of a red LED element 90, FIG. 8 (a) is a cross-sectional view, FIG. 8 (b) is a plan view seen from the element electrode side, and FIG. () Is a bottom view as seen from the n-type layer 32 side.
【図9】青色LED素子50および赤色LED素子90
を実装した状態を示す断面図である。FIG. 9 shows a blue LED element 50 and a red LED element 90.
FIG. 4 is a cross-sectional view showing a state in which is mounted.
【図10】配線基板77上でのLED素子の配置関係を
示す平面図である。FIG. 10 is a plan view showing an arrangement relationship of LED elements on a wiring board 77.
【図11】1個の表示画素95の電気的構成を示す回路
図である。FIG. 11 is a circuit diagram showing an electrical configuration of one display pixel 95.
【図12】LED表示装置200の表示面を示す平面図
である。FIG. 12 is a plan view showing a display surface of the LED display device 200.
【図13】LED表示装置200の表示画素95および
配線の接続関係を示す図である。FIG. 13 is a diagram showing a connection relationship between display pixels 95 and wiring of the LED display device 200.
【図14】図14(a)は従来技術のLED素子20の
構造を示す平面図であり、図10(b)は断面図であ
る。FIG. 14A is a plan view showing the structure of a conventional LED element 20, and FIG. 10B is a sectional view.
【図15】LED素子20のワイヤボンディングによる
実装構造を示す断面図である。FIG. 15 is a sectional view showing a mounting structure of the LED element 20 by wire bonding.
【図16】LED素子20のバンプ15およびバンプ1
6による実装構造を示す断面図である。FIG. 16 shows bump 15 and bump 1 of LED element 20.
6 is a cross-sectional view showing a mounting structure according to No. 6.
31 サファイア基板 32 n型層 33 p型層 43 電気絶縁部 44 導電性樹脂層 50,90,100 LED素子 68 スキージ 77 配線基板 79〜81,92〜94 配線 132,133 チップ接続面 134,135 上部空間 136,137 素子接続面 155,156 接続電極 W2 素子接続面の高さ REFERENCE SIGNS LIST 31 sapphire substrate 32 n-type layer 33 p-type layer 43 electrical insulating part 44 conductive resin layer 50, 90, 100 LED element 68 squeegee 77 wiring board 79 to 81, 92 to 94 wiring 132, 133 chip connection surface 134, 135 upper part Space 136,137 Device connection surface 155,156 Connection electrode W2 Height of device connection surface
フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 33/00 Continuation of front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 33/00
Claims (3)
成した後、一方の層の一部を除去して、接合方向の一方
側にそれぞれ露出する各層のチップ接続面を有するLE
Dチップ部を形成する工程と、 各チップ接続面上に所定形状の上部空間を残し、電気絶
縁部を形成する工程と、 前記電気絶縁部を覆いかつ前記各チップ接続面上の前記
上部空間を埋めて導電性樹脂を塗布する工程と、 前記電気絶縁部上の前記導電性樹脂の一部を除去して前
記電気絶縁部の一部を露出させるとともに接続電極を形
成する工程と、 基板を分割して、複数のLED素子を形成する工程と、 各LED素子の接続電極を、配線基板上の配線に対面さ
せて接続する工程とを含むことを特徴とするLED表示
装置の製造方法。After forming a bonded n-type layer and a p-type layer on a substrate, a part of one of the layers is removed, and an LE having a chip connection surface of each layer exposed to one side in a bonding direction is provided.
A step of forming a D chip portion, a step of forming an electric insulating portion while leaving an upper space of a predetermined shape on each chip connecting surface, and a step of covering the electric insulating portion and forming the upper space on each of the chip connecting surfaces. Filling a conductive resin, removing a portion of the conductive resin on the electrical insulating portion to expose a portion of the electrical insulating portion, and forming a connection electrode; and dividing the substrate. Forming a plurality of LED elements; and connecting the connection electrodes of the respective LED elements so as to face the wiring on the wiring board.
るものであることを特徴とする請求項1記載のLED表
示装置の製造方法。2. The method for manufacturing an LED display device according to claim 1, wherein the application of the conductive resin is performed by a printing method.
赤および緑の3色発光用のLEDチップ部を個々に形成
した後、各LEDチップ部のチップ接続面上に、それぞ
れ素子接続面の高さが等しい接続電極を形成して、各L
ED素子を形成して、配線基板上に配置することを特徴
とする請求項1記載のLED表示装置の製造方法。3. The p-type layer and the n-type layer are made of different blue materials,
After individually forming LED chips for emitting three colors of red and green, connection electrodes having the same height of the element connection surface are formed on the chip connection surfaces of the LED chip portions, respectively.
2. The method according to claim 1, wherein an ED element is formed and arranged on a wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31668896A JP3342322B2 (en) | 1996-11-27 | 1996-11-27 | Method for manufacturing LED element display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31668896A JP3342322B2 (en) | 1996-11-27 | 1996-11-27 | Method for manufacturing LED element display device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10163536A JPH10163536A (en) | 1998-06-19 |
JP3342322B2 true JP3342322B2 (en) | 2002-11-05 |
Family
ID=18079806
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31668896A Expired - Fee Related JP3342322B2 (en) | 1996-11-27 | 1996-11-27 | Method for manufacturing LED element display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3342322B2 (en) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3906653B2 (en) * | 2000-07-18 | 2007-04-18 | ソニー株式会社 | Image display device and manufacturing method thereof |
JP4461616B2 (en) | 2000-12-14 | 2010-05-12 | ソニー株式会社 | Element transfer method, element holding substrate forming method, and element holding substrate |
JP4649745B2 (en) | 2001-02-01 | 2011-03-16 | ソニー株式会社 | Light-emitting element transfer method |
WO2002084631A1 (en) * | 2001-04-11 | 2002-10-24 | Sony Corporation | Element transfer method, element arrangmenet method using the same, and image display apparatus production method |
JP2003005674A (en) * | 2001-06-18 | 2003-01-08 | Sony Corp | Display element and image display device |
JP2003045901A (en) | 2001-08-01 | 2003-02-14 | Sony Corp | Method for transferring element and method for arraying element using the same, and method for manufacturing image display unit |
JP2003077940A (en) | 2001-09-06 | 2003-03-14 | Sony Corp | Device transfer method, device array method using the same, and image display device manufacturing method |
JP4120223B2 (en) * | 2002-01-16 | 2008-07-16 | ソニー株式会社 | Electronic component manufacturing method and image display apparatus using the same |
JP3924756B2 (en) | 2002-01-21 | 2007-06-06 | 松下電器産業株式会社 | Manufacturing method of nitride semiconductor laser device |
KR100964399B1 (en) * | 2003-03-08 | 2010-06-17 | 삼성전자주식회사 | Semiconductor laser diode and semiconductor laser diode assembly using same |
NL1029688C2 (en) * | 2005-08-05 | 2007-02-06 | Lemnis Lighting Ip Gmbh | Method for manufacturing an electrical circuit provided with a plurality of LEDs. |
JPWO2007083378A1 (en) * | 2006-01-20 | 2009-06-11 | 富士通株式会社 | Chip component mounting structure, mounting method, and electronic apparatus |
US8159449B2 (en) * | 2006-04-14 | 2012-04-17 | Semiconductor Energy Laboratory Co., Ltd. | Display device having light-emitting element and liquid crystal element and method for driving the same |
JP4811669B2 (en) * | 2007-06-22 | 2011-11-09 | 日本精機株式会社 | Printed wiring board |
US7985979B2 (en) | 2007-12-19 | 2011-07-26 | Koninklijke Philips Electronics, N.V. | Semiconductor light emitting device with light extraction structures |
JP4724222B2 (en) | 2008-12-12 | 2011-07-13 | 株式会社東芝 | Method for manufacturing light emitting device |
JP2011071272A (en) | 2009-09-25 | 2011-04-07 | Toshiba Corp | Semiconductor light-emitting device and method for manufacturing the same |
JP5378130B2 (en) | 2009-09-25 | 2013-12-25 | 株式会社東芝 | Semiconductor light emitting device |
JP5414579B2 (en) | 2009-11-19 | 2014-02-12 | 株式会社東芝 | Semiconductor light emitting device |
JP5349260B2 (en) | 2009-11-19 | 2013-11-20 | 株式会社東芝 | Semiconductor light emitting device and manufacturing method thereof |
JP5537446B2 (en) | 2011-01-14 | 2014-07-02 | 株式会社東芝 | Light emitting device, light emitting module, and method of manufacturing light emitting device |
JP5603793B2 (en) | 2011-02-09 | 2014-10-08 | 株式会社東芝 | Semiconductor light emitting device |
WO2016047133A1 (en) | 2014-09-26 | 2016-03-31 | 東芝ホクト電子株式会社 | Light-emission module |
WO2018030695A1 (en) | 2016-08-11 | 2018-02-15 | 주식회사 루멘스 | Led module and method for preparing same |
JP6170232B1 (en) * | 2016-08-11 | 2017-07-26 | ルーメンス カンパニー リミテッド | Display module including an array of LED chip groups and manufacturing method thereof |
-
1996
- 1996-11-27 JP JP31668896A patent/JP3342322B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH10163536A (en) | 1998-06-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3342322B2 (en) | Method for manufacturing LED element display device | |
JP3195720B2 (en) | Multicolor LED element, LED display device using the multicolor LED element, and method of manufacturing multicolor LED element | |
US10790267B2 (en) | Light emitting element for pixel and LED display module | |
US20070051966A1 (en) | Light emitting diode and method for manufacturing the same | |
JP2005116998A (en) | Wavelength conversion type light emitting diode package using phosphor and manufacturing method | |
KR20110000730A (en) | Method of Manufacturing Surface Mount LED Module and Surface Mount LED Module | |
KR20100087329A (en) | Chip scale stacked die package | |
CN112310136B (en) | Passive micro-LED array device with uniform brightness | |
JP2002094123A (en) | Surface-mounted light emitting diode and its manufacturing method | |
CN102959747A (en) | Light-emitting device and manufacturing method therefor | |
TWI420630B (en) | Semiconductor package structure and semiconductor package process | |
JP2000332055A (en) | Flip-chip mounting structure and mounting method | |
JP3685633B2 (en) | Chip-type light emitting device and manufacturing method thereof | |
JPH10150119A (en) | Manufacture of semiconductor device | |
JP3604108B2 (en) | Manufacturing method of chip type optical semiconductor | |
JP2017157593A (en) | Light-emitting diode, manufacturing method for light-emitting diode, light-emitting diode display device, and manufacturing method for light-emitting diode display device | |
TWI661584B (en) | Light emitting chip, packaged structure and associated manufacturing method | |
US10290563B2 (en) | Semiconductor device including die pad with projections | |
KR100616680B1 (en) | Light emitting diode package and manufacturing method thereof | |
JP2012044034A (en) | Semiconductor light-emitting device and semiconductor light-emitting device manufacturing method | |
CN114725080B (en) | Light emitting unit, display device and preparation method thereof | |
JPH11150295A (en) | Semiconductor light emitting device, method of manufacturing semiconductor light emitting device, and display device | |
TWI775682B (en) | Light source element, preparation method of light source element, and display device | |
KR102325808B1 (en) | Semiconductor light emitting device and method of manufacturing the same | |
JP4617846B2 (en) | Semiconductor light emitting device, manufacturing method thereof, and manufacturing method of image display device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070823 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080823 Year of fee payment: 6 |
|
LAPS | Cancellation because of no payment of annual fees |