JP3335620B2 - Microcomputer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly, to a microcomputer device that executes a program changed when an address to be corrected in a read-only memory is executed.

[Prior Art] In general, a conventional one-chip microcomputer includes:
As shown in FIG. 12, it has a program counter PC, a program memory PM in which a predetermined program is written, and an instruction decoder ID. As is well known, the operation of this one-chip microcomputer is performed by a program memory PM whose address is designated by a program counter PC which counts up by a system lock (not shown).
A program is executed by the data read from the memory being decoded by the instruction decoder ID.

As the program memory PM, a mask ROM (read only memory) is generally used, and a program is written in the mask ROM by a maker in a manufacturing process of the maker and cannot be rewritten by a user.

Recently, a one-time ROM that can be rewritten only once by a user has been sold.

[Problems to be Solved by the Invention] However, when a bug or the like is found in a program for writing a mask ROM after manufacturing a one-chip microcomputer or when a part of the program is desired to be corrected, the mask pattern of the ROM is rewritten again. Since it is necessary to restart the manufacturing process of the integrated circuit, it takes several months to obtain a modified one-chip microcomputer at present.

Moreover, a one-chip microcomputer in which a bug or the like is found in a mask ROM writing program cannot be reused, and a one-time ROM is very expensive compared to a mask ROM. It takes a very long time and is not suitable for mass production.

The present invention has been made in view of such a problem, and rewrites the contents of a read-only memory when a bug or the like is found in a write program of the read-only memory or when a part thereof is to be corrected. It is another object of the present invention to provide a microcomputer which can modify a program by partially rewriting the program in a pseudo manner, or can substantially add or delete a program by performing an interrupt process.

[Means for Solving the Problems] A microcomputer device of the present invention comprises a program counter, a read-only memory for storing an execution program, first address data corresponding to a portion of the execution program to be corrected, and a jump destination. A second address data corresponding to an address and means for comparing the value of the program counter with the first address data are held as one set, and the value of the program counter and the first address data are held. And control means for controlling to rewrite the value of the program counter to the second address data when a match with the second address data is detected.

Further, the microcomputer device of the present invention includes a program counter, a read-only memory for storing an execution program, and a predetermined control code and an address of one.
A storage means for storing the data in the form of a pair, and an operation corresponding to the control code stored in the storage means when an interrupt process occurs during execution of the execution program. And control means for controlling the execution. In this case, a plurality of types of codes are defined as the control codes, and the codes are codes corresponding to at least a subroutine call and a jump.

[Operation] When a bug or the like is found in the write program of the read-only memory or when a part of the bug is to be corrected, the address data corresponding to the address to be corrected in the read-only memory and the corrected program data are stored in a nonvolatile manner. By storing the data in the memory, when the address data stored in the non-volatile memory matches the program counter, the program data to be corrected in the read-only memory is replaced with the corrected data stored in the non-volatile memory. The program data is output to the instruction decoder, and the program in which a bug or the like is corrected is executed.

Also, if a bug is found in the write program of read-only memory or if you want to correct a part of it,
By storing the address data corresponding to the address to be corrected in the read-only memory and the program data for the interrupt to be corrected in the non-volatile memory, the address data stored in the non-volatile memory matches the program counter. In this case, the interrupt processing is performed based on the interrupt program data stored in the nonvolatile memory instead of the program data to be corrected in the read-only memory. In this interrupt processing, it is possible to rewrite the data in the memory, call a subroutine for the function you want to add, change the flow of the processing up to that point by unconditional jump, etc., and add or delete a program substantially. The program can be modified.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

First, the concept of the microcomputer of the present invention will be described with reference to FIG. FIG. 1 shows a one-chip microcomputer, for example, 1 is a program counter, 2 is a program memory in which a predetermined program is written using, for example, a mask ROM, and 3 is an electrically writable nonvolatile memory. A non-volatile memory (for example, an EPROM, an EEPROM, etc .; hereinafter, abbreviated as EROM), 4 is a selector, and 5 is an instruction decoder.

The program counter 1 is connected to give an address value not only to the program memory 2 but also to the EROM 3. When a bug or the like is found in a program to be written in the program memory 2 or when a part of the program is to be corrected, the EROM 3 writes the address data corresponding to the address to be corrected in the program memory 2 and the program data to be corrected. It is rare. The selector 4 normally selects the output data of the program memory 2 and inputs the output data to the instruction decoder 5, but when the address data stored in the EROM 3 matches the output content of the program counter 1,
When the program data is output from 3, the output data of the EROM 3 (corrected program data) is selected instead of the output data of the program memory 2 (program data to be corrected) and input to the instruction decoder 5. ing.

Next, the operation of the microcomputer shown in FIG. 1 will be described. The operation of this microcomputer is basically the same as that of a conventional microcomputer, but a part of a program to be written into the program memory 2 is rewritten in a pseudo manner to modify the program. I have.

That is, normally, data read from the program memory 2 whose address is designated by the program counter 1 which counts up by a system lock (not shown) is selected by the selector 4 and the instruction decoder 5
The program is executed by being decoded. However, if the program data is output from EROM3 when the address data stored in EROM3 matches the output content of program counter 1, this EROM3
Of the program memory 2 is selected by the selector 4 in place of the output data of the program memory 2 (program data to be corrected) and input to the instruction decoder 5. Thereby, the pseudo rewritten program is decoded by the instruction decoder 5, and the corrected program is executed.

FIG. 2 and FIG. 3 show a first embodiment of the microcomputer of the present invention. FIG. 2 shows, for example, a one-chip microcomputer, and 6 shows an EROM3
The selector 4 'is constituted by, for example, a multiplexer so as to select a data in response to a data switching control signal from the EROM 3, and the others are provided by the microcomputer shown in FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

The operation of the one-chip microcomputer shown in FIG. 2 is the same as the operation described above with reference to FIG. 1, and will not be described in detail. Hereinafter, the operation of the write control unit 6 will be mainly described. When a bug or the like is found in the writing program in the program memory 2 or when a part of the bug is to be corrected, a writing permission signal is given from the writing control unit 6 to the EROM 3 so that the EROM 3 can write data. further,
When the write controller 6 designates an EROM address and gives EROM data to the EROM 3 to activate the write signal, the EROM data is written to the EROM 3. In this case, the EROM data is the address data and the program data for correction as described above. The address data and the program data for correction may be simultaneously written to the same EROM address, or may be sequentially written to different EROM addresses. May be written.

FIG. 3 shows a specific example of a part of the EROM 3 in FIG. 2, and has a plurality (n) of data correction blocks 31 to 3n provided corresponding to a desired number of data corrections. In each of the blocks 31 to 3n, an address data area 32 and a program data area 33 are secured as a pair of memory areas each using an electrically writable nonvolatile memory element. In the area 33, address data corresponding to a specific address of the program memory 2 where the program data to be corrected is written and program data corrected as the content of the specific address are written correspondingly.

Further, one data judgment circuit 34 is provided for the address data area 32 and the program data area 33, and this data judgment circuit 34
A comparison is made between the address input from the controller and the address stored in the address data area 32, and when a match occurs, the match signal output is activated to output the program data (correction data) stored in the program data area 33. Control.

Since the data correction locations (addresses) assigned to the blocks 31 to 3n are different from each other, the correction data is output from one of the blocks at the time of data correction.

The output data (correction data) of each of the blocks 31 to 3n is input to the selector 4 via a common bus, and the coincidence signal output of each of the blocks 31 to 3n is input to an OR circuit 35. The output becomes a switching control input to the selector 4, and the output data of the EROM3 is the output data of the program memory 2 (program data to be corrected).
Instead of.

Since the EROM 3 can cover all the addresses of the program memory 2, the EROM capacity can be reduced,
The price increase of the one-chip microcomputer due to the addition of the OM is only slight.

Next, a description will be given of a microcomputer according to a second embodiment of the present invention. The second embodiment is different from the first embodiment in that the ER
The OM 3 'and the selector 4 "are different, and the other components are the same, and thus are denoted by the same reference numerals as in the first embodiment.
Is configured so that the OR circuit 35 in FIG. 3 is omitted and the data switching control signal is not output. As a result of the address comparison determination, the correction data is output from the program data area 33 when the addresses match, but when the addresses do not match. It is configured to output predetermined fixed data (for example, NOP code or the like) when (data correction is not necessary).

Selector 4 "is configured to select data without receiving the data switching control signal, for example, as shown in FIG. 4. That is, in FIG.
The data from OM3 'is input to the data determination circuit 41 and the multiplexer 42, and the data from the program memory 2 is input to the multiplexer 42. Data judgment circuit 41
Stores the same fixed data as the fixed data output when the address of the EROM 3 'does not match, compares and judges the stored data with the input data, and when they do not match (when data correction is necessary), the switching control signal The output is made inactive, and at the time of coincidence (when data correction is not necessary), the switching control signal output is activated.

When the switching control signal input from the data determination circuit 41 is in an inactive state (when data correction is necessary), the multiplexer 42 outputs the correction data from the EROM 3 'to the output data of the program memory 2 (the program to be corrected). (Data) instead of data, and when the switching control signal input from the data determination circuit 41 is in the active state (when data correction is not necessary)
, The output data of the program memory 2 (in this case, the program data that does not require data correction) is selected and output as it is.

FIG. 5 shows a third embodiment of the microcomputer of the present invention. FIG. 5 shows a microcomputer of one chip, for example. Compared with the microcomputer described above with reference to FIG. 2, (a) In the EROM 53, a bug or the like was found in the writing program of the program memory 2. When a case or a part of the case is to be corrected, the address data corresponding to the address to be corrected in the program memory 2 and the program data for interrupt processing to be corrected are written. The point that the output (address value) and the address data stored in the EROM 53 are given to the coincidence detecting section 54, (c)
When the match detection unit 54 detects a match between the two inputs, the interrupt processing program data stored in the EROM 53 is input to the interrupt generation circuit 55, and the value of the program counter 1 is rewritten by the interrupt generation circuit 55. (D) The selector (FIG. 4) is omitted, and data read from the program memory 2 is input to the instruction decoder 5 without passing through the selector. Therefore, the same reference numerals as in FIG. 2 are used.
The EROM 53 is connected to a system bus (not shown) of the microcomputer.

Next, the operation of the microcomputer shown in FIG. 5 will be described. The operation of this microcomputer is basically the same as the operation of a conventional microcomputer, but an interrupt process is generated at an arbitrary program position, and the program can be modified by the interrupt process.

That is, first, the operation of the write control unit 56 will be described. When a bug or the like is found in the writing program of the program memory 2 or when a part of the bug is to be corrected, when the writing control unit 56 gives a writing permission signal to the EROM 53,
The EROM 53 can write data. Further, when the write control unit 56 specifies the EROM address and gives the EROM data to the EROM 53 to activate the write signal,
The EROM data is written in the EROM 53. In this case, ER
The OM data is the address data as described above and the program data for an interrupt for correction, and the address data and the program data for the interrupt are the same.
The data may be written to the EROM addresses at the same time, or may be sequentially written to different EROM addresses.

During a normal operation, the instruction decoder 5 decodes data read from the program memory 2 whose address is designated by the program counter 1 which counts up by a system clock (not shown), thereby executing a program. . But,
When the address data stored in the EROM 53 matches the output content of the program counter 1, an interrupt occurs, the value of the program counter 1 is rewritten, and an interrupt process is performed. In this case, various processing (such as rewriting of memory data, calling of a subroutine of a function to be added, unconditional jumping, etc.) is performed based on the program data for interrupt for correction output from the EROM 53. Thus, the flow of processing up to that point is changed, and programs are substantially added or deleted.

As described above, in the microcomputers of the first embodiment and the second embodiment, the number of steps of the program before the correction and the number of steps of the program of the number of corrections need to match. In the microcomputer, even if the number of steps before and after the modification of the program does not match, not only the change of the program but also the addition or deletion of the program and the execution of another program become possible.

Since the EROM 53 can cover all the addresses of the program memory 2, the capacity of the EROM is small, and the ER
The price increase of the one-chip microcomputer due to the addition of the OM is only slight.

Next, the data configuration of the EROM 53 and the flow of interrupt processing will be described with reference to FIGS. 6 and 7. FIG. EROM
As shown in FIG. 6, the data structure of the 53 program data area is such that a plurality of pairs of an address data containing an address for generating an interrupt and a code part and an address data part are successively written. It is rare. In the interrupt processing, as shown in the flow chart of FIG. 7, first, the value of the code part is checked, and the processing to be performed is selected according to the value. When the value of the code part is "1", the adjustment program is executed. When the value of the code part is "2", the subroutine of the address of the address / data part is called, and the value of the code part is " When the value is "3", data is written to the address of the address / data part. When the value of the code part is "4", the data of the address of the address / data part is read. When the value of the code part is "5". Jumps to the address of the address / data portion, and returns when the value of the code portion is other than 5, for example, 6. The return from interrupt processing is
This can be easily performed by rewriting the return address saved in the stack (not shown) and returning. Of course, the data in the EROM 53 may be replaced with a normal instruction code to be executed. Since there are six codes that can be modified, a very small flow is sufficient for the interrupt processing program. Needless to say, the code of the interrupt processing may be added as needed for the product to provide more flexibility.

FIG. 8 is a flowchart showing the contents of the adjustment program. First, the adjustment flag is set to “0”. Next, if an adjuster (not shown) is not connected, the process returns. If connected, communication is performed with the adjuster. As shown in FIG. 9, the communication data used in this communication is composed of an adjustment code section, an address section, and a data section. When the value of the adjustment code section is "1", the address data section Call the subroutine at address
When the value of the adjustment code part is "2", the data of the data part is written to the address of the address data part, and when the value of the adjustment code part is "3", the data of the address of the address data part is adjusted. When the value of the adjustment code part is "4", the control jumps to the address of the address / data part.

When the value of the adjustment code part is other than “4”, it is checked whether the adjustment flag is “1”. If the adjustment flag remains “0”, the process returns. If the adjustment flag is “1”, communication is performed. Is repeated. As described above, the adjustment flag is initially set to “0”.
Is normally set, only one adjustment process is performed. When the adjustment process is continuously performed a plurality of times, in the step of writing the data of the data portion to the address of the address data portion, adjustment is performed in the communication step with the adjuster so that the value of the adjustment flag is written to “1”. Communication is performed from the device, and the value of the adjustment flag is set to “1”. The adjuster writes the address of the position to be adjusted and the adjustment code “1” into the EROM 53, and waits for the adjustment communication to be performed. When the address of the EROM 53 matches the address of the program being executed, the microcomputer generates an interrupt and performs communication because the adjustment code is “1”. The coordinator writes the contents to be adjusted in the communication data. When it is desired to execute a plurality of subroutines in the adjustment, the adjustment code is rewritten to "1" in the first communication, and the subroutine call is repeated in the plurality of communication. As a result, it is possible to make adjustments in all steps of the product program in a product state. Not only that, the addition of adjustment points can be easily performed by rewriting the contents of the EROM 53.

In the above-described third embodiment, an example in which a software interrupt is performed has been described. In the fourth embodiment illustrated in FIG. 10, an example in which a hardware interrupt is performed is illustrated. The fourth embodiment has an address data area 11i (i = a,... N) and a plurality of sets each including one of the vector table 12i and the coincidence detecting means 13i.
The vector table 12i is contained in the EROM. The address at which an interrupt is to be generated is written in the address data area 11i, and the start address of the interrupt processing is written in the vector table 12i. The value of the program counter 1 is input to a plurality of sets of coincidence detecting means 13i.
An output permission signal is sent to the vector table 12i of the same set as i, and only the data output of the vector table 12i is transmitted to the program counter value changing means 14.

Further, each output of the plurality of sets of match detecting means 13i is input to an interrupt generation circuit 16 via an OR circuit 15, a match is detected in any of the plurality of sets, and the content of the interrupt enable flag is enabled. In this case, an interrupt occurs, and the value of the vector table 12i of the matched set is written into the program counter 1 by the program counter value changing means 14. At this time, it goes without saying that the value of the program counter 1 is simultaneously saved in a stack (not shown). Also, if the contents of the interrupt permission flag are prohibited, it goes without saying that no interrupt occurs and the value of the program counter 1 does not change.

FIG. 11 shows a memory map in the fourth embodiment. A normal program is written in the ROM area, and the EROM does not need to be particularly used. To change the program in the ROM area, the addresses to be changed are sequentially written into the address data areas 11a, 11b, 11c,... Of the EROM area, and the start address of the processing to be performed at that time is stored in the vector table 12.
Write in a, 12b, 12c… If the required subroutine is already in the ROM area, the start address of the subroutine may be written.If the required subroutine is not in the ROM area, a new subroutine is added to the EROM area and the start address is added. Is written to the vector table.

The number of addresses that generate an interrupt is in the address data area.
It is determined by the number of 11i, but 5 is enough for normal products.

In each of the above embodiments, the control system of the write control units 6 and 56 may be a dual-purpose terminal system that switches when an external terminal (port terminal or the like) of the one-chip microcomputer is set to the write mode. Alternatively, the program may be written by a program.

Further, in each of the above embodiments, the EROM is built in the microcomputer, but the EROM may be externally inherited by the microcomputer. In each of the above embodiments, it is needless to say that a non-volatile memory includes a normal RAM in a system in which a power supply is always backed up.

[Effects of the Invention] As described above in detail, according to the microcomputer of the present invention, when a bug or the like is found in a program written in a program memory or when a part of the bug is to be corrected, the contents of the program memory are rewritten. Without modifying the program, the program can be modified by partially rewriting the program in a pseudo manner, or by adding or deleting a program by performing an interrupt process.

Therefore, a microcomputer in which a bug or the like has been found can be reused, and it is not necessary to recreate the program memory again, so that the generation process is not affected, and a corrected microcomputer can be obtained in a short time. Can be. Actually, when correcting a bug or the like, it is often sufficient to correct a program of one or two lines, and thus the microcomputer of the present invention is extremely useful.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing the concept of a microcomputer of the present invention, FIG. 2 is a block diagram showing a first embodiment of the microcomputer of the present invention, and FIG. 3 is a part of the configuration of an EROM in FIG. FIG. 4 is a block diagram showing a selector used in a second embodiment of the microcomputer of the present invention. FIG. 5 is a block diagram showing a third embodiment of the microcomputer of the present invention. Fig. 6 shows the EROM in Fig. 5.
FIG. 7 is a flow chart showing an example of interrupt processing in the microcomputer of FIG. 5, FIG. 8 is a flow chart showing the contents of an adjustment program in FIG. 7, FIG. 9 is a diagram for explaining the configuration of data used for communication when the adjustment program in FIG. 8 is executed, FIG. 10 is a block diagram showing a microcomputer according to a fourth embodiment of the present invention, and FIG. FIG. 11 is a diagram showing a memory map in the microcomputer of FIG. 10, and FIG. 12 is a block diagram showing a conventional one-chip microcomputer. 1 ... program counter, 2 ... program memory,
3,3 ', 53 …… Electrically writable nonvolatile memory, 4,
4 ', 4 "selector, 5 instruction decoder, 6 write control unit, 11i address data area, 12i vector table, 13i match detecting means, 14 program counter value changing means , 15 ... OR circuit, 16 ... interrupt generation circuit, 32 ... address data area, 33 ... program data area, 34 ... data determination circuit, 35 ... OR circuit,
41: Data determination circuit, 42: Multiplexer, 54:
Match detection unit, 55: interrupt generation circuit, 56: write control unit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-145596 (JP, A) JP-A-62-219126 (JP, A) JP-A-55-43641 (JP, A) JP-A-49-1979 107645 (JP, A) JP-A-63-44241 (JP, A) JP-A-62-15200 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/06 G06F 15 / 78 JOIS

Claims (3)

(57) [Claims] A program counter; a read-only memory for storing an execution program; first address data corresponding to a location to be corrected in the execution program; second address data corresponding to a jump address; Means for comparing the value of the program counter with the first address data is held as one set, and when a match between the value of the program counter and the first address data is detected, And a control means for controlling the value of the second address data to be rewritten to the second address data. 2. A program counter, a read-only memory for storing an execution program, storage means for storing a predetermined control code and an address in a pair, and an interrupt processing during execution of the execution program And a control means for controlling an operation corresponding to the control code stored in the storage means to be executed on data at an address destination which is a pair, when the error occurs. 3. The microcomputer device according to claim 2, wherein a plurality of types of codes are defined as the control code, and the codes are codes corresponding to at least subroutine calls and jumps.