JP3331754B2 - Charging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charging device provided with a rectifier using a MOS transistor. The charging device of the present invention is applied to, for example, a charging device that rectifies an AC power generation voltage of an automotive alternator (AC generator) to charge a battery.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. Hei 4-138030 discloses FIG.
Has proposed a three-phase full-wave rectifier using a MOS power transistor. This three-phase full-wave rectifier 3 has M
High-side switches 31 to 3 composed of OS transistors
3 and three sets of low-side switches 34 to 36 are connected in series, and three sets of phase inverter circuits 37 to 39 are connected in parallel, and a pair of DC power terminals are individually connected to the high and low ends of the battery 7. , Each phase inverter circuit 37-3
The connection points 41 to 43 of the two switches 9, that is, the AC input terminals are individually connected to the respective phase output terminals of the armature windings 11 to 13 of the AC generator 1. 2 is a field coil, 4 is a field current control transistor, 5 is a flywheel diode, and 6 is a controller.

In this prior art embodiment, the NMO
Low-side switches 34 to 36 composed of S transistors
The main electrode (shown as S) on the battery lower terminal side is connected to a P-type region (referred to as a substrate region) immediately below a channel to apply a potential to this substrate region, and similarly, the high-side switches 31 to 33 composed of NMOS transistors The main electrode (illustrated as S) on the stator coil side of P
It is connected to a mold region (substrate region) to apply a potential to this substrate region.

[0004]

[0005]

In the conventional diode-rectified three-phase full-wave rectifier or the MOS transistor-type three-phase full-wave rectifier 3, the charging line 8 of the battery 7 is disconnected or the overload of the vehicle load 9 is exceeded. If the output current of the three-phase full-wave rectifier suddenly decreases due to blowing of the protective fuse 10 or the like, the transistor 4 is turned off in response to the reduction of the field current. To continue refluxing for a predetermined time at 5,
In addition, a large pulse voltage (hereinafter, referred to as a G pulse voltage) is generated because the magnetic energy accumulated in the magnetic circuit in which the armature windings 11 to 13 link is generated as an induced voltage in the armature windings 11 to 13. The voltage is applied to the vehicle load 9 through the channels of the MOS transistors 31 to 36 or the parasitic diode.

For this reason, conventionally, there has been a problem that an important vehicle load must be provided with a surge countermeasure, that is, a G pulse voltage blocking countermeasure. The present invention has been made in view of the above circumstances, and the generated current has been rapidly reduced. It is an object of the present invention to provide a charging device including a rectifier capable of preventing a G pulse voltage generated at the generator from being transmitted to a battery.

[0007]

[0008]

[0009]

[0010]

The first aspect of the charging device of the present invention is described below.
Is composed of a required number of phase inverter circuits connected in series with a high-side switch and a low-side switch composed of N-channel MOS transistors, and a pair of DC output terminals are individually connected to both ends of a battery and a load. A rectifier in which the connection point of the two switches is individually connected to each phase output terminal of the armature winding of the AC generator, and a control unit that controls the gate potential of each switch to turn the switches on and off. In the charging device provided, a substrate region composed of a P-type region immediately below a gate electrode of the high-side switch is connected to a lower end of the battery.

According to a second configuration of the present invention, in the first configuration, the control unit detects a phase voltage at each phase output terminal of the AC generator, and any one of the phase voltages is detected. A surge voltage cutoff mode is provided in which at least the high side switch group is cut off when the voltage exceeds a predetermined voltage value. The third configuration of the present invention is characterized in that, in the second configuration, the control unit keeps the surge voltage cutoff mode for a predetermined time.

According to a fourth configuration of the present invention, in the above-mentioned second configuration, the control unit maintains the surge voltage cutoff mode while any one of the phase voltages exceeds a predetermined voltage value. It is characterized by having. The fifth of the present invention
In the second configuration, the control unit may further include, among the high-side switches, the phase voltage applied to an N-type armature winding side region forming a main electrode on a connection point side. The high side switch which is higher than the voltage of the battery is turned on.

According to a sixth aspect of the present invention, in the above-mentioned second aspect, the control section further applies the voltage to an N-type armature winding-side region forming a main electrode on the connection point side among the low-side switches. And turning on the low-side switch in which the phase voltage is lower than the voltage of the battery. According to a seventh configuration of the present invention, in the second configuration, a first parasitic diode between an N-type battery-side region forming the main electrode on the battery side of the high-side switch and the substrate region is further provided. It has a withstand voltage exceeding the maximum rated voltage value of the battery.

In an eighth aspect of the present invention, in the above-mentioned second aspect, further, an N-type armature winding-side region forming a main electrode on the connection point side of the high-side switch and the substrate region are provided. 2 The parasitic diode has a predetermined G exceeding the maximum generated voltage.
It is characterized by having a withstand voltage exceeding the pulse voltage value. According to a ninth configuration of the present invention, in the second configuration, the third parasitic diode between the N-type armature winding side region forming the main electrode on the connection point side of the low side switch and the substrate region is further provided. And has a withstand voltage exceeding a predetermined G pulse voltage value exceeding the maximum power generation voltage.

[0015] A tenth configuration of the present invention is the above-mentioned seventh configuration, further comprising: the MO as the high-side switch.
One of the two N-type regions forming the main electrode of the S transistor has an N ⁻ -type breakdown voltage layer, and the N ⁻ -type breakdown voltage layer is formed on the first parasitic diode side. According to an eleventh configuration of the present invention, in the eighth configuration, one of the two N-type regions forming the main electrode of the MOS transistor forming the high-side switch has an N ⁻ -type breakdown voltage layer, The N ⁻ -type breakdown voltage layer is formed on the side of the second parasitic diode.

A twelfth configuration of the present invention is the ninth configuration, further comprising the low-side switch.
One of the two N-type regions forming the main electrode of the S transistor has an N ⁻ -type breakdown voltage layer, and the N ⁻ -type breakdown voltage layer is formed on the third parasitic diode side. According to a thirteenth configuration of the present invention, in the second configuration, the high-side switch and the low-side switch forming the phase inverter circuit of the same phase are integrated on the same chip having an N-type region as a substrate. The substrate region is connected to a phase output terminal of the alternator.

According to a fourteenth configuration of the present invention, in the second configuration, the control unit turns off all the high-side switches and turns on the low-side switches when the surge voltage cutoff mode is performed. It is characterized by being .

[0018]

[0019]

[0020]

[0021]

According to the first structure of the present invention,
Since the substrate region consisting of the P-type region immediately below the gate electrode of the high-side switch is connected to the lower end of the battery, the N-type armature winding-side region and the substrate region (the main electrode on the connection point side of the high-side switch) A second parasitic diode formed by a PN junction with the semiconductor region immediately below the gate electrode) causes a G pulse voltage generated in the armature winding to be equal to a first pulse to be described later.
Since it is prevented from being applied to the load through the parasitic diode, it is not necessary to take measures to protect each load from the G pulse voltage. The first parasitic diode is a parasitic diode formed by a PN junction between an N-type battery-side region serving as a battery-side main electrode of the high-side switch and a substrate region (a semiconductor region immediately below a gate electrode). .

According to the second configuration of the present invention, in the first configuration, when any of the phase voltages at the output terminals of each phase of the AC generator exceeds a predetermined voltage value, at least the high-side switch group is switched. Since the cutoff prevents the G pulse voltage from being applied to the load through the channel region formed in the high-side switch during the ON operation, it is not necessary to take measures to protect each load from the G pulse voltage.

According to the third configuration of the present invention, in the above-mentioned second configuration, the high-side switch group is cut off for a predetermined time sufficient for the surge voltage to decrease from the time of detecting the surge voltage. When the side switch is turned on again, the remaining surge voltage is not applied to the load.
According to the fourth configuration of the present invention, the high-side switch group is turned off while any one of the phase voltages at the phase output terminals of the AC generator exceeds a predetermined voltage value in the second configuration. , G pulse voltage can be reliably blocked regardless of the G pulse voltage duration.

According to the fifth configuration of the present invention, the high-side switch in a state where the phase voltage applied to the N-type armature winding side region is higher than the battery voltage is further turned on in the second configuration. Otherwise, the battery turns off, so that no reverse current flows from the battery to the armature winding. According to the sixth configuration of the present invention, the low-side switch in which the phase voltage applied to the N-type armature winding side region is lower than the battery voltage is turned on in the second configuration, and is turned off otherwise, There is no current backflow from the battery to the armature winding.

According to a seventh configuration of the present invention, in the second configuration, the first parasitic diode between the N-type battery-side region of the high-side switch and the substrate region exceeds the maximum rated voltage value of the battery. Since it has a withstand voltage, the first parasitic diode does not break down due to the battery voltage even when the generated voltage is 0V. According to the eighth configuration of the present invention, in the second configuration, the second parasitic diode between the N-type armature winding side region of the high-side switch and the substrate region further includes a predetermined G pulse voltage value. , The surge voltage up to the G pulse voltage value can be prevented from being applied to the load.

According to a ninth configuration of the present invention, in the second configuration, the third parasitic diode between the N-type armature winding side region of the low-side switch and the substrate region further includes a predetermined G pulse. Since it has a withstand voltage exceeding the voltage value,
It is possible to prevent a surge voltage up to the pulse voltage value from being applied to the load. According to the tenth configuration of the present invention, since the N ⁻ -type breakdown voltage layer of the high-side switch is formed on the first parasitic diode side in the seventh configuration, the withstand pressure of the first parasitic diode is increased. be able to.

According to the eleventh configuration of the present invention, the eighth aspect
Further, since the N ⁻ -type breakdown voltage layer of the high-side switch is formed on the second parasitic diode side, the breakdown voltage of the second parasitic diode that must withstand the G pulse voltage can be increased. According to the twelfth configuration of the present invention,
In the ninth configuration, the low-side switch N
^- Since -type withstand voltage layer is formed in the third parasitic diode side,
The pressure resistance of the third parasitic diode, which must withstand the G pulse voltage, can be increased.

According to the thirteenth structure of the present invention, the second structure
In addition, in the configuration described above, a pair of high-side switch and low-side switch forming a phase inverter circuit of the same phase are integrated on the same chip, so that the structure and wiring are simplified, and downsizing can be realized. According to the fourteenth configuration of the present invention, in the second configuration, all the high-side switches are turned off when the surge voltage cutoff mode is performed.
Turn on the low side switch. By doing so, the armature windings of each phase are short-circuited through the on-resistance of each low-side switch, so that surge power can be consumed without increasing the B voltage of the battery, and the G pulse voltage can be reduced. An increase can be prevented.

[0029]

[0030]

[0031]

[0032]

[0033]

[0034] Note that according to the first to the first 4 configuration described above of the present invention, in the case of normal control the field current in the switching transistor, the switching transistor or the exciting current control circuit for the field current control Even if the system becomes abnormal and the field current control malfunctions, the battery voltage can be controlled well by controlling the MOS transistor of the three-phase full-wave rectifier, preventing overcharging of the battery. Can be.

[0035]

【Example】

(Embodiment 1) An embodiment of the charging device of the present invention used in a vehicle alternator will be described below with reference to FIG. Reference numeral 1 denotes a three-phase AC generator for a vehicle, and armature windings 11 to 1 thereof are provided.
3 are connected to AC input terminals (connection points to be described later) 41 to 43 of the three-phase full-wave rectifier 3, and a pair of DC output terminals of the three-phase full-wave rectifier 3 are connected to a battery 7. Connected to both ends. A load 9 is connected to both ends of the battery 7 via a fuse 10.

Reference numeral 2 denotes a field coil having one end connected to the high-order end of the battery 7, and the other end connected to the collector of the field current control transistor whose emitter is grounded. 5 is a flywheel diode, 6 is a controller, and the controller 6 is a high terminal voltage (B
Voltage) to control the field current by intermittently controlling the transistor 4, thereby controlling the armature windings 11-1.
3 is controlled. The controller 6
Controls the transistors 31 to 36 of the three-phase full-wave rectifier 3 intermittently to perform full-wave rectification of the generated voltage.

Next, the three-phase full-wave rectifier 3 will be described. This three-phase full-wave rectifier 3 is composed of three sets of high-side switches 31 to 33 and low-side switches 34 to 36 each composed of a power NMOS transistor using Si or SiC having a higher withstand voltage than Si and individually connected in series. Are connected in parallel, and a pair of DC output terminals are individually connected to a high-order terminal and a low-order terminal of the battery 7, respectively, and each switch 3 of each phase inverter circuit 37-39 is connected.
The connection points 1 to 36, that is, the AC input terminals 41 to 43 are configured to be individually connected to the respective phase output terminals of the armature windings 11 to 13 of the AC generator 1.

The main electrode (shown as a drain electrode D) of the low-side switches 34 to 36 on the battery lower terminal E side is connected to a P-type substrate region immediately below the gate electrode (P-type substrate is also used).
(May be a mold well region) to apply a potential to this substrate region, and further connect a P-type substrate region immediately below the gate electrodes of the high side switches 31 to 33 to the battery low terminal E to apply a potential.

Therefore, in this embodiment, the first parasitic diode D1, which is a junction between the main electrode (shown as the source electrode S) of the high-side switches 31 to 33 on the battery 7 side and the P-type substrate region, Side switch 31
33, a first parasitic diode D2 composed of a junction between a main electrode (indicated as a drain electrode D) on the side of the stator coils 11 to 13 and the P-type substrate region, and stator coils 11 to 31 of the low-side switches 34 to 36. A third parasitic diode D3 consisting of a junction between the main electrode on the 13th side (indicated as a source electrode S) and the P-type substrate region is formed in a parasitic manner.

Here, the first parasitic diode D1 has a withstand voltage exceeding the maximum rated voltage value of the battery. For example, when the potential of the connection point 41 is 0 V (ground potential) or the forward voltage drop of the PN junction by more than 0 V (ground potential). No breakdown occurs even at low potentials. Further, the second parasitic diode D2 and the third parasitic diode D3 have a withstand voltage exceeding a predetermined G pulse voltage value exceeding the maximum generated voltage. The predetermined G pulse voltage value is defined as a connection point 4 when the output current of the rectifier 3 becomes 0 at a predetermined time from a predetermined current value when a predetermined exciting current (field current) is supplied and during a predetermined rotation.
The surge voltage value is induced to 1 to 43, for example, 300V here, and the maximum voltage of the battery 7 is 14V.

Furthermore, when the G pulse voltage is applied to the connection point 41, the withstand voltage of the gate insulating films of the transistors 31 to 36 between the N-type regions on the connection points 41 to 43 side and the gate electrode is also ensured. Transistors 31 between the N-type regions on the battery side of side switches 31 to 33 and the gate electrode
The withstand voltage of the 36 gate insulating films is also ensured. As is well known, the withstand voltage of each part is ensured by transistors 31 to 36.
It is realized by selecting the impurity concentration of each part and the gate oxide film thickness.

Particularly, in this embodiment, in order to improve the breakdown voltage of the second parasitic diode D2 and the third parasitic diode D3,
The transistors 31 to 36 have a DMOS structure (see FIG. 5) or a vertical power MOS structure (see FIG. 6), and their N
^- type type withstand voltage layer these second parasitic diode D2 and the third
Arranged in the parasitic diode D3, the withstand voltage of the second parasitic diode D2 and the third parasitic diode D3 against the G pulse voltage and the withstand voltage between the N-type region on the connection points 41 to 43 side and the gate electrode are easily ensured. . In this case, since the high-side switch and the low-side switch forming the same-phase inverter circuit have the same potential on the substrate, a one-chip configuration can be adopted, and a rectifier can be formed by a total of three chips.

Controller (control section in the present invention) 6
Has a built-in microcomputer, controls the excitation current so that the B voltage becomes a predetermined level, and switches each switch based on the phase and magnitude to the generated voltage at each phase output terminal for three-phase full-wave rectification. Intermittent control of 31 to 36 is performed. Hereinafter, the control operation of the controller 6 that executes the intermittent control method of the switches 31 to 36 in this embodiment will be described more specifically.

First, the potentials (phase voltages) V1 to V3 of the connection points (phase output terminals) 41 to 43 are detected, and the phase voltages V1 to V3 are detected.
V3 is compared with the battery voltage and the ground potential, and the high-side switch that applies a phase voltage higher than the battery voltage (voltage B) and the low-side switch of another phase inverter circuit are turned on. In this way, three-phase full-wave rectification can be performed.

Alternatively, each phase voltage V1 to V3 is compared with the battery voltage and the ground potential, and each phase voltage V1 to V3 is higher than the battery voltage and the ground battery voltage (voltage B), and the highest phase voltage is applied. The low side switch to which a phase voltage lower than the ground potential E is applied is turned on. In this way, different high-side switches do not turn on at the same time and short-circuit current flows, and different low-side switches do not turn on at the same time and short-circuit current does not flow.

In this embodiment, the phase voltages V1 to V3
Are cut off when any one of them exceeds a predetermined G pulse voltage value, the rectifier is turned off because the current to the load 7 suddenly decreases (for example, the fuse 10 is turned off) or the battery connection terminal B is disconnected. The surge voltage generated when the output current of the switch 3 suddenly decreases is equal to the high-side switches 31-31.
Since the channel disappears at 33 and is completely blocked by the second parasitic diode D2, no G pulse voltage is applied to the load 9. The surge voltage cutoff mode can be maintained for a predetermined time, or can be maintained while any one of the phase voltages exceeds a predetermined voltage value.

Further, all the low-side switches 34 to 36 can be turned on during the above-mentioned surge voltage cutoff mode in which all the high-side switches 31 to 33 are turned off. In this case, the armature windings 11 to 13 of each phase are short-circuited through the on-resistance of each of the low-side switches 34 to 36, and the surge power can be consumed without increasing the B voltage of the battery. As a result, an increase in the G pulse voltage can be prevented.

The control operation of the controller 6 described above may be performed based on the determination result of the input voltages V1 to V3 and the B voltage or a predetermined threshold value by a built-in microcomputer and based on the determination result. Can be implemented. FIG. 2 shows an example of the flowchart.
That is, in step 100, the input phase voltages V1 to V3 and the battery voltage VB are input, and then the input phase voltages V1 to V3 are input.
It is determined whether any one of the three is greater than a predetermined G pulse voltage value Vg (102).
In step 3, three-phase full-wave rectification is performed by sequential opening / closing control of the normal switches 34 to 36.
At 6, the high-side switches 31 to 33 are turned off, and the low-side switches 34 to 36 are turned on to reduce the surge voltage and prevent the surge voltage from being applied to the load 9 . (Modification) In the above embodiment, the occurrence of the G pulse voltage is determined by comparing the phase voltages V1 to V3 with the predetermined G pulse voltage value. However, the battery voltage VB is compared with the predetermined G pulse voltage value. In this case, the phase voltages V1 to V3 are compared with a predetermined G pulse voltage value via the battery voltage VB. Of course it is included. (Modification) Next, an example of a circuit in which the operations of steps 102 and 106 described above are configured by hardware will be described with reference to FIG. However, FIG. 3 shows only the phase voltage (X phase) of the armature winding 11.

The phase voltage V1 is divided by the voltage dividing circuit 58 and inputted to the + input terminal of the comparator 51 and the-input terminal of the comparator 52. The battery voltage VB is divided by the voltage dividing circuit 58 and The input is input to the input terminal, and the + input terminal of the comparator 52 is grounded. As a result, the comparator 51 outputs a high level to the AND circuit 54 when the phase voltage V1 is higher than the battery voltage VB, and the comparator 52 turns on the low-side switch 34 when the phase voltage V1 is lower than 0V.

On the other hand, the battery voltage VB is inputted to the + input terminal of the comparator 53 divided by the voltage dividing circuit 58, and the minus input terminal thereof has a predetermined threshold voltage (corresponding to the predetermined G pulse voltage value). ) Vth is input. As a result, when the divided voltage of the battery voltage VB is larger than the predetermined G pulse voltage value Vth (when a surge voltage occurs), the comparator 53 outputs a high level potential to the common emitter transistor 56, and the transistor 56 is turned on. To discharge the capacitor C.

The collector voltage of the transistor 56 is input to the AND circuit 54. Therefore, the AND circuit 54 raises the low level potential during the generation of the surge voltage.
5 is output. The booster circuit 55 is composed of, for example, a switching capacitor circuit and boosts the battery voltage to a level at which the high side switch 31 can be turned on. When a low level potential is input from the AND circuit 54, the low level is output to the high side switch 31. As a result, the high-side switch 31 is turned off.

The disappearance of the surge voltage causes the comparator 5
3 outputs a low level, the transistor 56 is turned off, and charging of the capacitor C is started. After a predetermined time determined by the CR time constant, the AND circuit 54 outputs
Can be opened and closed. With this configuration, even if the instantaneous value of each phase voltage, which is an AC voltage, becomes a phase period in which the instantaneous value becomes equal to or less than the predetermined voltage value Vth, the high-side switch 31 is kept off for a predetermined time (at least one cycle). When the phase voltage applied to the other high-side switch 32 or 33 exceeds the predetermined voltage value Vth, the high-side switch 31
Can be shut off. (Modification) Next, another example of a circuit in which the operations of steps 102 and 106 are configured by hardware will be described with reference to FIG.

In this embodiment, the comparator 53 shown in FIG.
A transistor 56 and an integrating circuit 59 are compared with a peak value holding circuit including an operational amplifier 53, a diode Di and a capacitor C, and an output voltage of the peak value holding circuit is compared with a threshold voltage (a predetermined G pulse voltage value). This is replaced with a comparator 60 that performs the operation. This operation will be described. The divided voltage of the phase voltage V1 is input to the negative input terminal of the comparator 60 while being held by the peak value hold circuit. As a result, the instantaneous maximum value (peak value) of the phase voltage V1 becomes equal to a predetermined threshold voltage (corresponding to the predetermined G pulse voltage value) Vth.
When the value exceeds 1 (when a surge voltage occurs), the comparator 60 turns off the AND circuit 54, thereby turning off the high-side switch 51.

Here, in the reset circuit composed of the comparator 61 and the transistor 62, the battery voltage VB is divided by the voltage dividing circuit 58 and is inputted to the minus input terminal of the comparator 61, and the + input terminal thereof is provided with a predetermined voltage. A threshold voltage (reset occurrence) Vth2 is input. As a result, when the divided voltage of the battery voltage VB becomes smaller than the predetermined reset voltage Vth2, the comparator 61 outputs a high level to the common-emitter transistor 62, and the transistor 62 is turned on to discharge the capacitor C, and to the peak hold circuit. Give a reset operation.

As a result, an effect similar to that of the circuit of FIG. 3 can be obtained. (Modification) FIG. 5 shows an example of a DMOS integrated circuit in which the high-side switch 31 and the low-side switch 34 constituting the X-phase inverter circuit 37 are integrated on the same chip.
FIG. 5 shows an example of a vertical MOS integrated circuit.

In FIG. 5, an N-type breakdown voltage layer 105 is formed on an N ⁺ -type substrate 106 by epitaxial growth.
A P-type well region 103 is formed on the surface of the mold breakdown voltage layer 105, and an N ⁺ -type region 104 is formed on the surface of the P-type well region 103. Then, the gate insulating film 109
Is formed thereon, and a gate electrode 110 made of doped polysilicon is formed thereon.

Therefore, in this embodiment, the first parasitic diode D1 of the high side switch 31 disposed on the left side in FIG. 5 is connected to the PN junction between the N ⁺ type region 104 and the P type well region 103. And the second parasitic diode D2 is N
⁺ Consists PN junction between the substrate 106 and the P-type well region 103, in FIG. 5, a third parasitic diode of the low-side switch 34 disposed on the right - de D3 is N ⁺ substrate 106 and P
It consists of a PN junction with the mold well region 103.

That is, in this embodiment, the high-side switch 31 and the low-side switch 34 can be integrated on the same chip, and the second and third parasitic diodes D2 and D3 need a large surge withstand voltage (G pulse withstand voltage). Has an excellent feature that a large surge withstand voltage can be ensured since it has a low-concentration N-type epitaxial breakdown voltage layer 105.

FIG. 6 shows a vertical MOS structure in place of the DMOS structure of FIG. 5, and can provide the same functions and effects as those of FIG. Further, according to the structures of FIGS. 5 and 6, wiring is also simplified .

[0060]

[0061]

[0062]

[0063]

[0064]

[0065]

[0066]

[0067]

[0068]

[0069]

[0070]

[0071]

[0072]

[0073]

[0074]

[0075]

[0076]

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a charging device of the present invention.

FIG. 2 is a flowchart showing the operation of the controller 6 of FIG.

FIG. 3 is a circuit diagram showing an example in which the controller 6 of FIG. 1 is configured by hardware.

FIG. 4 is a circuit diagram showing an example in which the controller 6 of FIG. 1 is configured by hardware.

FIG. 5 is a sectional view showing an example of the phase inverter circuit 37 of FIG.

6A is a cross-sectional view illustrating an example of the phase inverter circuit 37 of FIG. 1, and FIG. 6B is a plan view thereof.

FIG. 7 is a circuit diagram showing another embodiment of the conventional MOS transistor type three-phase full-wave rectifier and the charging device of the present invention .

[Explanation of symbols]

1 is a three-phase AC motor, 3 is a rectifier, 6 is a controller (controller), 7 is a battery, 9 is a load, 11 to 13 are armature windings, 31 to 33 are high side switches composed of MOS transistors, 34 to 36 is a low side switch composed of a MOS transistor; 37 to 39 are phase inverter circuits; 41 to 43 are connection points of the phase inverter circuits 37 to 39 (AC input terminals of the rectifier 3); 103 is a P-type region (substrate region); Is a first parasitic diode, D2 is a second parasitic diode, D3 is a third parasitic diode, 106 is an N-type armature winding side region of the high-side switch 31 and the low-side switch 34, and 105 is an N- Mold pressure-resistant layer.

Claims (14)

(57) [Claims] 1. A required number of phase inverter circuits in which a high side switch and a low side switch each composed of an N-channel MOS transistor are connected in series are connected in parallel, and a pair of DC output terminals are connected to both ends of a battery and a load. A rectifier in which a connection point of the two switches is individually connected to each phase output terminal of the armature winding of the AC generator, and a control unit that controls a gate potential of each of the switches and turns the switches on and off. In the charging device, a substrate region formed of a P-type region immediately below a gate electrode of the high-side switch is connected to a lower end of the battery. 2. The control unit detects a phase voltage at each phase output terminal of the AC generator, and shuts off at least the high-side switch group when any of the phase voltages exceeds a predetermined voltage value. 2. The charging device according to claim 1, further comprising a surge voltage cutoff mode. 3. The charging device according to claim 2, wherein the control unit keeps the surge voltage cutoff mode for a predetermined time. 4. The charging device according to claim 2, wherein the control unit maintains the surge voltage cutoff mode while any of the phase voltages exceeds a predetermined voltage value. 5. The high-side switch, wherein the phase voltage applied to an N-type armature winding side region forming a main electrode on a connection point side of each of the high-side switches is higher than a voltage of the battery. The charging device according to claim 2, wherein the side switch is turned on. 6. The low-side switch, wherein the phase voltage applied to an N-type armature winding-side region forming a main electrode on a connection point side among the low-side switches is lower than a voltage of the battery. 3. The charging device according to claim 2, wherein the charging device is turned on. 7. A first parasitic diode between an N-type battery-side region forming a main electrode on the battery side of the high-side switch and the substrate region has a withstand voltage exceeding a maximum rated voltage value of the battery. Item 3. The charging device according to Item 2. 8. A second parasitic diode between an N-type armature winding side region forming a main electrode on a connection point side of the high-side switch and the substrate region has a predetermined G value exceeding a maximum generated voltage.
3. The charging device according to claim 2, which has a withstand voltage exceeding a pulse voltage value. 9. A third parasitic diode between an N-type armature winding-side region forming a main electrode on the connection point side of the low-side switch and the substrate region has a predetermined G exceeding a maximum generated voltage.
3. The charging device according to claim 2, which has a withstand voltage exceeding a pulse voltage value. 10. The MO constituting the high-side switch
The charging device according to claim 7, wherein one of the two N-type regions forming the main electrode of the S transistor has an N- type breakdown voltage layer, and the N- type breakdown voltage layer is formed on the first parasitic diode side. 11. The MO constituting the high-side switch
9. The charging device according to claim 8, wherein one of the two N-type regions forming the main electrode of the S transistor has an N- type breakdown voltage layer, and the N- type breakdown voltage layer is formed on the second parasitic diode side. 12. The MO constituting the low-side switch
10. The charging device according to claim 9, wherein one of the two N-type regions forming the main electrode of the S transistor has an N- type breakdown voltage layer, and the N- type breakdown voltage layer is formed on the third diode side. 13. The high-side switch and the low-side switch forming the phase inverter circuit of the same phase are integrated on the same chip having an N-type region as a substrate, and the N-type substrate region is connected to a phase output terminal of the AC generator. The charging device according to claim 2, which is connected. 14. The charging device according to claim 2, wherein the control unit turns off all the high-side switches and turns on the low-side switches when the surge voltage cutoff mode is performed .