JP3328247B2 - In-circuit emulator and emulation method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-circuit emulator and an emulation method therefor, and more particularly to an in-circuit emulator and an emulation chip incorporating only an emulation function and a peripheral emulator incorporating each peripheral function. The present invention relates to an in-circuit emulator for emulating the operation of a microcomputer chip and an emulation method therefor.

[0002]

2. Description of the Related Art An in-circuit emulator is a combination of a central processing unit (CPU) for controlling the execution of a user program, an evolution chip containing only functions necessary for emulation, and a peripheral emulator containing peripheral functions. Used to emulate the operation of a microcomputer.

[0003] Such, in-circuit emulator, rather than to develop a dedicated e variation chip in each product, and a CPU and a common, circumference of the built-in peripheral functions its
By changing only the side emulator, product types can be expanded, contributing to reductions in product development costs and man-hours.

Recently, an interface such as a programmable integrated circuit (IC) FPGA or a dedicated gate array has been used.
However, the use of in-circuit emulators that use different products as peripheral emulators is increasing. In this case, there is a demand that the emulation bus selected according to the interface of the peripheral emulator be selected by setting the emulation register built in the emulation chip to enable emulation of the target peripheral emulator.

[0005] As an example of an evolution chip developed to meet this demand, μP of NEC Corporation has been used.
D780009.

The variation chip μPD780
Referring to FIG. 6, which shows a block diagram of a conventional in-circuit emulator using 009, the conventional in-circuit emulator has two peripheral emulators 2 having different emulation bus interfaces for convenience of explanation.
Assuming that the peripheral emulators 2 and 23 are provided, each of the peripheral emulators 22 and 23 has an independent configuration as described later .

More specifically, as shown in FIG. 6A, an in-circuit emulator including the peripheral emulator 22 has a CPU (not shown) for controlling the execution of a user program.
), An emulation chip 100 having an emulation register 11 and a peripheral emulator 22.
And an emulation bus 3 which is an interface conforming to the peripheral emulator 22 and connects the variation chip 100 and the peripheral emulator 22.

An in-circuit emulator including the peripheral emulator 23 is, as shown in FIG.
An emulation chip 100 having the emulation register 11, a peripheral emulator 23, and an emulation bus 4 that is an interface based on the peripheral emulator 23 and connects the emulation chip 100 and the peripheral emulator 23.

Next, the operation of the conventional in-circuit emulator will be described with reference to FIG. 6. The peripheral emulator 22 and the peripheral emulator 23 are connected to the corresponding emulation buses 3 and 4 , respectively. The emulation register 11 of the emulation chip 100 selects one of the emulation buses 3 and 4 according to the setting corresponding to the interface of the target peripheral emulator, and executes a predetermined emulation.

For convenience of explanation, the variation chip 1
Assume that the default value of the emulation register (hereinafter referred to as EMR) 11 is 1 . Evarision chip 1
00, when the peripheral emulator 22 there, during the reset period, and outputs the value 00H to the peripheral emulator 23 and a disabled emulation bus 4, also in the case of there peripheral emulator 23 during the reset period, peripheral emulator 23 is output to the emulation bus 4 for causing the H.23 to perform the emulation operation. Further, when the EMR 11 has the default value of 1, the emulation bus 3 is selected.

Further, the peripheral emulator 23 outputs an interrupt request signal I in response to an interrupt in the emulation mode.
NTRQ is output and supplied to the variation chip 100. The variation chip 100 replies to the peripheral emulator 23 with an interrupt acceptance signal INTACK in response to the supply of the interrupt request signal INTRQ. In response to the supply of the interrupt acceptance signal INTACK, the peripheral emulator 23 outputs a predetermined vector code to the emulation bus 4 and supplies it to the variation chip 100 . See below
As shown, the variation chip 100 accepts an interrupt
Emulation corresponding to the response of the signal INTACK
It is assumed that the bus 4 is latched to recognize the vector code .

EMR1 of the variation chip 100
By setting 1 to the default value of 1, as described above,
The emulation bus 3 is selected, and the peripheral functions incorporated in the peripheral emulator 22 can be emulated. At this time, during the reset period, the variation chip 100 outputs a value 00H to the peripheral emulator 23 to disable the peripheral emulator 23 via the emulation bus 4, and the peripheral functions included in the peripheral emulator 23 are emulated. Avoid being rated.

Next, when the value of the EMR 11 is set to 0 , the emulation bus 4 is selected and the emulation chip 100 outputs 01H to emulate the peripheral functions built in the peripheral emulator 23, and at the same time, the emulation bus 3 Is not selected, and the peripheral function built in the peripheral emulator 22 cannot be emulated.

Therefore, it is impossible to emulate the peripheral emulator 22 and the peripheral emulator 23 simultaneously with the same in-circuit emulator.

Furthermore, when the selected emulation bus 3 and to shift the peripheral emulator 23 to forcibly emulation mode, peripheral emulator 23 an interrupt request signal INTRQ in error variation chip 100
You supply. The variation chip 100 returns an interrupt acceptance signal INTACK to the peripheral emulator 23 in response to the supply of the interrupt request signal INTRQ. The peripheral emulator 23 outputs a predetermined vector code to the emulation bus 4 in response to the supply of the interrupt acceptance signal INTACK. However, as described above, since in the selected state of the emulation bus 3, d variation chip 100 will latch the error <br/> emulation bus 3 in response to the reply of the interrupt acceptance signal INTACK, the emulation bus 4 Since the latch is not performed, the vector code cannot be recognized.

[0016]

In the above-mentioned conventional in-circuit emulator and its emulation method, an emulation bus is selected according to the interface of a peripheral emulator by setting an emulation register built in the emulation chip. Emulation of a peripheral emulator that does not
Emulation mode)
To the interrupt request that occurs when the
In response to the interrupt acceptance signal of the creation chip,
Emulation bus supported by the setting peripheral emulator
Output a predetermined vector code to
The chip sets the above according to the response of the interrupt acceptance signal.
Latches the currently selected emulation bus
Emulation for non-setting peripheral emulators
The bus cannot be latched, so the above vector code cannot be recognized.
Because it does not come, there is a disadvantage that the emulation bus interface is not possible to emulate a plurality of different peripheral emulator at the same time.

An object of the present invention is to provide an in-circuit emulator capable of emulating a plurality of peripheral emulators having different emulation bus interfaces simultaneously, and an emulation method therefor.

[0018]

An in-circuit emulator according to the present invention combines the operation of an actual microcomputer chip with a combination of an emulation chip having only a central processing unit and an emulation function and a peripheral emulator having a peripheral function. in-circuit emulator for emulation, the Ebarie
Option chip sets the emulation function
An emulation register that holds the set value for
Based on the set value of the emulation register,
Select one of the first and second emulation buses
A bus control unit that performs bus control to select
And a said central processing unit for controlling the execution of the ram, the
The emulator section includes a first peripheral emulator having a first peripheral function, a second peripheral emulator having a second peripheral function, and an input section of the first peripheral emulator .
A first interface having a first interface conforming to the
An emulation bus, a second emulation bus having a second interface conforming to the interface of the second peripheral emulator, and the first and second emulation buses.
A bus control circuit for adjusting the interface compatibility between the first and second emulation buses between the emulation buses, and a reset signal and a clock signal from the emulation chip, and a bus control circuit for the first and second peripheral emulators . Either one of the selection peripheral emulation
Supplied with the interrupt acknowledge signal is supplied in response to acceptance of the interrupt request signal from the non-selected peripheral emulator towards non over data, the selection peripheral emulator
Preset reset period when emulating
The non-selected peripheral emulator during the hold period corresponding to
The first and the second to enable emulation of
The first and second peripheral emulators can be simultaneously emulated on the same emulation configuration by executing the interface compatibility adjustment between the emulation buses.

Further, the bus control circuit detects a falling edge of a reset signal and outputs an edge detection signal, and a clear control circuit which outputs a clear control signal in response to the supply of the edge detection signal. And a clock counter that is cleared in response to the supply of the clear control signal and simultaneously starts counting clocks and outputs a count value of the count result, and sets a hold period corresponding to a reset period and outputs a hold period set value. A hold period setting register, a match circuit that compares the count value with the hold period set value, and outputs a match signal when the count value matches the hold period set value; An output control circuit that outputs a switch control signal; and An analog switch for connecting the least significant bit bus line of the second emulation bus to the above-mentioned variation chip side and the second peripheral emulator side; and receiving an inverted interrupt by inverting an interrupt reception signal from the above-mentioned emulation chip. A first inverter that outputs a signal, and a latch circuit that is enabled when the inverted interrupt acceptance signal is input, latches data on the second emulation bus in synchronization with the clock, and outputs the data to the first emulation bus. May be.

[0020]

The analog switch of the bus control circuit includes a second inverter having an input terminal connected to a control terminal;
An N-channel MOS transistor having a source connected to an input terminal, a drain connected to an output terminal, and a gate connected to a control terminal;
P-channel MOS having a common connection to the drain and source of the transistor and a gate connected to the output terminal of the inverter
And a transistor.

The latch circuit of the bus control circuit receives a clock supplied to a clock terminal, connects an output terminal of the inverter to an enable terminal, connects a second emulation bus to a data terminal, and connects a first emulation bus to an output terminal. A D flip-flop connected to a bus may be provided.

The emulation method of the in-circuit emulator according to the present invention is an emulation method for emulating the operation of an actual microcomputer chip by combining an emulation chip having only a central processing unit and an emulation function with a peripheral emulator having a peripheral function. In the emulation method for a circuit emulator, the variation chip may
Holds setting values for setting the simulation function,
Based on the set value, first and second emulations described later
Bus control to select one of the
A first emulation bus having a first interface conforming to a first peripheral emulator; and a second emulation bus having a second interface conforming to a second peripheral emulator.
The bus control circuit for interfacing compatible adjustment of the first and second emulation bus between the emulation bus provided in the bus control circuit, the first及
And one of the second peripheral emulators
Predetermined when emulating as a emulator
The first and the second during the hold period corresponding to the reset period
And the selected peripheral emulator of the second peripheral emulator
Emulation of non-selected peripheral emulator that is not
By executing the above interface compatible adjust the predetermined timing so as to enable, characterized in that it allows emulation time emulation bus said first and second peripheral emulator different interfaces on the same emulator configuration Things.

[0024]

The bus control circuit may supply an interrupt acceptance signal output by the evolution chip in response to acceptance of an interrupt request signal from the second peripheral emulator during a hold period corresponding to the reset signal. The interface may be adjusted by connecting the first and second emulation buses to each other.

[0026]

Next, embodiments of the present invention will be described with reference to the drawings.

The in-circuit emulator according to the present embodiment combines the operation of an actual microcomputer chip with a combination of an evolution chip having only a central processing unit (CPU) and an emulation function and a peripheral emulator having each peripheral function. in-circuit emulator for emulation, the Ebarie
Is used to set the emulation function.
Emulation register that holds the set value for
Based on the value set in the emulation register,
Select one of the first and second emulation buses
A bus control unit that controls the bus
And a central processing unit for controlling execution of the system.
Emulator unit, the upper between the plurality of emulation bus
Select one of the first and second peripheral emulators.
When emulating as a peripheral emulator
Above the hold period corresponding to the preset reset period
The selected peripheral emulator of the first and second peripheral emulators
Emulator of non-selected peripheral emulator that is not
A bus control circuit that adjusts the interface compatibility of the plurality of emulation buses so as to enable the first emulation bus. The first bus control circuit has a first interface that complies with a first peripheral emulator among the plurality of emulation buses.
Interface emulation bus and a second emulation bus having a second interface conforming to the second peripheral emulator are adjusted at a predetermined timing, so that a plurality of peripheral emulators having different emulation bus interfaces can be connected to the same emulator bus. Enable emulation on the emulation configuration at the same time.

Next, referring to FIG. 1 which shows the embodiment of the present invention and also shows constituent elements common to FIG. 6 with common reference characters / numerals and similarly shown by blocks, FIG. An in-circuit emulator of the form includes an emulation chip 1 having only a central processing unit (CPU) for controlling execution of a user program and a function necessary for emulation, and an emulator section having a plurality of peripheral emulators having built-in peripheral functions. 2 and peripheral emulator 2
An emulation bus 3 which is a data bus having an interface conforming to the H.2 and emulating peripheral functions built in the peripheral emulator 22;
An emulation bus 4 is provided as a data bus having an interface conforming to the peripheral emulator 23 and enabling emulation of peripheral functions built in the peripheral emulator 23.

The emulation chip 1 has an emulation register (EMR) 11 for holding a set value for setting an emulation function, and a bus control for selecting one of the emulation buses 3 and 4 based on the set value of the EMR 11. Bus control unit 12 that performs
The bus controller 12 includes an address bus 14 for inputting an address A to the bus controller 12 and a data bus 15 for inputting data D to the bus controller 12.

The emulator unit 2 includes, in addition to the peripheral emulator 22 and the peripheral emulator 23 common to the related art,
The emulation bus 3 and the emulation bus 4 receive a reset signal R, a clock CK, and an interrupt acceptance signal IK from the emulation chip 1.
Bus control circuit 2 for performing predetermined interface compatibility adjustment of
1 is provided.

For convenience of description, here, the peripheral emulator 22 is a programmable IC and the peripheral emulator 2
3 is an emulator chip, which requires emulation mode setting to emulate built-in peripheral functions, and emulates built-in peripheral functions during a hold period until a reset signal is supplied.

The default value of the emulation register (hereinafter referred to as EMR) 11 of the variation chip 1 is 1. Further, the emulation buses 3 and 4 are each an 8-bit bus. When there is the peripheral emulator 22, the variation chip 1 outputs an enable / disable value 00H for disabling the peripheral emulator 23 to the emulation bus 4 during the reset period regardless of the presence or absence of the peripheral emulator 23. If there is only the peripheral emulator 23,
Enable / disable value 01 for causing the peripheral emulator 23 to perform the emulation operation during the reset period
H is output to the emulation bus 4. Furthermore, EM
When R11 has a default value of 1, emulation bus 3 is selected, and when R11 is 0, emulation bus 4 is selected.

Further, the peripheral emulators 22 and 23
Outputs an interrupt request signal IQ when an interrupt occurs in the emulation mode,
In response to the supply of the interrupt request signal IQ, the variation chip 1 returns an interrupt acceptance signal IK to the peripheral emulators 22 and 23. Peripheral emulator 2
2 and 23 output a predetermined vector code to each of the emulation buses 3 and 4 in response to the supply of the interrupt accepting signal IK and supply the same to the variation chip 1.

Next, the operation of this embodiment will be described with reference to FIG.
By setting the default value 1 to R11, the emulation bus 3 is selected, and the peripheral functions built in the peripheral emulator 22 can be emulated. The variation chip 1 has an enable / disable value 00 at the falling edge of the reset signal R activated at the L level.
H is output and supplied to the peripheral emulator 23 via the emulation bus 4, and the peripheral emulator 23 is disabled.

In contrast to the above operation, the bus control circuit 21
As described later, an enable / disable value 01H for enabling emulation via the emulation bus 4 is output to the peripheral emulator 23 during a hold period corresponding to the reset period.

Referring to FIG. 2, which is a block diagram showing the configuration of the bus control circuit 21 of the present embodiment, the bus control circuit 21 shown in FIG. 2 detects a falling edge of the reset signal R and outputs an edge detection signal RE. Edge detection circuit 21
1, a clear control circuit 212 that outputs a clear control signal RC in response to the supply of the edge detection signal RE, and a clear control circuit 212 that is cleared in response to the supply of the clear control signal RC and simultaneously outputs the clear signal and the peripheral emulators 22 and 23. A clock counter 213 that starts counting the clock CK for the interface and outputs a count value N as a counting result.
And a reset period, that is, a hold period setting register 21 for setting a hold period and outputting a hold period HT.
4, a match circuit 215 that outputs a match signal CI when the count value N is compared with the hold period HT, and a switch control signal for controlling the analog switch 217 receiving the edge detection signal RE and the match signal CI. An output control circuit 216 for outputting AC, and a switch control signal AC
Bit 0 of the emulation bus 4 in response to the
In other words, the bus line 41 for the least significant bit (B0) of the eight bits has the variation chip 1 side (B0
1 ) and an analog switch 217 connecting the peripheral emulator 23 side (B0O), and an evolution chip 1
An inverter 218 that inverts the interrupt accept signal IK from the inverter and outputs an inverted interrupt accept signal IKB;
A latch circuit 219 is enabled when an inverted interrupt acceptance signal IKB is input, latches data on the emulation bus 4 in synchronization with the clock CK, and outputs the data to the emulation bus 3. The number of the latch circuits 219 is equal to the number of bits of the emulation buses 3 and 4, and in this example, eight bits are required. Therefore, only one bit is shown for convenience of explanation.

The latch circuit 219 receives, for example, a clock CK from a clock terminal CK and enables the enable terminal OE.
To the output terminal of the inverter 218, the data terminal D to the emulation bus 4, and the output terminal Q to the emulation bus 3.

Referring to FIG. 3A which shows a block diagram of the configuration of the analog switch 217, the analog switch 217 has a control terminal TC, an input terminal TI to which the signal B0I is connected, and an output terminal TO to which the signal B0O is connected. The switch element S1 is turned on in response to the H level of the switch control signal AC, and the input terminal TI
And the output terminal TO.

FIG. 3 is a circuit diagram showing an example of a switch element.
Referring to (B), the switch element S1 includes an inverter IV1 having an input terminal connected to the control terminal TC, and an N-channel MOS having a source connected to the input terminal TI, a drain connected to the output terminal TO, and a gate connected to the control terminal TC. It includes a transistor N1 and a P-channel MOS transistor P1 having a drain and a source commonly connected to the drain and the source of the transistor N1, and a gate connected to the output terminal of the inverter IV1.

The operation of the bus control circuit 21 will be described with reference to FIGS. 2 and 3 and FIGS. 4 and 5, which are time charts showing the bus switching operation and the emulation interrupt accepting operation, respectively. When receiving the supply of R, the falling edge of the reset signal R is detected, and an edge detection signal RE is output.
It is supplied to the clear control circuit 212 and the output control circuit 216. The clear control circuit 212 outputs a clear control signal RC in response to the supply of the edge detection signal RE, and supplies the same to the clock counter 213. The clock counter 213
In response to the supply of the clear control signal RC, the count value N at that time is cleared, and at the same time, counting of the clock CK is started and a new count value N is output, and the coincidence circuit 215 is output.
To supply. On the other hand, the hold period setting register 214
Supplies a hold period HT corresponding to the length of the preset reset period, that is, the hold period, to the matching circuit 215.

The hold value H is determined by the clock CK
, Which is assumed to be a fixed number, for example, 100 for convenience of explanation. Then, assuming that the frequency of the clock CK is 100 MHz, that is, the period is 10 ns, the hold period is 1000 ns. The hold period is a time necessary for emulating the peripheral emulator 23, and this time depends on the characteristics of the peripheral emulator 23.

The coincidence circuit 215 compares the count value N of the clock CK with the hold period HT, and outputs a coincidence signal CI when both coincide with each other, and supplies it to the output control circuit 216.

The output control circuit 216 normally sets the switch control signal AC to the H level to set the analog switch 217
To supply. Further, when the edge detection signal RE responding to the detection of the falling edge of the reset signal R is inputted, the switch control signal AC is transited to the L level. Further, the switch control signal AC is returned to the H level in response to the supply of the coincidence signal CI.

Accordingly, the analog switch 217 is in a conductive state during a normal period, and the input terminal TI and the output terminal TO are connected. That is, the bus line 41 of the least significant bit 0 of the emulation bus 4 connecting the emulation chip 1 and the peripheral emulator 23 is in a connected state.

When the switch control signal AC changes to the L level in response to the input of the edge detection signal RE, the analog switch 217 is turned off in response to the L level of the switch control signal AC, and the analog switch 217 is connected to the input terminal TI. The connection of the output terminal TO is cut off. As a result, the bus line 41 of the emulation bus 4 is turned off. This non-conduction state continues as described above until match signal CI is supplied. Therefore, this continuation period corresponds to the hold period HT.

According to the precondition described above, when the peripheral emulator 22 is present, the variation chip 1 sets the enable / disable value 00H for disabling the peripheral emulator 23 during the reset period regardless of the presence or absence of the peripheral emulator 23. It outputs to the emulation bus 4, and if there is only the peripheral emulator 23, outputs an enable / disable value 01H for emulating the peripheral emulator 23 to the emulation bus 4 during the reset period.

In this case, the variation chip 1
Output the enable / disable value 00H to the emulation bus 4.

Therefore, when the reset signal R is supplied,
During the hold period HT, the bus line 41 for transmitting the bit 0 (B0) of the emulation bus 4 is turned off, and during this period, the output side of the bus line 41 connected to the output terminal TO of the analog switch 217, that is, the peripheral emulator 23 Side, that is, 1 is supplied as B0. Other bits 1 to 7 of emulation bus 4
(B1 to B7) are irrelevant to the conducting / non-conducting operation of the analog switch 217, and are at the L level, that is, 0 because they remain conducting. As a result, bus line 4
1, the enable / disable value 01H is supplied to the peripheral emulator 23 side.
The emulation is enabled.

The H level is supplied, for example, by the output control unit 21 supplying the H level potential to the output side of the bus line 41 via the control line W1 during the L level of the switch control signal AC as shown in FIG. Then, the control line W1 is configured to be in a high impedance (Hiz) state during the H level of the switch control signal AC.

[0050] Thus, during the hold period HT, the
In response to the supply of the enable / disable value 01H, the peripheral emulator 23 enters an enabled state, and executes a predetermined emulation.

After the hold period HT has elapsed, the match signal CI
Is supplied, the output control circuit 216 returns the switch control signal AC to the H level,
7 becomes conductive again, and the enable / disable value 00H is supplied to the peripheral emulator 23, so that the peripheral emulator 23 is disabled.

Next, referring also to FIG. 5, the peripheral emulator 23 outputs an interrupt request signal IQ in the emulation mode and supplies the interrupt request signal IQ to the emulation chip 1. The emulation chip 1 outputs the interrupt request signal IQ.
In response to the supply of the interrupt request signal, an interrupt acceptance signal IK is returned to the peripheral emulators 22 and 23. Peripheral emulators 22, 23
Responds to the supply of the interrupt acceptance signal IK, outputs a predetermined vector code to the emulation buses 3 and 4 and supplies it to the variation chip 1.

At this time, the variation chip 1
This is an operation state in which the emulation bus 3 for emulating the peripheral emulator 22 is enabled by setting the emulation register 11. Therefore, in this state, as described above, the H level is transmitted via the bus line 41, and the substantial enable / disable value 01H is transmitted.
Is supplied, the emulation chip 1 cannot recognize the vector code output to the emulation bus 4 by the emulator-enabled peripheral emulator 23.

In the present embodiment, the inverter 218 and the latch circuit 219 of the bus control circuit 21 cause the peripheral emulator 23 to operate the emulation bus 4 by the following operation.
Is supplied to the emulation bus 3.

First, in response to the interrupt request signal IQ from the peripheral emulator 23, the variation chip 1
Responds with an H level (active H) interrupt acceptance signal IK when active. The inverter 218 inverts the interrupt reception signal IK and supplies the inverted interrupt reception signal IKB to the OE terminal of the latch circuit 219. As a result, the latch circuit 219 is enabled, and the peripheral emulator 23 latches the vector code output to the emulation bus 4 in synchronization with the clock CK and outputs the vector code to the emulation bus 3. The above-described vector code via the emulation bus 3 is input to the variation chip 1, and the variation chip 1 latches the vector code at the falling edge of the interrupt acceptance signal IK and recognizes the vector code.

[0056]

As described above, the in-circuit emulator of the present invention and the emulation method thereof are:
By providing a bus control circuit for performing interface compatibility adjustment between the first and second emulation buses having different interfaces, the first and second peripheral emulators having different emulation bus interfaces can be provided.
There is an effect that emulation can be performed simultaneously in the same emulation device.

Further, the provision of the means for supplying the set value that enables emulation to the peripheral emulator is provided, so that the peripheral emulator can be emulated irrespective of the value of the emulation register of the variation chip. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an in-circuit emulator according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a bus control circuit of the in-circuit emulator according to the present embodiment.

FIG. 3 is a block diagram and a circuit showing a configuration example of the analog switch of FIG. 2;

FIG. 4 is a time chart illustrating an example of a bus switching operation of the in-circuit emulator according to the present embodiment.

FIG. 5 is a time chart showing an example of an emulation interrupt accepting operation of the in-circuit emulator of the present embodiment.

FIG. 6 is a block diagram showing an example of a conventional in-circuit emulator.

[Explanation of symbols]

 1,100 Evariation chip 2 Emulator section 3,4 Emulation bus 11 EMR 12 Bus control section 13 CPU 14 Address bus 15 Data bus 21 Bus control circuit 22,23 Peripheral emulator 41 Bus line 211 Edge detection circuit 212 Clear control circuit 213 Clock Counter 214 Hold period setting register 215 Matching circuit 216 Output control circuit 217 Analog switch 218 Inverter 219 Latch circuit

Claims (6)

(57) [Claims] 1. Central processing unit and emulation function
Only the built-in variation chip and peripheral functions
Combined with a built-in peripheral emulator, actual microphone
Emulating the operation of a computer chip
Circuit emulator,The emulation chip is used for emulation.
Emulation that retains setting values for setting functions
Register Based on the set value of the emulation register,
Select one of the first and second emulation buses
A bus control unit that performs bus control to select The central processing unit that controls execution of a user program;
With The emulator section includes: First built-in first peripheral function
Peripheral emulator, a second peripheral emulator incorporating a second peripheral function, and the first peripheral emulatorInterfaceCompliant with
First emulation with a first interface
A bus and the second peripheral emulatorinterfaceCompliant with
Second emulation with a second interface
Bus and between the first and second emulation buses.
Interface of first and second emulation buses
And a bus control circuit for performing compatibility adjustment.
Signal and theFirst andSecond peripheral emulatorNozomi
Non-selection of non-peripheral emulator
From peripheral emulatorThe interrupt request signal
Receives the supply of the interrupt acknowledgment signal supplied in response.
KeEmulate the selected peripheral emulator
Hold period corresponding to the preset reset period when
Emulation of the unselected peripheral emulator in between
As possibleThe first and second emulation bars
To perform interface compatibility coordination between
The first and second peripheral emulators are
Emulation on the configuration
An in-circuit emulator characterized by the following. 2. An edge detection circuit for detecting a falling edge of a reset signal and outputting an edge detection signal, and a clear control circuit for outputting a clear control signal in response to the supply of the edge detection signal. A clock counter that is cleared in response to the supply of the clear control signal and simultaneously starts counting clocks and outputs a count value of the count result; and sets a hold period corresponding to a reset period and outputs a hold period set value. A hold period setting register, a match circuit that compares the count value with the hold period set value and outputs a match signal when the count value matches the hold period set value, and supplies the edge detection signal and the match signal to control an analog switch described later. An output control circuit for outputting a switch control signal; and An analog switch for connecting the lower peripheral bit bus line of the emulation bus to the side of the emulation chip and the side of the second peripheral emulator; and an inverted interrupt acceptance signal by inverting an interrupt acceptance signal from the emulation chip. Output the first
And a latch circuit which is enabled when the inverted interrupt acceptance signal is input, latches data on the second emulation bus in synchronization with the clock, and outputs the data to the first emulation bus. Item 2. An in-circuit emulator according to item 1. A second inverter having an input terminal connected to a control terminal; an N-channel MOS transistor having a source connected to the input terminal, a drain connected to the output terminal, and a gate connected to the control terminal; 3. The in-circuit emulator according to claim 2, further comprising a P-channel MOS transistor having a source connected in common to a drain and a source of the N-channel MOS transistor and a gate connected to an output terminal of the inverter. 4. The latch circuit receives a clock supplied to a clock terminal, connects an output terminal of the inverter to an enable terminal, connects a second emulation bus to a data terminal, and connects a first emulation bus to an output terminal. The in-circuit emulator according to claim 2, further comprising a D flip-flop. 5. A central processing unit and an emulation function.
Only the built-in variation chip and peripheral functions
Combined with a built-in peripheral emulator, actual microphone
Emulating the operation of a computer chip
Circuit emulator emulation method
AndThe emulation chip is used for emulation.
Holds set values for setting functions, Based on the set value, first and second emulations described later
Bus control to select one of the  A first interface conforming to a first peripheral emulator
A first emulation bus with
A second interface having a second interface conforming to the emulator
Between the first and second emulation buses.
Performs emulation bus interface compatibility adjustment
A bus control circuit, wherein the bus control circuit comprises:The first and second peripheral emules
Emulator as one of the selected peripheral emulators
During the reset period,
The first and second peripheral emulations during a corresponding hold period.
Non-selected peripherals other than the selected peripheral emulator
Enable emulator emulationSaid
Execute interface compatibility adjustment at a predetermined timing
The emulation bus interface
The first and second peripheral emulators are the same emulator.
LehTaSimultaneous emulation on configuration
Emulator of an in-circuit emulator characterized by
Option. Wherein said bus control circuit, before Symbol said error variations chip interrupt acceptance signal supplying receiving the first and second of which is output in response to acceptance of the interrupt request signal from the second peripheral emulator 6. The emulation method for an in-circuit emulator according to claim 5, wherein said interface compatibility adjustment is performed by connecting emulation buses to each other.