JP3327071B2 - Ferroelectric memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device capable of achieving high integration and large capacity by forming a memory cell basically from one ferroelectric capacitor.
In particular, its device structure, device operation operation,
And a manufacturing method.

[0002]

2. Description of the Related Art An oxide ferroelectric material having a perovskite structure (such as PbZrTiO ₃ ) or an oxide ferroelectric material having a Bi-based layered perovskite structure (such as BiSr ₂ Ta ₂ O ₉ ) is insulated from a capacitor. 2. Description of the Related Art A ferroelectric storage device in which a ferroelectric capacitor is formed as a film and data is stored according to the polarization direction of the ferroelectric capacitor is known.

Hereinafter, the hysteresis characteristic of a ferroelectric capacitor will be described with reference to FIG. In FIG. 12, (a) is a hysteresis characteristic, (b) and (c)
Indicates the states of the capacitors to which the first data (hereinafter referred to as data 1) and the second data (hereinafter referred to as data 0) having opposite phases are written.

In the ferroelectric memory device, in the hysteresis characteristic shown in FIG. 12A, a positive voltage is applied to the ferroelectric capacitor (C in the figure), and a residual polarization charge of + Qr remains (FIG. 12A). A) is data 1 (first data),
The state in which the negative voltage is applied (D in the figure) and the residual polarization charge of -Qr remains (B in the figure) is used as data 0 (second data) as a nonvolatile memory.

By the way, assuming that the above-described ferroelectric capacitor is used as a nonvolatile ferroelectric memory device, a method of forming one memory cell from one selection transistor and one ferroelectric capacitor (hereinafter referred to as a memory cell). 1TR-1
CAP-type cells) are known.

FIG. 13 is a memory array diagram of a ferroelectric memory device having 1TR-1CAP type cells.

The memory array shown in FIG. 13 has a so-called folded bit line structure. In the figure, MA and MA 'are memory cells, MRA and MRA' are comparison cells, WLA and WL.
A 'is a word line, BLA, BLA' is a bit line, PLA
Is a plate electrode line, RWLA, RWLA 'are word lines for driving the comparison cell, RPLA is a plate electrode line for driving the comparison cell, and CL is each bit line BLA, B
The load capacity of LA ′ is shown. Memory cell M
A is a selection transistor TA and a ferroelectric capacitor C
A, and the memory cell MA ′ includes a select transistor TA ′ and a ferroelectric capacitor CA ′. The comparison cells MRA, MRA 'are the memory cells MA,
The comparison cell MRA is provided for comparing and reading out the data of the comparison cell MRA. In the case of the comparison cell MRA, the comparison cell MRA is constituted by the selection transistor TRA and the ferroelectric capacitor CRA.
In the case of RA ', it is composed of a select transistor TRA' and a ferroelectric capacitor CRA '.

[0008] In the ferroelectric memory device having the 1TR-1CAP type cell of FIG.
Is performed by comparison with a comparison cell MRA ′ connected to a comparison bit line BLA ′ adjacent to the read bit line BLA in the folding direction.
The data reading of A 'is performed by comparison with the comparison cell MRA connected to the comparison bit line BLA adjacent to the read bit line BLA' in the folding direction. In comparison cells MRA and MRA ', respectively, FIG.
In the hysteresis characteristic described above, the capacitor is optimally designed by adjusting, for example, the capacitor area or the bias voltage so as to be in an intermediate state when the residual polarization charge of + Qr or -Qr is read. Therefore, 1TR-1CAP
In the type cell, the potential difference between the read bit line of the read cell and the comparison bit line of the comparison cell is amplified by the sense amplifier SA to determine data.

[0009]

By the way, the above-mentioned 1
In the ferroelectric memory device having the TR-1CAP type cell, since the memory cell is composed of one selection transistor and one ferroelectric capacitor, disturb prevention at the time of data writing and data reading are prevented. It is easy to secure the operation margin of
When compared with other nonvolatile storage devices composed of a plurality of elements, for example, a flash memory, an EPROM, or the like, there is a problem that the memory cell area becomes large and the capacity cannot be increased.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a ferroelectric memory device that stores data in accordance with the polarization direction of a ferroelectric capacitor, in which basically one memory cell is used. It is an object of the present invention to provide a ferroelectric memory device that can be highly integrated and has a large capacity by being constituted only by the ferroelectric capacitors.

[0011]

In order to achieve the above object, in the ferroelectric memory device of the present invention, each main bit line wired in a column is connected to a plurality of sub-bit lines via connection means. Then, memory cells each composed of one ferroelectric capacitor are arranged at lattice positions where the sub-bit lines and a plurality of word lines wired in rows intersect, and one electrode of each ferroelectric capacitor is the sub-bit line, the other one of the electrodes is connected to the word line, the direction of polarization of the ferroelectric capacitor, strong stores either the data of the first data or the second data of opposite phase Dielectric storage device, each main bit
Read or write data corresponding to the line
Means for writing data to the memory cells.
Connected to the selected word line
Select all memory cells at once and select
All word lines that intersect with the selected sub-bit line
Then, the process is sequentially performed for each word line.

In the above ferroelectric memory device, the connection means is a MOS type semiconductor element,
One of a source electrode and a drain electrode of the S-type semiconductor element is connected to the main bit line, the other is connected to the sub-bit line, and the gate electrode is connected to a selection gate line. The main bit line and the sub-bit line are operatively connected.

Further, the ferroelectric memory device according to the present invention has a
Each main bit line wired to the
Connected to a plurality of sub-bit lines, and in a row with the sub-bit lines
At each grid position where multiple wired word lines intersect
Memory cell consisting of one ferroelectric capacitor
And one electrode of each ferroelectric capacitor is
The other bit electrode is connected to the word line above
Depending on the polarization direction of the ferroelectric capacitor.
Either the first data or the second data in opposite phase
Ferroelectric storage device for storing data of
Latch write data corresponding to the main bit line
Means for writing data to the memory cell,
All memory cells connected to the selected word line
And write the first data or the second data all at once
Data is written in the opposite phase to the write data
Write the above-mentioned reversed-phase data to the memory cell to be
In this case, the opposite phase data is written.
For memory cells that should not be
Voltage less than half was applied.

Further, in the above ferroelectric memory device ,
A voltage less than a minute is a voltage that is approximately one third of the write voltage.
It is .

In the ferroelectric memory device , the contact
The connecting means is a MOS type semiconductor element, and the MOS type
One of the source and drain electrodes of the semiconductor element is
The gate is connected to the main bit line and the other to the sub-bit line.
The electrodes are connected to the selection gate lines, respectively,
The main bit line and the sub bit line according to the applied voltage of the
Is operatively connected .

In the above ferroelectric memory device , the memory
Writing the first data to the cell depends on the selected word.
Voltage at which the potential of the selected sub-bit line is higher than the potential of the
Apply a voltage in the direction and apply the ferroelectric capacitor
Polarization in the direction of the electric field is performed,
The writing of the second data is performed by selecting the word line potential
In the voltage direction where the potential of the selected sub-bit line is lower than
Pressure to apply the ferroelectric capacitor in the direction of the applied electric field.
This is performed by polarization.

Further, the ferroelectric memory device according to the present invention has a
Each main bit line wired to the
Connected to a plurality of sub-bit lines, and in a row with the sub-bit lines
At each grid position where multiple wired word lines intersect
Memory cell consisting of one ferroelectric capacitor
And one electrode of each ferroelectric capacitor is
The other bit electrode is connected to the word line above
Depending on the polarization direction of the ferroelectric capacitor.
Either the first data or the second data in opposite phase
Ferroelectric storage device for storing data of
Latch read data corresponding to the main bit line
Means for reading data from the memory cell,
All memory cells connected to the selected word line
The sub bit line to be selected and the sub bit
Unselected word lines and selected word lines
Precharge to 1 potential and select word
The second potential is applied to the line to change the polarization of the ferroelectric capacitor.
Change the polarization state of the ferroelectric capacitor.
By detecting changes in the main bit line potential in response to
Determine the data.

[0018] In the ferroelectric memory device, the upper
After reading data from the memory cell,
Data is rewritten to the recell.

Further, in the ferroelectric memory device, the upper
The connection means is a MOS type semiconductor device, and the MO
One of the source electrode or the drain electrode of the S-type semiconductor element
To the main bit line and the other to the sub bit line.
Gate electrodes are connected to select gate lines, respectively,
The above-mentioned main bit line and sub-bit according to the applied voltage of the gate line
Operately connect to the wire.

Further, in the method of manufacturing a ferroelectric memory device according to the present invention, a step of forming a lower layer capacitor electrode of each memory cell by the sub-bit line and a step of forming a ferroelectric capacitor insulating film of each memory cell Forming an upper capacitor electrode for each memory cell, forming the word line such that the word line is connected to the upper capacitor electrode for each memory cell, and forming the main bit line. And

In the above manufacturing method, the lower capacitor electrode (the sub bit line) is formed of a first-layer platinum or oxide ceramic material, and the ferroelectric capacitor insulating film is formed of an oxide having a perovskite structure. The upper capacitor electrode is formed of a second-layer platinum or oxide ceramic material, and the word line is formed of a first ferroelectric material or an oxide ferroelectric material having a Bi-based layered perovskite structure. The main bit line is formed of a second layer of aluminum, an alloy thereof, or a composite film.

According to the ferroelectric memory device of the present invention, since the memory cell is basically composed of only one ferroelectric capacitor, the area of the memory cell is reduced, and high integration is possible. It is suitable for increasing the capacity.

Further, the bit line (main bit line) is divided into a plurality of sub-bit lines, and the memory cells are arranged at lattice positions where the sub-bit lines and a plurality of word lines arranged in rows intersect. At the time of data writing and data reading, the number of memory cells connected to the bit line (main bit line) is divided, so that disturbance at the time of data writing is reduced and a margin at the time of data reading is easily secured.

The connection between the main bit line and the sub-bit line can be controlled by operatively connecting the main bit line and the sub-bit line according to the voltage applied to the select gate line.

In writing the first data to the memory cell, a voltage is applied in a direction in which the potential of the selected sub-bit line is higher than the potential of the selected word line, and the ferroelectric capacitor is moved in the direction of the applied electric field. The second data is written to the memory cell by applying a voltage in a direction in which the potential of the selected sub-bit line is lower than the potential of the selected word line, and the ferroelectric capacitor is subjected to the applied electric field. This is possible by polarization in the direction.

In reading data from the memory cell, the ferroelectric capacitor is connected to a sub-bit line for selecting a main bit line, and the voltage of the selected word line is changed to change the polarization state of the ferroelectric capacitor. Data detection can be performed by detecting a change in the main bit line potential according to a change in the polarization state of the capacitor.

Further, by rewriting data to the memory cell after reading the data from the memory cell, the data can be recovered even if the data content in the memory cell is destroyed at the time of reading the data. .

Further, a latch type sense amplifier is provided corresponding to each main bit line, and read data or write data is latched in the sense amplifier, whereby data writing or reading and rewriting to a memory cell can be performed. Since all the memory cells connected to the selected word line are collectively performed, high-speed data writing and high-speed reading can be performed, which is preferable.

Further, the data writing includes an erasing step of writing first data or second data to all the memory cells connected to the selected word line at once, and the erasing step after the erasing step. By comprising a writing step of writing the above-mentioned reversed-phase data to a memory cell to which data of the opposite phase is to be written, it is possible to reduce a disturb voltage applied to an unselected memory cell at the time of data writing. It is possible.

Further, the above-mentioned data writing is performed for each word line in units of all the word lines intersecting the sub-bit line selected by the selection gate line, so that the non-selected memory can be written at the time of data writing. It is possible to limit the number of disturbances applied to a cell.

The data reading and rewriting are sequentially performed for each word line in units of all the word lines intersecting the sub-bit lines selected by the selection gate lines, so that the data is rewritten at the time of data rewriting. It is possible to limit the number of disturbances applied to the unselected memory cells.

According to the method of manufacturing a ferroelectric memory device of the present invention, the lower capacitor electrode of each memory cell is formed by the sub-bit line, and then the ferroelectric capacitor insulating film of each memory cell is formed. You. Then, an upper capacitor electrode is formed for each memory cell, the word line is formed such that a word line is connected to the upper capacitor electrode for each memory cell, and then a main bit line is formed.

More specifically, for example, the lower-layer capacitor electrode (the sub-bit line) is formed of a first-layer platinum or oxide ceramic material, and the ferroelectric capacitor insulating film has a perovskite structure. The upper capacitor electrode is formed of an oxide ferroelectric material or an oxide ferroelectric material having a Bi-based layered perovskite structure, the upper capacitor electrode is formed of a second layer of platinum or an oxide ceramic material, and the word line is formed of a second layer. The first bit is formed of aluminum or its alloy or composite film, and the main bit line is formed of the second layer of aluminum or its alloy or composite film.

[0034]

FIG. 1 is a diagram showing a memory array in a ferroelectric memory device according to the present invention.

In the memory array diagram of FIG. 1, only one sub-bit line SBLN, SBLN + 1 is shown for each of the two main bit lines MBLN, MBLN + 1 in the figure, but this is for convenience. In practice, a plurality of sub-bit lines are connected to each main bit line. The number of word lines intersecting the sub-bit lines is M in the figure, but specifically, about four, eight, or sixteen is appropriate.

In the memory array diagram of FIG.
WLm and WLM are word lines, MBLN and MBLN + 1 are main bit lines, SBLN and SBLN + 1 are sub-bit lines, S
TN and STN + 1 denote selection transistors for operatively connecting the main bit line and the sub-bit line according to the operation, respectively. The selection transistors STN and STN + 1 are controlled by a selection gate line SL. Each word line WL1, WL
At the intersection of the sub-bit lines SBLN and SBLN + 1 with each of the ferroelectric capacitors C1, N, Cm, N, CM, N, C1, N + 1, Cm, N + forming a memory cell, respectively.
1, CM, N + 1 are connected to a corresponding sub-bit line with one electrode and a corresponding word line with the other electrode.

The transistors PCTN, PCTN +
1 indicates that the main bit line MB
A transistor for precharging LN and MBLN + 1 to a precharge voltage VPC.
TN and CTN + 1 are transistors for connecting the main bit lines MBLN and MBLN + 1 to the respective sense amplifiers according to the column selection signal φC. The sense amplifiers SAN and SAN + 1 are respectively connected to the main bit lines MBLN,
This is a sense amplifier connected to MBLN + 1, activated by a sense enable signal φSE and sense amplifier SAN
Senses the potential difference between the node potential VN and the comparison potential VRN, and the sense amplifier SAN + 1 receives the node potential VN
+1 and the potential difference between the comparison potential VRN + 1 are sensed.

FIG. 2 is a pattern layout diagram in the memory array diagram of FIG. FIG. 3 is a cross-sectional view of the device structure viewed from the AA ′ direction in the pattern layout diagram of FIG.

FIG. 2 shows the pattern layout diagram, and FIG.
In the device structure sectional view, 1 is a silicon substrate, 2 is a LOCOS element isolation, 3 is a gate oxide film, and 4 is a source / drain n + diffusion layer region of the select transistors STN and STN + 1. Reference numeral 5 denotes a select gate line SL, which is a normal polysilicon or polycide gate electrode. 6
Are the sub-bit lines SBLN and SBLN + 1 and are also the lower electrodes of the ferroelectric capacitors. Specifically, they are formed of the first platinum layer. Reference numeral 7 denotes a ferroelectric capacitor insulating film, specifically, a ferroelectric material having hysteresis characteristics, for example, PbZrTiO ₃ , BiSr ₂ Ta
It is formed of ₂ O ₉ or the like. Reference numeral 8 denotes each ferroelectric capacitor C1, N, Cm, N, CM, N, C1, N + 1, Cm, N + 1, CM, N + 1.
The upper electrode is formed of a second platinum layer. Reference numeral 9 denotes an interlayer insulating film below the first-layer aluminum wiring, which is a normal CVD silicon oxide film.

Reference numerals 10a, 10b, 10c, and 10d denote contact holes under the first-layer aluminum wiring. Contact holes 10a and 10d respectively correspond to the first-layer aluminum wiring and the N + diffusion layer region. The first-layer aluminum wiring is connected to the first-layer platinum layer, and the contact hole 10c is for connecting the first-layer aluminum wiring to the second-layer platinum layer. Reference numerals 11a, 11b, and 11c denote first-layer aluminum wirings.
Represents a bridge wiring of a sub-bit line, the first layer aluminum wiring 11b represents word lines WL1, WLm, WLM,
The layer aluminum wiring 11c forms a pad aluminum layer for connecting the second layer aluminum wiring to the n + diffusion layer region. Reference numeral 12 denotes an interlayer insulating film below the second-layer aluminum wiring, which is a normal CVD silicon oxide film. Reference numeral 13 denotes a contact hole below the second-layer aluminum wiring, and connects the second-layer aluminum wiring to the first-layer aluminum wiring. Reference numeral 14 denotes a second-layer aluminum wiring, which forms the main bit lines MBLN and MBLN + 1.

Next, referring to the timing chart of FIG. 4 and the hysteresis characteristic of FIG. 6, a first embodiment in which data is written to a memory cell in the memory array diagram of FIG. 1 will be described in order. I do.

The timing chart of FIG. 4 shows that the word line WLm and the sub-bit lines SBLN, SBLN + 1 are selected and the first ferroelectric capacitor (memory cell) Cm, N
Is a timing chart in the case where the data (hereinafter referred to as 1 data) and the second data (hereinafter referred to as 0 data) are written into Cm, N + 1. In this case, writing of one data to the memory cell is performed by applying a voltage in a direction in which the potential of the selected sub-bit line is higher than the potential of the selected word line, and polarizing the ferroelectric capacitor in the direction of the applied electric field. Do. Writing 0 data to the memory cell is performed by applying a voltage in a direction in which the potential of the selected sub-bit line is lower than the potential of the selected word line, and polarizing the ferroelectric capacitor in the direction of the applied electric field. .

First, at time t1, the main bit line MBLN connected to the memory cell Cm, N is connected to the power supply voltage VCC (3.3
V), the main bit line M connected to the memory cell Cm, N + 1
BLN + 1 is set to the ground voltage (0 V).

Next, at time t2, the select gate line SL is set to 0.
From V to 5 V, the selected word line WLm to which the memory cells Cm, N, Cm, N + 1 are connected is connected to the power supply voltage VCC (3.3 V).
Then, non-selected word lines WL1 to WLM other than WLm are set to (1/2) VCC (1.65 V). As a result, 0
The ferroelectric capacitor Cm, N + 1 of the memory cell to which data is to be written has a hysteresis characteristic shown in FIG.
The state moves to the point state by time t3, and the writing of 0 data is completed.

Next, at time t3, the selected word line WLm falls to the ground voltage (0 V). As a result, the ferroelectric capacitor Cm, N of the memory cell to which one data is to be written
Moves to the state of point C in the hysteresis characteristic shown in FIG. 6 by time t4, and the writing of one data is completed. Finally, at time t4, all the main bit lines MBLN,
After MBLN + 1 falls to 0V, select gate line S
L, all word lines WL1 to WLM are connected to the ground voltage (0
When the voltage falls to V), the write operation ends.

During the data writing period, unselected word lines WL1 to WLM other than WLm are set to (1/2) VCC.
(1.65 V). As a result, the ferroelectric capacitors Cm, N, C connected to the selected sub-bit line are set.
Unselected memory cells other than m, N + 1 have (1/2) VCC
A disturb voltage of (1.65 V) is applied. The disturb voltage causes a problem when the disturb voltage is applied in a direction in which data opposite to the data content recorded in the non-selected memory cell is written.

For example, when one data is recorded in a non-selected memory cell, as a result of the application of the disturb voltage, the hysteresis characteristic shown in FIG.
The polarization state of the ferroelectric capacitor changes up to one point. When 0 data is recorded in the unselected memory cells, the disturb voltage is applied, and as a result, the polarization state of the ferroelectric capacitor changes from point B to point B1 in the hysteresis characteristic of FIG. However, the disturb for the unselected memory cell is such that when 1 data is recorded in the unselected memory cell, 0 data is recorded in the unselected memory cell as long as the polarization state does not change from point A to point A3. In this case, as long as the polarization state does not change from the point B to the point B3, the data is not inverted, and there is no problem.

Next, referring to the timing chart of FIG. 5 and the hysteresis characteristics of FIG. 6, a description will be given of a second embodiment in which data is written to a memory cell in the memory array diagram of FIG. I do. The second embodiment shaped state, advantages with respect to the first embodiment of FIG. 4, disturbance voltage applied to the non-selected memory cells during data writing, the (1/2) VCC (1.65V) ( 1 /
3) It can be reduced to VCC (1.1V).

In the case of FIG. 5, similarly to FIG.
FIG. 11 is a timing chart in the case where m and the sub-bit lines SBLN, SBLN + 1 are selected, and 1 data is written to the ferroelectric capacitor (memory cell) Cm, N and 0 data is written to Cm, N + 1. In the case of the second embodiment of FIG. 5, unlike the case of the first embodiment of FIG. 4, 0 data (or 1 data may be used) for all the memory cells connected to the selected word line. ), And after the erasing step, a writing step of writing the reversed-phase data to a memory cell to which data having the opposite phase to the erasing data is to be written. Is configured.

In this case, when erasing data (writing 0 data) to the memory cell, a voltage is applied in a direction in which the potential of the selected sub-bit line is lower than the potential of the selected word line, and the ferroelectric capacitor is applied. This is performed by polarization in the direction of the electric field. In addition, when writing the reversed-phase data (1 data) to the memory cell, a voltage is applied in a direction in which the potential of the selected sub-bit line is higher than the potential of the selected word line, and the ferroelectric capacitor is moved in the direction of the applied electric field. This is performed by polarization.

First, at time t1, all main bit lines M
BLN and MBLN + 1 are set to the ground voltage (0 V), the selection gate line SL is changed from 0 V to 5 V, and the selected word line WLm is set to the power supply voltage VCC (3.3 V). WL1 to WLM are set to the ground voltage (0 V). As a result, the ferroelectric capacitors Cm, N of all the memory cells connected to the selected word line WLm
, Cm, N + 1 move to the state of point D in the hysteresis characteristic shown in FIG. 6 by time t2, and the erasing (writing of 0 data) is completed.

Next, at time t2, the selected gate line SL and the selected word line WLm are dropped to the ground voltage (0 V), and subsequently, the memory cells Cm, N to which the opposite phase data (1 data) is to be written. Connected main bit line MBLN
Is set to the power supply voltage VCC (3.3 V), and the main bit line MBLN + 1 connected to the memory cell Cm, N + 1 that can remain erased data (0 data) is set to (1/3) VCC (1.1 V). I do. Next, at time t3, the selection gate line SL is set to 5 V, the selected word line WLm is set to the ground voltage (0 V), and all non-selected word lines WL1 to WLM other than WLm are set to (2/3) VCC.
(2.2V). As a result, the ferroelectric capacitor Cm, N of the memory cell to which the opposite-phase data (1 data) is to be written moves from the point D to the point C in the hysteresis characteristic shown in FIG. Writing is completed. Finally, at time t4, all the main bit lines MBLN and MBLN + 1 are set to (1/3) VCC (1.1 V).
Then, the select gate line SL and all the word lines WL1 to WLM are dropped to the ground voltage (0 V), thereby completing the write operation.

During the writing period of the reverse phase data, WL
unselected word lines WL1 to WLM other than m are (2/3) VC
C (2.2 V). As a result, (1/3) VCC (1.V) is applied to non-selected memory cells other than Cm, N and Cm, N + 1 connected to the selected sub-bit line. 1V) is applied. The disturb voltage causes a problem when the disturb voltage is applied in a direction in which data opposite to the data content recorded in the non-selected memory cell is written.

For example, when one data is recorded in a non-selected memory cell, as a result of the application of the disturb voltage, the hysteresis characteristic shown in FIG.
The polarization state of the ferroelectric capacitor changes up to two points. When 0 data is recorded in the unselected memory cells, the disturb voltage is applied. As a result, in the hysteresis characteristic shown in FIG. 6, the polarization state of the ferroelectric capacitor changes from point B to point B2. However, the second in FIG.
It can be seen from the hysteresis characteristic of FIG. 6 that the disturbance of the unselected memory cell can be significantly reduced in the case of the first embodiment as compared with the case of the first embodiment in FIG. Therefore, when 1 data is recorded in a non-selected memory cell, points A to A3 are set. When 0 data is recorded in a non-selected memory cell, points B to B3 are set.
It is impossible that the polarization state changes to the point and the data is inverted.

In the first embodiment shown in FIG. 4 and the second embodiment shown in FIG. 5, batch data writing is performed on a memory cell connected to one selected word line. Alternatively, data writing may be performed sequentially for each word line, with all word lines intersecting the sub-bit line selected by the selection gate line as a unit. For example, in the case of the first embodiment of FIG. 4 and the second embodiment of FIG.
The word lines WL1 to WLM are taken as one unit and WL1, WL
2,... WLM may be written in this order. Such data writing in units of blocks makes it possible to limit the number of disturbances to the non-selected memory cells at the time of data writing to a maximum of (M-1) times, which is preferable from the viewpoint of preventing disturbance.

[0056] Subsequently, in FIG. 1, in the memory array diagram, a first embodiment in which data is read to the memory cell, a timing chart of FIG. 7, and in sequence with reference to Hisurishisu characteristics of FIG. 9 explain.

The timing chart of FIG. 7 shows that one word recorded on the ferroelectric capacitor (memory cell) Cm, N and one data Cm, N + are selected by selecting the word line WLm and the sub-bit lines SBLN, SBLN + 1. FIG. 11 is a timing chart in a case where 0 data recorded in 1 is read out, and thereafter, 1 data is rewritten in Cm, N and 0 data is rewritten in Cm, N + 1. In this case, to read data from the memory cell, the main bit line is connected to the sub-bit line, the word line voltage to be selected is changed, the polarization state of the ferroelectric capacitor is changed, and the ferroelectric capacitor is read. Data is determined by detecting a change in the main bit line potential according to a change in the polarization state. The rewriting of data to the memory cells is the same as that in the first embodiment of the data writing method of FIG.

First, at time t1, the precharge signal φP
By raising C to the power supply voltage VCC (3.3 V) and raising the column selection signal φC to 5 V, the main bit lines MBLN and MBLN + 1 are precharged to the precharge voltage VPC (0 V) by time t2, The main bit lines MBLN and MBLN + 1 are connected to the nodes VN and VN + 1 of the respective sense amplifiers.

Next, at time t2, the precharge signal φP
C is dropped to 0V and the main bit lines MBLN, MBLN +
After the 1 is in a floating state, the select gate line SL is changed from 0V to 5V, and the read memory cells Cm, N, Cm, N + 1 are read.
Is changed from 0 V to the power supply voltage V
Start up to CC (3.3V). As a result, the ferroelectric capacitors Cm, N, Cm, N + 1 of all the memory cells connected to the selected word line WLm change to the polarization state in which 0 data is written.

Therefore, the polarization state of the memory cell Cm, N in which one data is recorded is inverted, and the main bit line MBL
The potential change ΔV (+) of N is large and is represented by the following equation (1). In addition, Cm, N +
In 1, the polarization state does not change, the potential change ΔV (−) of the main bit line MBLN ₊ 1 is small, and is expressed by the following equation (2). ΔV (+) = VCC · [C (+) / ｛(M−1) · C (−) + C (+) + CBL｝] (1) ΔV (−) = VCC · [C (−) / {M · C (−) + CBL}] (2) In the expressions (1) and (2), C (+) is the capacitance when the polarization state of the memory cell is inverted, and C (−)
Is a capacitance when the polarization state of the memory cell is not inverted, and CBL is a bit line capacitance. M is the number of word lines connected to the sub-bit lines. In this case, M is eight, and the power supply voltage VCC is 3.3 V. In the case of a general memory cell, C (+) ≒ 500fF, C (−) ≒ 100f
F, CBL ≒ 1000 fF, so equation (1)
From equation (2), ΔV (+) and ΔV (−) are as follows. ΔV (+) = 0.75V ΔV (−) = 0.18V

The above can be illustrated and described also in the hysteresis characteristic of FIG. That is, in the case of the ferroelectric capacitor Cm, N of the memory cell in which 1 data has been recorded, the state shifts from the state at the point A to the state at the point E, and is inverted to the polarization state of the 0 data. Then, non-selected memory cells C1, N to C other than Cm, N connected to the sub-bit line SBLN.
M and N are the memory cells where one data is recorded,
The memory cell moves from the state of point A to the state of point G, and in the case of a memory cell in which 0 data has been recorded, moves from the state of point B to the state of point I, but the original state is maintained.

In the case of the ferroelectric capacitor Cm, N + 1 of the memory cell in which 0 data has been recorded, the state moves from the state at the point B to the state at the point F, but the polarization state of the 0 data does not change. Then, non-selected memory cells C1, N + 1 to CM, N + other than Cm, N + 1 connected to the sub-bit line SBLN + 1.
1 is A for a memory cell where one data is recorded.
The memory cell moves from the point state to the point H state, and in the case of a memory cell in which 0 data is recorded, the state moves from the point B state to the J point state, but the original data state is maintained.
In the hysteresis characteristic shown in FIG. 9, the linear gradient of the dashed-dotted line AE represents the capacitance C (-) when the polarization state is reversed, and the linear gradient of the dashed-dotted line BF is , The capacitance C (−) when the polarization state is not inverted.

Next, at time t3, the selected gate line SL and then the selected word line WLm are lowered to 0 V, and at time t4, the sense enable signal φSE is changed to the power supply voltage VCC (3.3).
By raising the voltage to V), the sense-up SAN and SAN + 1 connected to each main bit line are activated. As a result, the sense-up SAN generates the potential change ΔV (+) (node potential V
N) and the potential difference between the reference potential VRN and the sense amplifier SAN + 1, and the potential change ΔV (−) of the main bit line MBLN + 1 (node potential VN + 1) and the comparison potential VR.
The potential difference of N + 1 is sensed.

Here, the respective comparison potentials VRN, VR
For all of N + 1, the expected change amount of the main bit line potential, ΔV (+) = 0.75V, and ΔV (−) = 0.
Approximately intermediate value of 18V VRN to VRN + 1 = 0.46V
Set to about. As a result, the sense amplifier SAN has
One data recorded in the read memory cell Cm, N is sense-latched by time t5, and the main bit line M
The potential of BLN is set to the power supply voltage VCC (3.3 V), and 0 data recorded in the read memory cell Cm, N + 1 is sense latched in the sense amplifier SAN + 1, and the potential of the main bit line MBLN + 1 is The potential is set to the ground voltage (0 V).

Now, from time t5, rewriting of data to the read memory cells Cm, N, Cm, N + 1 is started.

First, at time t5, select gate line SL is set to 0.
From V to 5 V, the selected word line WLm to which the memory cells Cm, N, Cm, N + 1 are connected is connected to the power supply voltage VCC (3.3 V).
All the non-selected word lines WL1 to W
Set LM to (1/2) VCC (1.65V). As a result, the ferroelectric capacitor Cm, N + 1 of the memory cell to which the 0 data is to be written becomes D.sub.D in the hysteresis characteristic of FIG.
The state moves to the point state by time t6, and the rewriting of 0 data is completed.

Next, at time t6, the selected word line WLm falls to the ground voltage (0 V). As a result, the ferroelectric capacitor Cm, N of the memory cell to which one data is to be written becomes
In the hysteresis characteristic shown in FIG. 9, the state moves to the point C by time t7, and the rewriting of one data is completed.
Finally, at time t7, the column selection signal φC falls to 0 V, thereby disconnecting the main bit lines MBLN and MBLN + 1 from the nodes VN and VN + 1 of the respective sense amplifiers, and then changing the precharge signal φPC to the power supply voltage VCC.
(3.3 V), all the main bit lines MBLN, MBLN + 1 are set to the precharge voltage VPC.
(0 V). Then, select gate line S
L, all word lines WL1 to WLM fall to the ground power supply voltage (0 V), thereby completing the write operation.

During the data rewriting period, non-selected word lines WL1 to WLM other than WLm are set to (1/2) VCC
(1.65 V). As a result, (1/2) VCC (1.65 V) is applied to non-selected memory cells other than Cm, N and Cm, N + 1 connected to the selected sub-bit line. ) Is applied. This is the same as the case of the first embodiment of the data writing described with reference to FIG.

Next, in the memory array diagram of FIG. 1, a second embodiment in which data is read from a memory cell will be described with reference to the timing chart of FIG.
Will be described in order with reference to the hysteresis characteristic of FIG. The advantage of the second embodiment over the first embodiment of FIG. 7 is that the disturb voltage applied to the non-selected memory cells at the time of data writing is reduced from (1/2) VCC (1.65 V) to (1
/ 3) It can be reduced to VCC (1.1V).

In the case of FIG. 8, as in the case of FIG. 7, one data recorded in the memory cell Cm, N and Cm, N + 1
Is read out, and then Cm, N
FIG. 9 is a timing chart when rewriting 1 data and 0 data to Cm, N + 1. In this case, reading of data to the memory cell is the same as that those of the first embodiment forms state of the data reading method of Figure 7. Also,
The rewriting of data to the memory cells is the same as in the second embodiment of the data writing method of FIG.

First, at time t1, precharge signal φP
By raising C to the power supply voltage VCC (3.3 V) and raising the column selection signal φ to 5 V, the main bit lines MBLN and MBLN + 1 are precharged to the precharge voltage VPC (0 V) by time t2; The main bit lines MBLN and MBLN + 1 are connected to the nodes VN and VN + 1 of the respective sense amplifiers.

Next, at time t2, precharge signal φPC
To 0V and the main bit lines MBLN, MBLN + 1
Is set to a floating state, the select gate line SL is read from 0 V to 5 V, and the selected word line WLm to which the memory cells Cm, N, Cm, N + 1 are connected is changed from 0 V to the power supply voltage VC.
Start up to C (3.3V). As a result, the ferroelectric capacitors Cm, N, Cm, N + 1 of all the memory cells connected to the selected word line WLm change to the polarization state in which 0 data is written.

Therefore, the memory cell Cm, N in which one data has been recorded has its polarization state inverted and the main bit line MBL
The potential change ΔV (+) of N is large, and ΔV (+) = 0.75V is expected as described in the first embodiment of FIG. Also, the memory cell Cm, N + 1 where 0 data is recorded
, The polarization state is not inverted, the potential change ΔV (−) of the main bit line MBLN + 1 is small, and ΔV (−) = 0.18 V is expected as described in the first embodiment of FIG. .

The above can be illustrated and described also in the hysteresis characteristic shown in FIG.
This is the same as the embodiment.

Next, at time t3, the select gate line SL and then the select gate line WLm are dropped to 0 V. At time t4,
Sense enable signal φSE is supplied to power supply voltage VCC (3.3
By raising the voltage to V), the sense amplifiers SAN and SAN + 1 connected to the respective main bit lines are activated. As a result, one data is sense-latched to the sense amplifier SAN by time t5, and the main bit line MBL is sensed.
The potential of N is set to power supply voltage VCC (3.3 V).
The sense amplifier SAN + 1 senses and latches 0 data, and the potential of the main bit line MBLN + 1 is set to the ground voltage (0 V).

Now, from time t5, data rewriting to the read memory cells Cm, N, Cm, N + 1 is started.

First, at time t5, the column selection signal φC falls to 0 V, thereby causing the main bit lines MBLN and MBLN to fall.
BLN + 1 is connected to each sense amplifier node VN, VN
After disconnection from N + 1, the precharge signal φPC is raised to the power supply voltage VCC (3.3 V), thereby precharging all the main bit lines MBLN and MBLN + 1 to the precharge voltage VPC (0 V). Subsequently, the selection gate line SL is changed from 0 V to 5 V, and the selected word line WLm
To the power supply voltage VCC (3.3 V) and all the non-selected word lines WL1 to WLM other than WLm to the ground voltage (0 V).
Set to. As a result, the ferroelectric capacitors Cm, N, Cm, N + of all the memory cells connected to the selected word line WLm
1 moves to the state of point D in the hysteresis characteristic of FIG. 9 by time t6, and the erasing (writing of 0 data) is completed.

Next, at time t6, the selected gate line SL and the selected word line WLm fall to the ground voltage (0 V). Next, the power supply of the sense amplifier system is maintained at the power supply voltage VCC (3.3 V) on the high side and the ground voltage (0 V) on the low side.
From (1/3) VCC (1.1V). Next, the column selection signal φC is raised to 5 V, and again the potential of the main bit line MBLN is set to the power supply voltage VCC (3.3 V) by the sense amplifier SAN, and the potential of the main bit line MBLN + 1 is set to (1) by the sense amplifier SAN + 1. / 3) VCC (1.1
V). Next, at time t7, the selected gate line SL is set to 5 V, the selected word line WLm is set to the ground voltage (0 V), and W
All non-selected word lines WL1 to WLM other than Lm
(2/3) Set to VCC (2.2V).

As a result, the memory cell Cm, N to which the opposite-phase data (1 data) is to be written moves from the point D to the point C in the hysteresis characteristic of FIG. Complete. Finally, at time t8,
The precharge signal φPC is raised to the power supply voltage VCC (3.3 V) after the main bit lines MBLN and MBLN + 1 are disconnected from the nodes VN and VN + 1 of the respective sense amplifiers by lowering the column selection signal φC to 0V. Allows all main bit lines MBLN, MB
LN + 1 is charged to the precharge voltage VPC ((1/3) VCC
(1.1 V)). Thereafter, the select gate line SL and all the word selections WL1 to WLM are dropped to the ground voltage (0 V), thereby completing the rewrite operation.

During the rewriting period of the reverse phase data, W
Unselected word lines WL1 to WLM other than Lm are (2/3) V
CC (2.2 V). As a result, (1/3) VCC (1.V) is applied to non-selected memory cells other than Cm, N and Cm, N + 1 connected to the selected sub-bit line. 1V) is applied. This is similar to the second embodiment of the data write described in FIG.
Compared with the example of data reading of the first embodiment,
Disturb for unselected memory cells can be significantly reduced.

In both the first embodiment shown in FIG. 7 and the second embodiment shown in FIG. 8, data is read and re-written collectively from the memory cells connected to one selected word line. However, the unit of data read and rewrite is data read and rewrite in order for each word line in units of all word lines intersecting the sub-bit line selected by the select gate line. May be performed. For example, in the case of the first embodiment shown in FIG. 7 and the second embodiment shown in FIG. 8, data reading and rewriting are performed in the order of WL1, WL2,. May be read and rewritten. By reading and rewriting data in block units as described above, it is possible to limit the number of disturbances to the non-selected memory cells at the time of data rewriting to a maximum of (M-1) times, which is preferable from the viewpoint of preventing disturbance. It is.

FIG. 10 is a diagram showing an example of a specific circuit diagram of the sense amplifiers SAN and SAN + 1 in the memory array diagram of FIG.

In the sense amplifier of FIG. 10, a p-channel MOS (hereinafter referred to as PMOS) transistor T
P1, an n-channel MOS (hereinafter referred to as NMOS) transistor TN1 and a PMOS transistor TP2,
A latch circuit is constituted by a complementary inverter circuit constituted by the NMOS transistor TN2. This latch circuit comprises a PMOS transistor TP3, an NMO
S transistor TN3 receives sense enable signal φSE
To amplify and latch the potential difference between the nodes N1 and N2.

For each main bit line, FIG.
By having a latch type sense amplifier as shown in FIG. 0, read data or write data can be latched in the sense amplifier. As a result, as shown in the examples of FIG. 4, FIG. 5, FIG. 7, and FIG. 8, writing, reading, and rewriting of data corresponding to a memory cell are performed collectively for all the memory cells connected to the selected word line. be able to.

Next, an example of a process flow for manufacturing the ferroelectric memory device of the present invention will be described.

FIGS. 11A to 11E are views showing a process flow up to the device structure sectional view of FIG.

First, as shown in FIG. 11A, a LOCOS element isolation region 2 and a gate oxide film 3 are formed on a silicon substrate 1 and a polysilicon or polycide gate electrode 5 is formed. Until the source / drain n + diffusion layer region 4 is formed by implantation, a normal CM
It is the same as the OS process.

Next, as shown in FIG. 11B, the first platinum layer is formed by, for example,
0 nm, and a ferroelectric thin film (for example, P
bZrTiO ₃ , BiSr ₂ Ta ₂ O ₉ ) is formed to a thickness of about 200 nm by sputtering or the like. Next, the first platinum layer and the ferroelectric thin body are simultaneously etched by RIE or the like to form a ferroelectric capacitor lower electrode 6 and a ferroelectric capacitor insulating film 7.

Next, as shown in FIG. 11 (c), the platinum layer as the second layer is formed by, for example,
Then, the upper electrode 8 of the ferroelectric capacitor is formed by etching by RIE or the like.

Next, as shown in FIG.
After forming the interlayer insulating film (SiO ₂ film) 9 by the method,
Contact holes 10a, 10b, 10c, and 10d are formed, and then a first aluminum layer is formed by a sputtering method and further etched to form a bridge wiring 11a of a sub-bit line, a word line 11b, and a pad aluminum. The layer 11c is formed.

Finally, as shown in FIG.
After forming an interlayer insulating film (SiO ₂ film) 9 by the method D, a contact hole 13 is formed, and then a second aluminum layer is formed by a sputtering method and further etched to form a main bit line. 14 is formed. As a result of the above process flow, a device structure sectional view of FIG. 3 is obtained.

[0092]

As described above, according to the ferroelectric memory device of the present invention, each main bit line wired in a column is connected to a plurality of sub-bit lines via connection means.
Memory cells each composed of one ferroelectric capacitor are arranged at lattice positions where the sub-bit lines and a plurality of word lines arranged in rows intersect. As a result, basically 1
For a memory cell consisting of ferroelectric capacitors,
It is possible to provide a ferroelectric memory device in which data can be written and read, and which can have high integration and large capacity.

[Brief description of the drawings]

FIG. 1 is a diagram showing a memory array of a ferroelectric memory device according to the present invention.

FIG. 2 is a diagram showing a pattern layout in the memory array diagram of FIG. 1;

FIG. 3 is a diagram illustrating a pattern layout in FIG.
FIG. 3 is a diagram showing a cross section of the device structure viewed from the direction A ′.

FIG. 4 is a diagram showing a timing chart in the case of the first embodiment for writing data in the memory array diagram of FIG. 1;

FIG. 5 is a diagram showing a timing chart in the case of the second embodiment for writing data in the memory array diagram of FIG. 1;

6 is a first data write embodiment of FIG. 4 and FIG.
FIG. 9 is a diagram illustrating a hysteresis characteristic of a ferroelectric capacitor for describing the second data writing embodiment of FIG.

FIG. 7 is a diagram showing a timing chart in the case of the first embodiment for reading data in the memory array diagram of FIG. 1;

FIG. 8 is a diagram showing a timing chart in the case of the second embodiment for reading data in the memory array diagram of FIG. 1;

9 is a diagram illustrating a hysteresis characteristic of a ferroelectric capacitor for describing the first data read embodiment of FIG. 7 and the second data read embodiment of FIG. 8;

FIG. 10 is a diagram showing a specific circuit of a sense amplifier.

FIG. 11 is a view showing a process flow of the ferroelectric memory device according to the present invention.

FIG. 12 is a diagram showing a hysteresis characteristic of a ferroelectric capacitor and a state of a capacitor in which first data and second data having phases opposite to each other are written.

FIG. 13 is a diagram showing a memory array of a ferroelectric memory device having 1TR-1CAP type cells.

[Explanation of symbols]

WL1 to WLM ... word line SL ... selection gate line φC ... column selection signal φPC ... precharge signal φSE ... sense enable signal C1, N to CM, N, C1, N + 1 to CM, N + 1 ...
Memory cells (ferroelectric capacitors) STN, STN + 1 ... selection transistors CTN, CTN + 1 ... precharge selection transistors PCTN, PCTN + 1 ... column selection transistors SAN, SAN + 1 ... sense amplifiers MBLN, MBLN + 1 ... main bit lines SBLN, SBLN + 1 ... sub-bit lines VPC ... Precharge voltage VRN, VRN + 1 ... Comparison potential VN, VN + 1 ... Node potential 1 ... Silicon substrate 2 ... LOCOS element isolation 3 ... Gate oxide film 4 ... Source / drain n + diffusion layer region 5 ... Polysilicon or polycide gate electrode 6 ... Ferroelectric capacitor lower electrode 7 ... Ferroelectric capacitor insulating film 8 ... Ferroelectric capacitor upper electrode 9 ... Interlayer insulating film under the first layer aluminum wiring 10a, 10b, 10c, 10 d: Contact holes 11a, 11b, 11c under the first-layer aluminum wiring 12 ... Interlayer insulating film under the second-layer aluminum wiring 13 ... Contact holes under the second-layer aluminum wiring 14 … Second layer aluminum wiring

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/108 29/788 29/792 (56) References JP-A-6-77434 (JP, A) JP-A-7-235648 (JP, A) JP-A-7-115141 (JP, A) JP-A-4-78098 (JP, A) JP-A-5-266676 (JP, A) JP-A-7-226443 (JP, A) International Published 94/10702 (WO, A1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/10 451 G11C 11/22 G11C 14/00 H01L 21/8242 H01L 21/8247 H01L 27/108 H01L 29/788 H01L 29/792

Claims (9)

(57) [Claims] 1. A grid position where each of main bit lines arranged in a column is connected to a plurality of sub-bit lines via connection means, and the sub-bit lines intersect with a plurality of word lines arranged in a row. A memory cell composed of one ferroelectric capacitor, one electrode of each ferroelectric capacitor is connected to the sub-bit line, and the other electrode is connected to the word line; A ferroelectric memory device that stores either first data or second data having a phase opposite to each other depending on the polarization direction of a body capacitor, and reads or writes data corresponding to each main bit line. Means for latching data, wherein writing or reading data to or from a memory cell is performed.
A ferroelectric memory device that performs the operation for all the memory cells connected to the selected word line in a lump and sequentially performs the operation for each word line in units of all the word lines crossing the selected sub-bit line. . 2. The connection means is a MOS semiconductor device, wherein one of a source electrode and a drain electrode of the MOS semiconductor device is connected to the main bit line, the other is connected to the sub bit line, and a gate electrode is connected to the gate electrode. 2. The ferroelectric memory device according to claim 1, wherein each is connected to a select gate line, and the main bit line and the sub bit line are operatively connected according to a voltage applied to the select gate line. 3. A grid position where each of the main bit lines arranged in a column is connected to a plurality of sub-bit lines via connection means, and the plurality of word lines arranged in a row intersect with the sub-bit lines. A memory cell composed of one ferroelectric capacitor, one electrode of each ferroelectric capacitor is connected to the sub-bit line, and the other electrode is connected to the word line; What is claimed is: 1. A ferroelectric memory device storing either first data or second data having a phase opposite to each other according to a polarization direction of a body capacitor, and latching write data corresponding to each main bit line. Means for writing data to the memory cells, and collectively perform the first write to all the memory cells connected to the selected word line.
After writing the second data or the second data, the opposite-phase data is written to a memory cell to which the opposite-phase data is to be written. In this case, the opposite-phase data is written. A ferroelectric memory device in which a voltage equal to or less than half of a write voltage is applied to a memory cell that should not be used. 4. The ferroelectric memory device according to claim 3, wherein said half or less voltage is substantially one third of said write voltage. 5. The connection means is a MOS type semiconductor device, wherein one of a source electrode and a drain electrode of the MOS type semiconductor device is connected to the main bit line, the other is connected to the sub bit line, and a gate electrode is connected to the gate electrode. 4. The ferroelectric memory device according to claim 3, wherein each is connected to a select gate line, and the main bit line and the sub bit line are operatively connected according to a voltage applied to the select gate line. 6. A method of writing first data to a memory cell, wherein a voltage is applied in a voltage direction in which a selected sub-bit line potential is higher than a selected word line potential, and the ferroelectric capacitor is placed in the direction of the applied electric field. The writing of the second data to the memory cell is performed by applying a voltage in a voltage direction in which the potential of the selected sub-bit line is lower than the potential of the selected word line, and applying the ferroelectric capacitor to the memory cell. 4. The ferroelectric memory device according to claim 3, wherein the ferroelectric memory device performs polarization by polarizing in a direction of an electric field. 7. A grid position where each main bit line wired in a column is connected to a plurality of sub-bit lines via connection means, and said sub-bit line and a plurality of word lines wired in a row intersect. A memory cell composed of one ferroelectric capacitor, one electrode of each ferroelectric capacitor is connected to the sub-bit line, and the other electrode is connected to the word line; What is claimed is: 1. A ferroelectric memory device for storing either first data or second data having phases opposite to each other according to the polarization direction of a body capacitor, and latching read data corresponding to each main bit line. The data read from the memory cell is performed collectively for all the memory cells connected to the selected word line, and the selected sub bit line and the sub A non-selected word line and a selected word line that intersect with the bit line are precharged to a first potential, and a second potential is applied to the selected word line to change the polarization state of the ferroelectric capacitor. A ferroelectric memory device that determines data by detecting a change in a main bit line potential according to a change in a polarization state of a dielectric capacitor. 8. The ferroelectric memory device according to claim 7, wherein after the data is read from the memory cell, the data is rewritten to the memory cell. 9. The connection means is a MOS type semiconductor device, wherein one of a source electrode and a drain electrode of the MOS type semiconductor device is connected to the main bit line, the other is connected to the sub bit line, and a gate electrode is connected to the gate electrode. 8. The ferroelectric memory device according to claim 7, wherein each is connected to a select gate line, and the main bit line and the sub bit line are operatively connected according to a voltage applied to the select gate line.