JP3307144B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device having a panel structure in which a display substrate and a counter substrate are joined to each other. More specifically, the present invention relates to a display substrate having a so-called on-chip black structure in which a light-shielding pattern is formed in addition to a wiring pattern. More specifically, the present invention relates to a technique for lowering the resistance of a wiring pattern using a light-shielding pattern in an auxiliary manner.

[0002]

2. Description of the Related Art FIG. 9 is a schematic equivalent circuit diagram showing an example of a conventional display substrate. On the display substrate 100, a gate wiring pattern 101 extending in the row direction and a signal wiring pattern (metal pattern) 102 extending in the column direction are formed.
The auxiliary wiring pattern 1 is arranged in parallel with the gate wiring pattern 101.
03 is also formed. The gate wiring pattern 101 is connected to a vertical scanning circuit 104 integrated on the same substrate, while the signal wiring pattern 102 is connected to a horizontal scanning circuit 106 via an image signal supply switch 105 integrated on the same substrate. ing. The vertical scanning circuit 104 and the horizontal scanning circuit 106 receive a power supply voltage, a clock pulse,
A start pulse or the like is supplied. An image signal is externally supplied to the image signal supply switch 105. A pixel is defined at the intersection of the gate wiring pattern 101 and the signal wiring pattern 102. Each pixel includes a liquid crystal cell LC, a thin film transistor Tr for driving the liquid crystal cell LC, and a capacitor Cs.
Are formed. The gate electrode of the transistor element Tr forms a part of the gate wiring pattern 101, the source electrode is connected to the corresponding signal wiring pattern 102, and the drain electrode is connected to the liquid crystal cell LC. The above-described capacitance element Cs is connected in parallel with the liquid crystal cell LC, and one electrode is held at a common potential via the auxiliary wiring pattern 103. The vertical scanning circuit 104 sequentially includes the gate wiring pattern 101.
To the transistor element Tr in line-sequential manner.
Open / close control. The horizontal scanning circuit 106 synchronizes with the image signal supply switch 105 and the signal wiring pattern 102.
The image signal is supplied via the. This image signal is written into the liquid crystal cell LC through the transistor element Tr selected in a line-sequential manner. The capacitive element Cs additionally holds the charge of the written image signal.

[0003]

As described above, the gate wiring pattern 10 is formed on the display substrate 100 along the row direction.
1 and an auxiliary wiring pattern 103 are formed, and a signal wiring pattern 102 is formed along the column direction. Generally, from the viewpoint of a wiring process, a signal wiring pattern is formed of a metal film made of aluminum or the like, and a gate wiring pattern and an auxiliary wiring pattern crossing the signal wiring pattern are formed of a semiconductor film such as polycrystalline silicon or amorphous silicon. ing. This semiconductor film is doped with impurities at a relatively high concentration to reduce its resistance. However, the semiconductor film has a relatively high resistance as compared with a metal film and has a resistance of 30 Ω / □ or more. The high resistance of the wiring pattern has various adverse effects on the performance of the display device. First, shading or the like occurs due to the high wiring resistance, which impairs the in-screen uniformity of the displayed image quality. For example, if the resistance of the gate wiring pattern is large, the response of the gate signal becomes worse as the distance from the vertical scanning circuit increases. In a pixel near the vertical scanning circuit, the gate signal keeps a substantially rectangular shape, whereas in a pixel far from the vertical scanning circuit, the rise and fall of the gate signal are extremely extreme. As the response of the gate signal deteriorates,
Shading appears on the screen and significantly impairs image quality.
Such deterioration of the image quality has become a serious problem particularly as the screen size and definition of the display device have been increased. However, as long as a semiconductor film is used as a material for the wiring pattern, there is a limit in reducing the resistance. Secondly, since a parasitic capacitance is generated at the intersection of the gate wiring pattern and the auxiliary wiring pattern with the signal wiring pattern, when the wiring resistance is high, the potential of the signal wiring pattern is disturbed by the capacitive coupling, which adversely affects the image quality. . Third, when the wiring width is increased to reduce the wiring resistance, the aperture ratio of the pixel is sacrificed and the transmittance of the display device is reduced. Fourth, when the thickness of the semiconductor film is increased in order to reduce the wiring resistance, the step at the end face of the wiring pattern becomes large. This step causes disconnection of the wiring pattern and deteriorates the electrical insulation of the interlayer insulating film. As a result, the production yield of the display substrate is reduced.

In recent years, in order to reduce the resistance of a gate wiring pattern and an auxiliary wiring pattern, a thin film transistor element using a metal gate electrode has been developed.
-3286. In this example, a single-layer metal film is used as a gate electrode. However, a problem arises because the metal film undergoes a thermoplastic change and a shape change. For example, when aluminum is used as a gate electrode material, a so-called hillock is generated due to a heat treatment applied in a later step, which causes a short circuit defect or the like. In addition, the electric resistance tends to fluctuate due to the heat history applied in the post-process. Furthermore, the heat treatment causes a plastic change of the metal film or diffusion of metal atoms, which deteriorates transistor characteristics.

[0005]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, an object of the present invention is to reduce the resistance of a wiring pattern made of a semiconductor film. In order to achieve this object, in the present invention, the resistance of the wiring pattern is reduced by using a light shielding pattern formed as a black mask on the display substrate.

The display device according to the present invention has a basic configuration in which a display substrate having pixels arranged in a matrix, a transparent counter substrate joined to the display substrate through a predetermined gap, and Electro-optical material. The display substrate, a pixel electrode arranged for each pixel,
Similarly, an element used for driving a corresponding pixel electrode arranged for each pixel, a wiring pattern made of a relatively high-resistance semiconductor film arranged for electrical connection of each element, and a light-shielding area around each pixel electrode And a light-shielding pattern formed of a metal film having a relatively low resistance. A contact portion for electrically connecting the light-shielding pattern to the wiring pattern;
The resistance of the wiring pattern is effectively reduced.

As a feature of the present invention, the light-shielding pattern is formed continuously between different pixels, while the wiring pattern is divided and formed discontinuously for each pixel.
As another feature, the display substrate has a light-shielding pattern parallel to a row of pixels arranged in a matrix and a metal pattern (signal wiring pattern) formed parallel to a column of pixels and supplying signal charges to each element. Contains. The light-shielding pattern and the metal pattern intersect each other to surround the individual pixel electrodes in a grid pattern and form a black mask (black matrix). Specifically, the element supplies signal charges to the pixel electrodes
Transistor element and auxiliary holding of the signal charge
A capacitive element. Correspondingly, the wiring path
Button is the gate connected to the gate electrode of each transistor element.
Wiring pattern and auxiliary wiring pattern connected to each capacitance element
And In this case, the contact portion is the gate wiring
Either the pattern or the auxiliary wiring pattern is
Electrical connection. Electrically connect to the auxiliary wiring pattern
In such a case, the light-shielding pattern is predetermined over the entire display screen.
Are held at the common potential. In addition, each pixel row corresponds to
When electrically connecting to the gate wiring pattern
The light-shielding pattern is the same for each row of pixels arranged in a matrix.
Is divided into

[0008]

In the display substrate, a wiring pattern made of a semiconductor film having a relatively high resistance is arranged for electrical connection of a transistor element or a capacitor element. This semiconductor film is made of the same material as the gate electrode of the thin film transistor and the electrode of the thin film capacitor. Further, a light-shielding pattern made of a metal film having a relatively low resistance is formed, and is arranged as a black matrix around each pixel electrode. According to the present invention, a contact portion is provided in an interlayer insulating film interposed between a wiring pattern and a light-shielding pattern, and both are electrically connected. Accordingly, the wiring structure has a substantially two-layer structure of a wiring pattern and a light-shielding pattern, and most of the current flows through the metal film, which can greatly contribute to a reduction in wiring resistance. Since the wiring pattern itself can be composed of a semiconductor film without using any metal film, it is possible to obtain high consistency with the formation of a thin film element in the process and to increase reliability.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a first view of a display device according to the present invention.
It is a typical partial sectional view showing an example. The display device has a panel structure including a display substrate 1 and a counter substrate 2 joined to each other with a predetermined gap therebetween, and an electro-optical material such as a liquid crystal 3 held in the gap. A transparent opposing electrode 4 is provided on the inner surface of the opposing substrate 2 made of transparent glass or the like.
Are formed over the entire surface. On the other hand, the display substrate 1 has pixels 5 arranged in a matrix.

[0010] On the display substrate 1, pixel electrodes 6 arranged for each pixel 5 are formed. Similarly, a thin film element arranged for each pixel 5 and used for driving the corresponding pixel electrode 6 is also formed. The thin film element includes a transistor element Tr for supplying signal charges to the pixel electrode 6 and a capacitor element Cs for holding the signal charges in an auxiliary manner. Each of the transistor element Tr and the capacitance element Cs has a thin film structure, and the common semiconductor thin film 7
Is an element region. A metal pattern (signal wiring pattern) 8 is connected to the source region S of the transistor element Tr. The pixel electrode 6 is connected to the drain region D of the transistor element Tr via the electrode pad 9. further,
A wiring pattern made of a semiconductor film having a relatively high resistance is formed for electrical connection of the individual elements. In this example,
These wiring patterns are a gate wiring pattern 10 connected to the gate electrode of the transistor element Tr and an auxiliary wiring pattern 11 connected to the capacitance element Cs. In the drawing, the gate electrode portion of the gate wiring pattern 10 and the auxiliary wiring pattern 1
One capacitor electrode portion is shown as a cross section. The gate electrode and the capacitor electrode are patterned on the semiconductor thin film 7 via the gate insulating film 12. Further, a light-shielding pattern 13 is formed around each pixel electrode 6 as a part of a black matrix. This shading pattern 1
3 is made of a metal film having a relatively low resistance. A contact part CON is provided as a feature of the present invention, and a light-shielding pattern is electrically connected to the wiring pattern to effectively reduce the resistance of the wiring pattern. In this embodiment, the light-shielding pattern 13 is applied to the gate wiring pattern 10 via the contact portion CON formed through the first interlayer insulating film 14 and the second interlayer insulating film 15.
Is electrically connected to Instead of this, the light shielding pattern 1
3 may be connected to the auxiliary wiring pattern 11 side. As can be understood from the figure, the gate wiring pattern 10 and the light shielding pattern 13 have a substantially two-layer wiring structure, and most of the current flows through the light shielding pattern 13, so that the resistance of the entire wiring can be reduced. The light-shielding pattern 13 is covered with a flattening film 16, and the above-described pixel electrode 6 is formed on the light-shielding pattern 13 by patterning.

With reference to FIG. 1, a method of manufacturing the present display device will be described in detail. On a display substrate 1 made of glass, quartz, or the like, a semiconductor thin film 7 made of polycrystalline silicon or amorphous silicon is formed with a thickness of 50 nm by a low pressure CVD method. The semiconductor thin film 7 is patterned in an island shape. The semiconductor thin film 7 serves as an active layer of the thin film transistor Tr and constitutes a lower electrode of the capacitor Cs. A gate insulating film 12 is formed on the semiconductor thin film 7. The gate insulating film 12 partially becomes a dielectric layer of the capacitor Cs, and is made of, for example, an oxide. However, as the material of the gate insulating film 12, a nitride or the like is used in addition to the oxide. Alternatively, a stacked structure of an oxide and a nitride may be employed. Next, polycrystalline silicon or amorphous silicon is formed with a thickness of about 350 nm by a low pressure CVD method. The polycrystalline silicon or amorphous silicon is doped with impurities to reduce the resistance, and is patterned into a predetermined shape to form a gate wiring pattern 10 and an auxiliary wiring pattern 1.
It becomes 1. The gate wiring pattern 10 (including the gate electrode) and the auxiliary wiring pattern 11 are covered with a first interlayer insulating film 14. The first interlayer insulating film 14 is obtained, for example, by forming PSG to a thickness of about 600 nm by normal pressure CVD. In the first interlayer insulating film 14, a contact portion reaching the source region S and the drain region D of the transistor element Tr and a contact portion CON reaching the gate wiring pattern 10 are opened. As a material of the first interlayer insulating film 14, an oxide film, a nitride film, or the like by a normal pressure CVD method or a plasma CVD method can be generally used. Alternatively, it is also possible to use an insulating film formed by another forming method such as SOG, or an organic film such as polyimide or acrylic resin. Aluminum is deposited on the first interlayer insulating film 14 to a thickness of about 600 nm by a sputtering method. This aluminum is patterned into a predetermined shape to form a metal pattern 8 serving as a signal wiring and an electrode pad 9 for connection. The metal pattern 8 is connected to the source region S of the transistor element Tr via a contact portion, and the electrode pad 9 is similarly connected to the drain region D of the transistor element Tr via the contact portion.
Is electrically connected to As the material of the metal pattern 8 and the electrode pad 9, tantalum, molybdenum, chromium, nickel, or the like may be used instead of aluminum. The metal pattern 8 and the electrode pad 9 are covered with the second interlayer insulating film 15. This second interlayer insulating film 15 is 400
It is obtained by depositing PSG to a thickness of about nm. A contact portion reaching the electrode pad 9 and a contact portion CON reaching the gate wiring pattern 10 are opened in the second interlayer insulating film 15. Titanium is deposited on the second interlayer insulating film 15 to a thickness of about 250 nm by a sputtering method. This titanium is patterned into a predetermined shape, and a light shielding pattern 1 is formed.
It is processed into 3. This light-shielding pattern 13 has a contact portion C
It is electrically connected to the gate wiring pattern 10 via ON.
As the light-shielding pattern 13, a metal material having good light-shielding properties and good contact with a wiring pattern is selected. In addition to titanium, molybdenum, chromium, nickel, tungsten, tantalum, platinum, palladium, and the like can be used as the metal material. The metal light shielding pattern 13 is covered with the third interlayer insulating film 16. The third interlayer insulating film 16 is obtained by depositing PSG to a thickness of about 600 nm by, for example, a normal pressure CVD method. This third interlayer insulating film 1
6 is provided with a contact portion reaching the electrode pad 9. ITO is formed on the third interlayer insulating film 16 to a thickness of about 150 nm by a sputtering method. This I
The transparent pixel electrode 6 is obtained by patterning the TO into a predetermined shape. The display substrate 1 shaped as described above is bonded to the counter substrate 2 on which the counter electrode 4 is formed in advance with a predetermined gap. The liquid crystal 3 having a twisted nematic orientation is held in the gap, and an active matrix type display device is completed.

FIG. 2 is a schematic diagram showing a planar pattern shape of the display device shown in FIG. As shown in the drawing, the display substrate has a light shielding pattern 13 parallel to the rows of the pixels 5 arranged in a matrix and includes a metal pattern 8 formed parallel to the columns of the pixels 5. The light-shielding pattern 13 and the metal pattern 8 intersect each other to form a black mask (black matrix) that surrounds each pixel electrode in a grid pattern.
Further, a gate wiring pattern 10 and an auxiliary wiring pattern 11 are also formed along the row direction of the pixels 5. In this example, the metal light-shielding pattern 13 and the gate wiring pattern 10 are electrically connected to each other by the contact part CON. The metal light-shielding pattern 13 can be functionally regarded as a wiring pattern in the row direction, and the resistance of the gate wiring pattern 10 can be substantially reduced. The light shielding pattern 13 is divided for each row of the pixels 5 arranged in a matrix and has a floating potential. Each pixel 5 includes a liquid crystal cell LC. This liquid crystal cell LC is composed of liquid crystal 3 held between a pixel electrode 6 and a counter electrode 4. The transistor element Tr supplies the signal charge supplied from the metal pattern 8 to the pixel electrode 6. The capacitance element Cs additionally holds this signal charge. As described above, the metal light-shielding pattern 13 is divided for each row of the pixels 5 and has a floating potential. In other words, from the potential of the pixel electrode 6 (pixel potential), the potential of the metal pattern 8 (signal potential), the potential of the auxiliary wiring pattern 11 (common potential), and the potential (gate potential) of the gate wiring pattern 10 in another stage, Insulation is maintained.

FIG. 3 is an equivalent circuit diagram showing the overall configuration of the display device shown in FIGS. On the display substrate 1, a liquid crystal cell LC, a transistor element Tr,
The capacitance element Cs is formed. Further, a gate wiring pattern 10, an auxiliary wiring pattern 11, and a light shielding pattern 13 arranged in a row are also formed. In addition to these elements constituting the screen section, a vertical scanning circuit 21
A horizontal scanning circuit 22, an image signal supply switch 23, and the like are formed. The gate wiring pattern 10 includes a vertical scanning circuit 21
On the other hand, the metal pattern 8 is connected to the horizontal scanning circuit 22 via the image signal supply switch 23. The gate electrode of the transistor element Tr forms a part of the gate wiring pattern 10, the source electrode is connected to the corresponding metal pattern 8, and the drain electrode is connected to the liquid crystal cell LC.
One electrode of the auxiliary capacitor Cs arranged in parallel with the liquid crystal cell LC is connected to the auxiliary wiring pattern 11. This auxiliary wiring pattern 11 is held at a common potential. The vertical scanning circuit 21 sequentially supplies a gate signal to the gate wiring pattern 10 and controls opening and closing of the transistor elements Tr in a line-sequential manner. The horizontal scanning circuit 22 sequentially controls the opening and closing of the image signal supply switch 23 in synchronization with this, and supplies the image signal via the metal pattern 8. This image signal is written into the liquid crystal cell LC through the transistor element Tr selected in a line-sequential manner. The capacitance element Cs additionally holds the charge of the image signal. As described above, the gate wiring pattern 10 is
Is electrically connected to the light-shielding pattern 13 via the. The light-shielding pattern 13 is electrically insulated from the pixel potential, the signal potential, the common potential, and the gate potential at another stage. Gate wiring pattern 1 connected to each other by contact part CON
0 and the light shielding pattern 13 have an equivalent double wiring structure as shown, and the combined wiring resistance is significantly reduced.

FIG. 4 shows a modification of the pattern structure shown in FIG. The basic structure is the same, and corresponding parts are denoted by corresponding reference numerals to facilitate understanding. The difference is that the light-shielding pattern 13 is formed continuously between different pixels 5, whereas the gate wiring pattern 10 is divided and formed discontinuously for each pixel 5. Specifically, the gate wiring pattern 10 is removed from a portion that intersects the metal pattern 8 in the column direction.
Since the intersection between the gate wiring pattern 10 and the metal pattern 8 can be eliminated, it is possible to reduce the parasitic capacitance that adversely affects the image quality. It should be noted that the gate wiring pattern 10
Even if the gate wiring pattern is divided, the gate wiring pattern is electrically continuous for each row as a whole, since there is no problem in terms of function because it is individually connected to the metal light shielding pattern 13 via the contact part CON.

FIG. 5 is a schematic sectional view showing a second embodiment of the display device according to the present invention, and shows only the display substrate 1 side for simplification of the drawing. The basic configuration is the same as that of the first embodiment shown in FIG. 1, and the corresponding parts are denoted by the corresponding reference numerals to facilitate understanding. The difference is that the light-shielding pattern 13 is connected to the auxiliary wiring pattern 11 side instead of the gate wiring pattern 10 via the contact part CON. That is, in this embodiment, the metal light-shielding pattern 13 and the auxiliary wiring pattern 11 are joined to each other to obtain a two-layer wiring structure.

FIG. 6 is a schematic diagram showing the planar pattern shape of the second embodiment shown in FIG. As described above, the auxiliary wiring pattern 11 is formed in the contact portion CO opened for each pixel 5.
It is connected to the light shielding pattern 13 via N. In general,
The auxiliary wiring pattern 11 for commonly connecting one side electrode of the capacitive element Cs is connected to a predetermined common potential. Therefore, the light shielding pattern 13 also has this common potential. For this reason, since the metal light-shielding patterns 13 are all kept at the same potential in the display area, the light-shielding patterns 13 corresponding to each row need not be physically separated from each other, but are connected to each other over the display area. It does not matter.

FIG. 7 is an equivalent circuit diagram showing the entire configuration of the second embodiment shown in FIGS. Basically, Figure 3
Is similar to that of the first embodiment, and corresponding parts are denoted by corresponding reference numerals to facilitate understanding.
The difference is that the light shielding pattern 13 is not the gate wiring pattern 10 but the auxiliary wiring pattern 11 via the contact part CON.
It is connected to. The light-shielding pattern 13 is maintained at a common potential, while being electrically insulated from the pixel potential, signal potential, and gate potential. The interconnection between the metal light-shielding pattern 13 and the auxiliary wiring pattern 11 makes it possible to substantially reduce the resistance of the wiring.

FIG. 8 shows a modification of the second embodiment described with reference to FIGS. Basically Figure 6
And the corresponding parts are given the same reference numerals to facilitate understanding. In the example shown in FIG. 6, the auxiliary wiring pattern 11 is continuous along the row direction, whereas in the present example, the auxiliary wiring pattern 11 is divided for each pixel. In other words, an upper electrode of an independent capacitive element is provided for each pixel 5. This upper electrode (that is, the divided auxiliary wiring pattern 11) is connected to the metal light shielding pattern 13 via the contact part CON.
The metal light shielding pattern 13 is continuous over the entire display area, and is connected to a common potential outside the display area. Therefore, the upper electrode of each capacitance element Cs is connected to a common potential. As a result, the upper electrodes do not need to be connected to each other between the pixels along the row direction, the area occupied by the auxiliary wiring pattern 11 required for this can be reduced, and a pixel layout with a high aperture ratio is realized. It is possible. Furthermore, since the intersection between the auxiliary wiring pattern 11 and the metal pattern (signal wiring) 8 can be eliminated, the parasitic capacitance that adversely affects the image quality can be reduced.

[0019]

As described above, according to the present invention, the metal light-shielding pattern and the semiconductor wiring pattern are connected to each other to form a composite, and the effective resistance of the wiring can be reduced. Deterioration of image quality can be avoided. Since the substantial wiring resistance is reduced, the line width of the wiring pattern itself can be reduced, and a pixel layout with a high aperture ratio can be realized. In particular, when a metal light-shielding pattern is connected to an auxiliary wiring pattern of a capacitor, each pattern can be divided for each pixel, so that an independent layout can be performed for each pixel and a high aperture ratio can be realized. In addition, since the intersection between the auxiliary wiring pattern and the signal wiring metal pattern can be eliminated, it is possible to avoid deterioration in image quality due to capacitive coupling or the like.

[Brief description of the drawings]

FIG. 1 is a schematic partial sectional view showing a first embodiment of a display device according to the present invention.

FIG. 2 is a schematic plan view of the first embodiment.

FIG. 3 is an equivalent circuit diagram of the first embodiment.

FIG. 4 is a plan view showing a modification of the first embodiment.

FIG. 5 is a schematic partial sectional view showing a second embodiment of the display device according to the present invention.

FIG. 6 is a plan view of the second embodiment.

FIG. 7 is an equivalent circuit diagram of the second embodiment.

FIG. 8 is a plan view showing a modification of the second embodiment.

FIG. 9 is an equivalent circuit diagram illustrating an example of a conventional display device.

[Explanation of symbols]

 Reference Signs List 1 display substrate 2 counter substrate 3 liquid crystal 4 counter electrode 5 pixel 6 pixel electrode 7 semiconductor thin film 8 metal pattern 10 gate wiring pattern 11 auxiliary wiring pattern 13 light shielding pattern Tr transistor element Cs capacitance element LC liquid crystal cell CON contact part

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-257164 (JP, A) JP-A-63-208896 (JP, A) JP-A-5-249492 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G02F 1/1368 G02F 1/1343 G09F 9/30 H01L 29/786

Claims (4)

(57) [Claims] 1. A display device comprising: a display substrate having pixels arranged in a matrix; a transparent opposing substrate bonded to the display substrate via a predetermined gap; and an electro-optical material held in the gap. The display substrate includes a pixel electrode arranged for each pixel, an element arranged for each pixel and used for driving a corresponding pixel electrode, and a relatively resistive element arranged for electrical connection of each element. A wiring pattern made of a high semiconductor film, a light shielding pattern made of a metal film having a relatively low resistance arranged around the individual pixel electrodes for light shielding, and electrically connecting the light shielding pattern to the wiring pattern to form the wiring pattern. And a contact portion for effectively lowering the resistance of the pixel , wherein the light shielding pattern is formed continuously between different pixels.
On the other hand, the wiring pattern is divided for each pixel and disconnected.
A display device characterized by being formed continuously . 2. A table having pixels arranged in a matrix.
And a transparent substrate bonded to the display substrate via a predetermined gap.
Clear opposing substrate and the electro-optical material held in the gap.
A display device, wherein the display substrate is used for driving a pixel electrode disposed for each pixel and a corresponding pixel electrode disposed for each pixel.
Elements and relatively high resistance semi-conductors arranged for electrical connection of individual elements
A wiring pattern consisting of a body film and a relatively
A light-shielding pattern made of a metal film having a low thickness, and electrically connecting the light- shielding pattern to the wiring pattern to form the wiring pattern.
A contact portion for effectively lowering the resistance of the button, and the display substrate is arranged in a row of pixels arranged in a matrix.
It has a row light-shielding pattern and is formed parallel to the pixel columns.
And a metal pattern for supplying a signal charge to each element.
The light-shielding pattern and the metal pattern cross each other.
Configure a black mask surrounding each pixel electrode in a grid
A display device characterized in that: 3. The element supplies a signal charge to a pixel electrode.
Transistor element and a capacity for auxiliary holding the signal charge.
The wiring pattern is in contact with the gate electrode of each transistor element.
Connected gate wiring pattern and auxiliary to connect to each capacitance element
A wiring pattern, wherein the contact portion includes the gate wiring pattern and the auxiliary wiring pattern.
One of the buttons is electrically connected to the light-shielding pattern , and the light-shielding pattern has a predetermined common potential over the entire display substrate.
And the supplement through the contact portion.
It is characterized by being electrically connected to the auxiliary wiring pattern
The display device according to claim 2. 4. The element supplies a signal charge to a pixel electrode.
Transistor element and a capacity for auxiliary holding the signal charge.
The wiring pattern is in contact with the gate electrode of each transistor element.
Connected gate wiring pattern and auxiliary to connect to each capacitance element
A wiring pattern, wherein the contact portion includes the gate wiring pattern and the auxiliary wiring pattern.
One of the buttons is electrically connected to the light-shielding pattern , and the light-shielding pattern is provided for each row of pixels arranged in a matrix.
Of the pixel through the contact portion.
Each row is electrically connected to the corresponding gate wiring pattern
The display device according to claim 2, wherein: