JP3285420B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device capable of internally forming a constant voltage power supply capable of extracting a lower constant output voltage from a fluctuating input voltage.

[0002]

2. Description of the Related Art FIG. 7 is a cross-sectional view showing an example of a conventional semiconductor device capable of internally forming a constant voltage power supply capable of extracting a constant output voltage lower than a fluctuating input voltage. In the figure, 1 is an n-type (second conductivity type) or p-type (first conductivity type) semiconductor substrate, 2 is an insulating film formed on a main surface of the semiconductor substrate 1, and 3 is a main surface of the insulating film 2 The n ⁻ -type semiconductor layers 4 and 5 formed thereon are p-type diffusion regions formed on the main surface of the n ⁻ -type semiconductor layer 3, respectively, and 6 is n ⁻
N ⁺ -type diffusion region formed on the main surface of
Is a p ⁻ -type diffusion region formed on the main surface of n ⁻ -type semiconductor layer 3 between p-type diffusion regions 4 and 5 in contact with diffusion regions 4 and 5, and 8 is formed in p ⁻ -type diffusion region 7 An n ⁺ -type diffusion region 9 is a reference electrode serving as a first electrode formed in contact with the p-type diffusion regions 4 and 5, respectively. A reference numeral 10 is formed in contact with the n ⁺ -type diffusion region 6, and an input that varies from outside. An input electrode as a second electrode to which a voltage is applied, 11 is a back electrode formed in contact with the semiconductor substrate 1, 12 is formed in contact with the n ⁺ diffusion region 8, and outputs a constant voltage to the outside. An output electrode as the third electrode.

Next, the operation will be described with reference to FIGS. 8 and 9. First, the potential of the output electrode 12 is set to a floating state, and the reference electrode 9 and the back surface electrode 11 are connected in common to have the same potential (0 V). When the input voltage applied to the input electrode 10 is increased, the depletion layer approaches the n ⁺ -type diffusion region 8 as shown by a broken line in the figure. The end of the depletion layer in this state is indicated by symbol A. Further, the input electrode 10
Is increased, the n ⁺ type diffusion region 8 enters a floating state in the depletion layer. During this time, the voltage obtained at the output electrode 12 rises in parallel with the input voltage applied to the input electrode 10. The end of the depletion layer in this state is indicated by reference numeral B.

Further, when the input voltage applied to the input electrode 10 is increased and the p ⁻ -type diffusion region 7 is completely depleted, the gap between the p-type diffusion regions 4 and 5 and the n ⁺ -type diffusion region 8 is reduced. Of the voltage obtained at the output electrode 12 by substantially preventing the space charge of the output electrode 12 from changing, and substantially functioning as a JFET (junction field effect transistor) between the p-type diffusion region 5 and the semiconductor substrate 1. The potential no longer changes. The end of the depletion layer in this state is indicated by reference symbol C.

[0005] In the state of symbol C, as shown in FIG. 9, the output electrode 12 and the reference electrode 9 are connected by a resistor 13, and the voltage obtained at the output electrode 12 is a diode (the diffusion regions 7 and 8). When lowered forward voltage drop of about Vf of the PN junction), electrons e ^- are n ⁺ -type diffusion region 8 flows punch-through toward the n ⁺ -type diffusion region 6, a current corresponding to the resistance from the output electrode 12 It flows to the reference electrode 9 side via the vessel 13. Since the punch-through current generally has a low resistance component of the diode, the resistor 13 generates a voltage sufficient to maintain the voltage obtained at the output electrode 12 from the floating state by about the forward drop voltage Vf of the diode. . In other words, the output electrode 12 is a constant voltage power supply having a large current driving capability that can constantly obtain a constant voltage even when the load resistance is substantially reduced.

[0006]

Since the conventional semiconductor device is constructed as described above, there has been a problem that the output voltage obtained at the output electrode 12 tends to fluctuate due to variations in the manufacturing process. That is, in the case of the conventional device, the output voltage obtained at the output electrode 12 greatly depends on the impurity concentration of the p ⁻ -type diffusion region 7 and the distance between the p-type diffusion regions 4 and 5 and the n ⁺ -type diffusion region 8. and, these p ^- easily step on variation values manufacture distance between the impurity concentration and the p-type diffusion regions 4 and 5 and the n ⁺ -type diffusion region 8 type diffusion region 7, which is, p ^- -type diffusion region n impurity concentration of 7 is adjacent ^- n to similarly low -type semiconductor layer 3 ^- -type semiconductor layer having an impurity concentration of 3 variation or p ^- type diffusion region 7 variations in injection amount of an impurity in forming itself like , The impurity concentration of the p ⁻ -type diffusion region 7 varies, and the distance between the p ⁻ -type diffusion regions 4 and 5 and the n ⁺ -type diffusion region 8, that is, the exposure of the p ⁻ -type diffusion region 7 The range of the surface varies, and as a result, the output voltage obtained at the output electrode 12 tends to fluctuate. There was a problem.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device which can function as a constant-voltage power supply whose output voltage hardly fluctuates due to variations in a manufacturing process. .

[0008]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on a main surface of the semiconductor substrate; A first conductivity type first semiconductor region formed on the main surface of the semiconductor layer and a first conductivity type second semiconductor region formed on the main surface of the semiconductor layer so as not to contact the first semiconductor region. And a third of the first conductivity type formed on the main surface of the semiconductor layer so as to be in contact with the second semiconductor region.
A fourth semiconductor region of a second conductivity type formed on the main surface of the semiconductor layer on the opposite side to the first semiconductor region so as not to contact the second semiconductor region; 5 of the second conductivity type formed inside the second semiconductor region.
And a first electrode formed in contact with the first semiconductor region, a second electrode formed in contact with the fourth semiconductor region, and a second electrode formed in contact with the fifth semiconductor region. And a third electrode formed.

According to a second aspect of the present invention, there is provided a semiconductor device, a conductive substrate, a dielectric layer formed on a main surface of the conductive substrate, and a dielectric layer formed on a main surface of the dielectric layer. A second conductive type semiconductor layer, a first conductive type first semiconductor region formed on a main surface of the semiconductor layer, and a main surface of the semiconductor layer so as not to be in contact with the first semiconductor region. A second semiconductor region of the first conductivity type formed, a third semiconductor region of the first conductivity type formed on the main surface of the semiconductor layer so as to be in contact with the second semiconductor region, and the semiconductor layer A fourth semiconductor region of a second conductivity type formed on the main surface of the second semiconductor region on the opposite side to the first semiconductor region so as not to contact the second semiconductor region, and formed inside the second semiconductor region. In contact with the formed fifth semiconductor region of the second conductivity type and the first semiconductor region. A first electrode made, and a second electrode formed in contact with the fourth semiconductor region, the fifth
And a third electrode formed in contact with the semiconductor region.

According to a third aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on a main surface of the semiconductor substrate; A first conductive type first semiconductor region formed on the main surface; and a first conductive type second semiconductor region formed on the main surface of the semiconductor layer so as not to contact the first semiconductor region. A third semiconductor region of the first conductivity type formed on the main surface of the semiconductor layer so as to be in contact with the second semiconductor region, and a third semiconductor region of the main surface of the semiconductor layer not being in contact with the second semiconductor region. A fourth semiconductor region of the second conductivity type formed on the side opposite to the first semiconductor region, a fifth semiconductor region of the second conductivity type formed inside the second semiconductor region, A first electrode formed in contact with the first semiconductor region; A second electrode formed in contact with the conductor region, in which a third electrode formed in contact with said third semiconductor region and the fifth semiconductor regions.

[0011]

According to the first aspect of the present invention, when the semiconductor substrate and the first electrode are set to the same potential and a reverse bias voltage is applied to the second electrode with respect to the first electrode, the voltage of the second electrode is increased. When a certain potential is reached, the voltage of the third electrode is fixed to a certain potential by the JFET between the semiconductor substrate and the third semiconductor region, and when the voltage of the third electrode is lowered from this fixed potential, The depletion layer punches through between the semiconductor layer and the fifth semiconductor region, and a current flows between the third electrode and the second electrode.

In the invention described in claim 2, the conductive substrate and the first electrode are set to the same potential, and when a reverse bias voltage is applied to the second electrode with respect to the first electrode, the second electrode is set to the second potential. When the voltage of the electrode reaches a certain potential, the voltage of the third electrode is fixed to a certain potential by the JFET between the conductive substrate and the third semiconductor region, and the voltage of the third electrode is reduced from the fixed potential. When lowered, the depletion layer punches through between the semiconductor layer and the fifth semiconductor region, and a current flows between the third electrode and the second electrode.

According to the third aspect of the present invention, the semiconductor substrate and the first electrode are set to the same potential, and the second electrode is connected to the first electrode.
When the voltage of the second electrode reaches a certain potential when a reverse bias voltage is applied to the electrode of the third electrode, the voltage of the third electrode is fixed to a certain potential by the JFET between the semiconductor substrate and the third semiconductor region, When the voltage of the third electrode is lowered from the fixed potential, the depletion layer punches through between the semiconductor layer and the fifth semiconductor region, and a current flows between the third electrode and the second electrode. .

[0014]

【Example】

Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention.
Parts corresponding to those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the figure, 1A is a p ^- type semiconductor substrate, 7
A is a second semiconductor formed in contact with the p-type diffusion region 5 in the n ⁻ -type semiconductor layer 3 between the p-type diffusion region 4 as the first semiconductor region and the p-type diffusion region 5 as the third semiconductor region. Is ap ⁻ type diffusion region as a semiconductor region. In the present embodiment, the reference electrode 9 is connected to only the p-type diffusion region 4. Other configurations are the same as those in FIG.

Next, the operation will be described with reference to FIGS. First, the potential of the output electrode 12 is set to a floating state, and the reference electrode 9 and the back surface electrode 11 are connected in common to have the same potential (0 V). When the input voltage applied to the input electrode 10 is increased, the depletion layer extends from the p ⁻ type semiconductor substrate 1A and the p type diffusion region 4 as shown by a broken line in the figure. Further, when the input voltage applied to the input electrode 10 is increased, the p-type diffusion region 5 and the p ⁻ -type diffusion region 7 are increased.
The space between A and the p ⁻ type semiconductor substrate 1A is completely depleted, and the p type diffusion region 5 and the n ⁺ type diffusion region 8 as the fifth semiconductor region enter a floating state. The end of the depletion layer in this state is indicated by symbol A.

Here, even if the input voltage applied to input electrode 10 is further increased, JFET comprising p-type diffusion region 5, n ^- type semiconductor layer 3 and p ^- type semiconductor substrate 1A is formed.
Are pinched off, so that even if the input voltage applied to the input electrode 10 is further increased, the right side of the p-type diffusion region 5 in the drawing is only depleted and the region on the left side of the p-type diffusion region 5 in the drawing is merely depleted. The electric field of the depletion layer does not change. Therefore, the depletion layer punches through the p ⁻ -type diffusion region 7A, and the output electrode 1
No electrons flow from 2 to the input electrode 10.

In this state, when the resistor 13 is inserted between the output electrode 12 and the reference electrode 9, the voltage obtained at the output electrode 12 tends to decrease, and at the same time, the depletion layer punches through the p ^- type diffusion region 7A, As shown in FIG. 3, the electron e ⁻ is transferred from the n ⁺ type diffusion region 8 to n as the fourth semiconductor region.
Flow toward the ⁺ type diffusion region 6, that is, the output electrode 12
, An electron e ⁻ flows to the input electrode 10, and a current corresponding thereto flows from the output electrode 12 to the reference electrode 9 via the resistor 13.

Since the punch-through current generally has a low resistance component of a diode (a PN junction of the diffusion regions 7A and 8), the voltage obtained at the output electrode 12 is applied to the resistor 13 from the floating state by the voltage required for punch-through. A voltage is generated enough to keep the voltage down. In other words, the output electrode 12 is a constant voltage power supply having a large current driving capability that can constantly obtain a constant voltage even when the load resistance is substantially reduced.

Here, the pinch-off voltage of the JFET is determined by the diffusion depth of the p-type diffusion region 5, the specific resistance and thickness of the n ⁻ type semiconductor layer 3, and the specific resistance of the p ⁻ type semiconductor substrate 1A. The voltage required for the depletion layer to punch through p ⁻ -type diffusion region 7A is substantially determined by the implantation amount and diffusion depth of diffusion regions 7A and 8, and can be made sufficiently small with respect to the pinch-off voltage. The voltage required to pass through is substantially negligible, and as a result, the output voltage of the output electrode 12 is substantially substantially equal to the JF.
It is determined only by the pinch-off voltage of ET. Since the impurity concentration of the p-type diffusion region 5 is higher than the impurity concentration of the adjacent n ⁻ -type semiconductor layer 3, the impurity concentration is less susceptible to variations in the impurity concentration or variations in the implantation amount or the like in the manufacturing stage. Further, the resistivity and thickness of the n ⁻ type semiconductor layer 3 or p ⁻
The specific resistance of the mold semiconductor substrate 1A is originally hardly affected by variations in the manufacturing process, and does not affect the fluctuation of the output voltage.

As described above, in this embodiment, the output electrode 12
Is substantially equal to the JFET composed of the p-type diffusion region 5, the n ⁻ type semiconductor layer 3 and the p ⁻ type semiconductor substrate 14.
And a constant voltage power supply that always outputs a constant output voltage without being affected by variations in the manufacturing process.

Embodiment 2 FIG. FIG. 4 is a cross-sectional view showing another embodiment of the present invention, in which parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, p used in FIG 1 ^- type in place of the semiconductor substrate 1A with n-type or which can be either a semiconductor substrate 1 of p-type as used in FIG. 7, the semiconductor substrate 1 and the n ^- -type semiconductor A dielectric layer 2A made of an insulating film such as a silicon oxide film or a silicon nitride film is provided between the layer 3 and the insulating layer. The semiconductor substrate 1 and the back electrode 11 constitute a conductor substrate. Other configurations are the same as those in FIG.

Next, the operation will be described with reference to FIG. First, the potential of the output electrode 12 is set to a floating state, and the reference electrode 9 and the back surface electrode 11 are connected in common to have the same potential (0 V). When the input voltage applied to the input electrode 10 is increased, a depletion layer extends from the p-type diffusion region 4 as shown by a broken line in FIG. ^The depletion layer extends toward the ⁻ type semiconductor layer 3.

Further, when the potential of the input voltage applied to the input electrode 10 is increased, the space between the p-type diffusion region 5, the p ⁻ -type diffusion region 7A and the dielectric layer 2A is completely depleted, and the p-type diffusion Region 5 and n ⁺ type diffusion region 8 are in a floating state. In this case, the pinch-off of the JFET including the p-type diffusion region 5, the n ⁻ type semiconductor layer 3, the dielectric layer 2A, and the semiconductor substrate 1 is caused by a depletion layer extending from the dielectric layer 2A reaching the p-type diffusion region 5. Occur.

The other operations are the same as those of the first embodiment, and the description thereof will be omitted. Here, even if the input voltage applied to the input electrode 10 is further increased, the above-mentioned JFE
Since T is pinched off, even if the input voltage applied to the input electrode 10 is further increased, the right side of the p-type diffusion region 5 on the drawing is only depleted, and the left side of the p-type diffusion region 5 on the drawing is only depleted. The electric field of the depletion layer in the region does not change.

Therefore, no electrons flow from the output electrode 12 to the input electrode 10 due to the depletion layer punching through the p ⁻ type diffusion region 7A. In this state, the output electrode 12
When the resistor 13 is inserted between the output electrode 1 and the reference electrode 9.
2, the depletion layer punches through the p ⁻ -type diffusion region 7A, and as shown in FIG. 3, electrons e ⁻ flow from the output electrode 12 to the input electrode 10,
A current corresponding to this flows from the output electrode 12 through the resistor 13 to the reference electrode 9 side.

Since the punch-through current generally has a low resistance component of a diode (a PN junction of the diffusion regions 7A and 8), the resistor 13 needs the potential of the voltage obtained at the output electrode 12 for the punch-through from the floating state. voltage of only keeps the voltage of <br/> lowered condition occurs. In other words, the output electrode 12 is a constant voltage power supply having a large current driving capability that can constantly obtain a constant voltage even when the load resistance is substantially reduced.

Here, the pinch-off voltage of the JFET is determined by the diffusion depth of the p-type diffusion region 5, the specific resistance and thickness of the n ^- semiconductor layer 3, and the specific resistance of the semiconductor substrate 1, while the depletion layer is The voltage required to punch through the p ^- type diffusion region 7A is substantially determined by the implantation amount and diffusion depth of the diffusion regions 7A and 8, and can be made sufficiently small with respect to the pinch-off voltage. The required voltage can be substantially neglected, and as a result, the output voltage of the output electrode 12 is determined substantially substantially only by the pinch-off voltage of the JFET.

Since the impurity concentration of the p-type diffusion region 5 is higher than the impurity concentration of the adjacent n ^- semiconductor layer 3, it is less susceptible to the variation in the impurity concentration or the variation in the implantation amount in the manufacturing stage. Also, the n ⁻ type semiconductor layer 3
The resistivity and the thickness of the semiconductor substrate 1 or the resistivity of the semiconductor substrate 1 are originally hardly affected by the variation in the manufacturing process, and do not affect the variation of the output voltage.

As described above, in this embodiment, the output electrode 12
Is substantially equal to the JFE composed of p-type diffusion region 5, n ⁻ -type semiconductor layer 3, dielectric layer 2A and semiconductor substrate 1.
A constant voltage power supply which is determined only by the pinch-off voltage of T and always outputs a constant output voltage without being affected by variations in the manufacturing process can be obtained.

Embodiment 3 FIG. FIG. 6 is a cross-sectional view showing still another embodiment of the present invention, in which parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment,
N instead of the output electrode 12 used in FIG. 1 ⁺ -type diffusion region 8
And an output electrode 12A formed to be in contact with both the p-type diffusion region 5 and the p-type diffusion region 5. Other configurations are the same as those in FIG.

The operation is the same as in the first embodiment, and will not be described. However, in the first embodiment, the n ⁺ -type diffusion region 8, the p ^-- type diffusion region 7A and the n ^-- type semiconductor layer 3 constitute an npn transistor, and the base of this transistor, that is, the p ^-- type diffusion region 7A is in a floating state. , A sudden change in the voltage of the n ⁺ -type diffusion region 6 connected to the input electrode 10 generates a forward-biased or reverse-biased voltage between the p-type diffusion region 5 and the n ⁺ -type diffusion region 8. However, there is a possibility that the output voltage of the output electrode 12 connected only to the n ⁺ type diffusion region 8 may be affected. In this embodiment, however, the output electrode 12A and the n ⁺ type diffusion region 8
Since it is connected to the n-type diffusion region 5 and is short-circuited between the n-type diffusion regions 5, the n ⁺ -type diffusion region 6 connected to the input electrode 10 has a sudden change in voltage. p
No forward-biased or reverse-biased voltage is generated between the n-type diffusion region 5 and the n ⁺ -type diffusion region 8, and there is no possibility that the output voltage of the output electrode 12 will be affected.

As described above, in this embodiment, a constant output voltage can be always obtained without being affected by variations in the manufacturing process, as in the above-described embodiment. A constant voltage power supply that always outputs a constant output voltage without being affected by such a change can be obtained.

[0033]

As described above, according to the present invention, the semiconductor substrate of the first conductivity type, the semiconductor layer of the second conductivity type formed on the main surface of the semiconductor substrate, A first semiconductor region of the first conductivity type formed on the main surface of the semiconductor layer; and a second semiconductor region of the first conductivity type formed on the main surface of the semiconductor layer so as not to contact the first semiconductor region. A semiconductor region, a third semiconductor region of a first conductivity type formed on the main surface of the semiconductor layer so as to be in contact with the second semiconductor region, and a second semiconductor region on the main surface of the semiconductor layer. A fourth semiconductor region of the second conductivity type formed on the side opposite to the first semiconductor region so as not to be in contact with the fifth semiconductor region of the second conductivity type formed inside the second semiconductor region; A region, a first electrode formed in contact with the first semiconductor region, and a fourth electrode. The second, which is formed in contact with the semiconductor region
And the third electrode formed in contact with the fifth semiconductor region, so that the output voltage of the third electrode, which is the output electrode, is substantially reduced to the third semiconductor region and the semiconductor layer. In addition, the output voltage is determined only by the pinch-off voltage of the JFET composed of the semiconductor substrate, and has an effect that a constant output voltage can always be obtained without being affected by variations in the manufacturing process.

According to the second aspect of the present invention, the conductive substrate, the dielectric layer formed on the main surface of the conductive substrate, and the second conductive layer formed on the main surface of the dielectric layer. A two-conductivity-type semiconductor layer, a first-conductivity-type first semiconductor region formed on the main surface of the semiconductor layer, and a main-surface of the semiconductor layer formed so as not to contact the first semiconductor region. A second semiconductor region of the first conductivity type, and a first semiconductor region formed on the main surface of the semiconductor layer so as to be in contact with the second semiconductor region.
A third semiconductor region of a conductivity type, and a fourth semiconductor of a second conductivity type formed on the main surface of the semiconductor layer on the opposite side to the first semiconductor region so as not to contact the second semiconductor region. Region and a second semiconductor region formed inside the second semiconductor region.
A fifth semiconductor region of conductivity type, a first electrode formed in contact with the first semiconductor region, a second electrode formed in contact with the fourth semiconductor region, And the third electrode formed in contact with the semiconductor region, so that the output voltage of the third electrode, which is the output electrode, substantially increases the third semiconductor region, the semiconductor layer, the dielectric layer, and the dielectric substrate. Is determined only by the pinch-off voltage of the JFET, which has an effect that a constant output voltage can always be obtained without being affected by variations in the manufacturing process.

According to the third aspect of the present invention, the first
A semiconductor substrate of a conductivity type, a semiconductor layer of a second conductivity type formed on a main surface of the semiconductor substrate, a first semiconductor region of a first conductivity type formed on a main surface of the semiconductor layer, A second semiconductor region of the first conductivity type formed on the main surface of the semiconductor layer so as not to contact the first semiconductor region; and a second semiconductor region formed on the main surface of the semiconductor layer so as to be in contact with the second semiconductor region. And a second conductive type third semiconductor region formed on the main surface of the semiconductor layer on the opposite side to the first semiconductor region so as not to contact the second semiconductor region. A fourth semiconductor region; a fifth semiconductor region of the second conductivity type formed inside the second semiconductor region; a first electrode formed in contact with the first semiconductor region; A second electrode formed in contact with the fourth semiconductor region and the third semiconductor region; And the third electrode formed in contact with the fifth semiconductor region, so that the output voltage of the third electrode, which is an output electrode, is substantially reduced to the third semiconductor region, the semiconductor layer, and the semiconductor substrate. Is determined only by the pinch-off voltage of the JFET consisting of a constant output voltage without being affected by the variation in the manufacturing process or the sudden change of the input voltage applied to the second electrode which is the input electrode. There is an effect that it can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view for explaining the operation of one embodiment of the semiconductor device according to the present invention;

FIG. 3 is a sectional view for explaining the operation of one embodiment of the semiconductor device according to the present invention;

FIG. 4 is a sectional view showing another embodiment of the semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view for explaining the operation of another embodiment of the semiconductor device according to the present invention;

FIG. 6 is a sectional view showing still another embodiment of the semiconductor device according to the present invention.

FIG. 7 is a sectional view showing a conventional semiconductor device.

FIG. 8 is a cross-sectional view for explaining the operation of a conventional semiconductor device.

FIG. 9 is a cross-sectional view for explaining the operation of a conventional semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 1A p ⁻ type semiconductor substrate 2A dielectric layer 3 n ⁻ type semiconductor layer 4, 5p type diffusion region 6, 8n ⁺ type diffusion region 7A p ⁻ type diffusion region 9 reference electrode 10 input electrode 11 back electrode 12 , 12A output electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/06 H01L 21/331 H01L 21/8232 H01L 27/095 H01L 29/73 H01L 29/80

Claims (3)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on a main surface of the semiconductor substrate, and a semiconductor layer of a first conductivity type formed on a main surface of the semiconductor layer. A first semiconductor region, a second semiconductor region of the first conductivity type formed on the main surface of the semiconductor layer so as not to contact the first semiconductor region, and a second semiconductor region on the main surface of the semiconductor layer. A third semiconductor region of the first conductivity type formed so as to be in contact with the semiconductor region; and a third surface formed on the main surface of the semiconductor layer on the side opposite to the first semiconductor region so as not to be in contact with the second semiconductor region. A fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the second conductivity type formed inside the second semiconductor region, and a second semiconductor region formed in contact with the first semiconductor region. A first electrode and a second electrode formed in contact with the fourth semiconductor region A semiconductor device characterized by comprising a third electrode formed in contact with the fifth semiconductor region. 2. A conductor substrate; a dielectric layer formed on a main surface of the conductor substrate; a second conductivity type semiconductor layer formed on a main surface of the dielectric layer; A first conductivity type first semiconductor region formed on the main surface of the layer; and a first conductivity type second semiconductor formed on the main surface of the semiconductor layer so as not to contact the first semiconductor region. A region, a third semiconductor region of the first conductivity type formed on the main surface of the semiconductor layer so as to be in contact with the second semiconductor region, and a region in contact with the second semiconductor region on the main surface of the semiconductor layer. A fourth semiconductor region of the second conductivity type formed on the opposite side to the first semiconductor region so as not to be disturbed; and a fifth semiconductor region of the second conductivity type formed inside the second semiconductor region. A first electrode formed in contact with the first semiconductor region; and a fourth semiconductor A semiconductor device comprising: a second electrode formed in contact with a body region; and a third electrode formed in contact with the fifth semiconductor region. 3. A semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on a main surface of the semiconductor substrate, and a semiconductor layer of a first conductivity type formed on a main surface of the semiconductor layer. A first semiconductor region, a second semiconductor region of the first conductivity type formed on the main surface of the semiconductor layer so as not to contact the first semiconductor region, and a second semiconductor region on the main surface of the semiconductor layer. A third semiconductor region of the first conductivity type formed so as to be in contact with the semiconductor region; and a third surface formed on the main surface of the semiconductor layer on the side opposite to the first semiconductor region so as not to be in contact with the second semiconductor region. A fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the second conductivity type formed inside the second semiconductor region, and a second semiconductor region formed in contact with the first semiconductor region. A first electrode and a second electrode formed in contact with the fourth semiconductor region A semiconductor device characterized by comprising a third electrode formed in contact with said third semiconductor region and the fifth semiconductor regions.