JP3251462B2 - MIS semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MIS (Metal-Insul
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MIS semiconductor device including a Si single crystal substrate, an insulating layer formed on the Si single crystal substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art An electronic device in which an insulating layer (dielectric film) is formed and integrated on a Si substrate, which is a semiconductor crystal substrate, has been devised. In semiconductors and dielectrics, LSIs with higher integration, dielectric isolation LSIs using SOI technology, nonvolatile memories, infrared sensors, optical modulators and optical switches, OEICs (opto-electronic integrated circuits: opto-electronici
ntegrated circuits) are being prototyped.

In semiconductor devices using these dielectric materials, it is necessary to use single crystals in order to ensure optimum device characteristics and reproducibility thereof. In the case of a polycrystal, it is difficult to obtain good device characteristics due to disturbance of physical quantities by grain boundaries. The same is true for a thin film material, and an epitaxial film of a functional material as close to a perfect single crystal as possible is desired. If epitaxial formation of dielectric and ferroelectric oxides can be realized on a Si substrate, the semiconductor properties of Si and the properties of dielectrics can be positively utilized. It is becoming.

The gate of a SiFET, which is the basis of a MIS capacitor for a DRAM, is usually formed of a polycrystalline or amorphous SiO ₂ film as an oxide film.
Make up the structure. As the integration advances, the size of the MOS capacitor is required to be smaller, and the current degree of integration has reached its limit. The dielectric constant of SiO ₂ is about 3, and in order to secure charge for operating the gate of the FET with a MOS capacitor, a dielectric having a larger dielectric constant is used in place of SiO ₂ and good MOS characteristics are obtained. I have to get. Since SiO ₂ is very compatible with Si, it has been used for Si devices in a polycrystalline or amorphous state. However, at present, other materials instead of SiO ₂ are not actually used in Si devices in a polycrystalline or amorphous state for the above-mentioned reason.

That is, a material having a large dielectric constant, a single crystal, and excellent MOS (MIS) characteristics is required in place of SiO ₂ .

In recent years, as oxides replacing SiO ₂ , A
ppl. Phys. 58 (6), 15 September
er 1985, page 2407, and App
l. Phys. 63 (2), 15 January 1
As reported on page 581 of 988,
ZrO ₂ has received attention. This report states that ZrO ₂ can be epitaxially grown on a Si single crystal substrate, but that the crystal is not a single orientation film but includes other crystal planes. Normally, bulk ZrO ₂ becomes cubic at 2500 ° C. or higher, tetragonal at 2500 ° C. to around 1000 ° C., and monoclinic at around 1000 ° C. to room temperature. Generally, a cubic crystal with high symmetry is easily obtained in an epitaxial thin film. This is because cubic crystals have more equivalent crystal planes than tetragonal crystals and monoclinic crystals. Since tetragonal and monoclinic materials have many crystal planes that are not equivalent to cubic materials, different crystal planes are likely to be mixed in addition to the orientation plane to be obtained. Therefore, Z
Since rO ₂ is also a monoclinic material at room temperature, no single-oriented epitaxial film has been obtained so far.

The above Appl. Phys. 58 (6), 1
5 September The first 2407 pages of 1985, at a deposition temperature of the ZrO ₂ is 800 ° C. or less, ZrO ₂ film is obtained monoclinic, 800 ° C. in the tetragonal ZrO ₂
It is stated that a film is obtained. In these ZrO ₂ films, (11) other than the (002) orientation plane of ZrO ₂
1), (11-1) or (200) was found to exist, and a single orientation film of ZrO ₂ was not obtained. There is no report that a single orientation film of ZrO ₂ has been obtained so far. In addition, reflection high-energy electron diffraction (Refle
ction High Energy Electron Diffraction-below, RH
Evaluation of the ZrO ₂ film crystal surface by EED) states that the RHEED image is a spot, and it is considered that large irregularities are present on the surface. Thus, a film having good crystallinity and surface properties of a ZrO ₂ epitaxial film has not been obtained so far.
Further, although a MIS capacitor using a ZrO ₂ film has not been manufactured and evaluated, a grain boundary is formed at an interface between different orientation planes when the orientation is not unidirectional as described above. When the property is poor, the interface with the electrode or semiconductor formed thereon is disturbed. Therefore, due to the disturbance of the physical quantity at the grain boundaries and the interface, the insulation property decreases,
Deterioration of interface characteristics occurs, and it is difficult to obtain good device characteristics.

On the other hand, the oxide material YSZ (ZrO ₂ has Y
Is reported to be capable of epitaxial growth on a Si single crystal. YSZ is ZrO ₂
As well as high chemical stability, wide band gap (about 5e
V), having a large dielectric constant (about 20),
It was considered a convenient material for the S capacitor. In addition, since YSZ is a cubic crystal, it is a great feature that a single-oriented epitaxial film is easily obtained.

A MIS structure is manufactured and evaluated by using this YSZ, and is described in Appl. Phys. Lett. 61 (2
6), No. 318 of 28 December 1992
Reported on page 4. In this report, MOS (MI
As the S) characteristic, the most basic CV characteristic was evaluated. However, a large hysteresis was observed in the CV characteristic, and a good MOS (MIS) characteristic was not obtained.

As described above, in YSZ in which a large hysteresis is observed in the CV characteristic, the MIS
Even when an FET is manufactured, the threshold voltage of the transistor greatly fluctuates due to the presence of CV hysteresis in the gate region of the FET, which is not practical.

[0011]

As described above,
The epitaxial YSZ film formed on the Si single crystal
Although it is very promising as a dielectric film for Si as a substitute for iO ₂ in terms of dielectric constant, hysteresis is observed in the most basic CV characteristic as a MOS (MIS) characteristic, and a good MOS (MIS) No characteristics were obtained, and it could not be used as a MIS capacitor for a Si device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a MIS semiconductor device exhibiting good MIS characteristics without showing hysteresis in CV characteristics and a method for manufacturing the same.

[0013]

This and other objects are achieved by the present invention which is defined below as (1) to (14). (1) In a MIS semiconductor device including a Si single crystal substrate and an insulating layer formed on the Si single crystal substrate, the insulating layer is made of Zr in terms of a constituent element excluding oxygen.
MIS semiconductor device characterized by being formed by a single oriented epitaxial film containing ZrO ₂ as a main component and containing 93 mol% or more of (2) (0) of the epitaxial film forming the insulating layer;
The MIS semiconductor device according to the above (1), wherein the half width of the rocking curve of the reflection on the (02) plane or the (111) plane is 1.5 ° or less. (3) The MIS semiconductor device according to (1) or (2), wherein at least 80% of the surface of the epitaxial film forming the insulating layer has a ten-point average roughness Rz of 2 nm or less at a reference length of 500 nm. . (4) As the Si single crystal substrate, the substrate surface is
The MIS semiconductor device according to any one of the above (1) to (3), which uses a Si surface-treated substrate having a 1 × 1 surface structure formed by Zr metal and oxygen. (5) The MIS semiconductor device according to any one of (1) to (4), wherein a Si single crystal is used as the single crystal substrate so that the (100) plane or the (111) plane is the substrate surface. (6) MIS in which a dielectric layer is constituted by the insulating layer
The MIS semiconductor device according to any one of the above (1) to (5), which is a capacitor. (7) The MIS semiconductor device according to any one of (1) to (6), wherein the gate oxide layer is a MISFET including the insulating layer. (8) In the method for manufacturing a MIS semiconductor device according to any one of the above (1) to (7),
i. heating the single crystal substrate, introducing an oxidizing gas into the vacuum chamber, and supplying Zr by evaporation to the surface of the single crystal substrate, and epitaxially growing a ZrO ₂ thin film on the substrate surface of the single crystal substrate. A method for manufacturing a MIS semiconductor device, comprising forming an insulating layer which is a single-oriented epitaxial film containing ZrO ₂ as a main component. (9) The MIS semiconductor device according to the above (8), wherein an oxidizing gas is jetted onto the surface of the single crystal substrate from the vicinity thereof to create an atmosphere having a higher partial pressure of the oxidizing gas than other portions only in the vicinity of the single crystal substrate. Production method. (10) The single crystal substrate has a substrate surface area of 10 cm ^2.
In addition to the above, by rotating in the plane of the substrate, Zr evaporate is supplied over the entire single crystal substrate in the oxidizing gas high partial pressure atmosphere, and substantially over the entire substrate surface of the single crystal substrate. (9) The method for manufacturing a MIS semiconductor device according to the above (8) or (9), wherein a uniform single-oriented epitaxial film is formed uniformly. (11) As the Si single crystal substrate, the substrate surface is Z
The method for manufacturing a MIS semiconductor device according to any one of the above (8) to (10), wherein a Si single crystal substrate pretreated so as to have a 1 × 1 surface structure formed by r and oxygen is used. (12) 0.2 to 1 on the surface of the Si single crystal substrate
After forming a silicon oxide layer having a thickness of 0 nm, the substrate temperature is set to 600 to 1200 ° C. in a vacuum chamber, and an oxidizing gas is introduced into the vacuum chamber to reduce the atmosphere at least in the vicinity of the substrate to 1 × 10 6. ^-4 to 1 × 10 ^-1 Torr, and in this state,
The method for manufacturing a MIS semiconductor device according to any one of the above (8) to (11), wherein Zr is supplied to the surface of the substrate on which the Si oxide layer is formed by evaporation to use a pretreated Si single crystal substrate. (13) When forming the Si oxide, the Si single crystal substrate is placed in a vacuum chamber into which an oxidizing gas has been introduced.
(12) The method for manufacturing a MIS semiconductor device according to the above (12), wherein the MIS semiconductor device is formed by heating to a temperature of at least 1 ° C. and setting the oxygen partial pressure of the atmosphere in the vacuum chamber at least near the substrate to 1 × 10 ⁻⁴ Torr or more. (14) As the Si single crystal substrate, a Si single crystal is
The M according to any of (8) to (13) above, wherein the (100) plane or the (111) plane is used as the substrate surface.
Manufacturing method of IS semiconductor device.

[0014]

The MIS semiconductor device of the present invention,
For example, MIS capacitors, MISFETs, and the like are most fundamentally formed by a structure including a Si single crystal substrate and a single orientation epitaxial film mainly composed of ZrO ₂ formed as a dielectric layer or the like on the Si single crystal substrate. Good CV characteristics without causing hysteresis.
IS characteristics can be obtained. It is considered that YSZ used in the conventional example contains a rare earth additive in ZrO ₂ , and has poor crystallinity and surface properties, so that hysteresis occurs in CV characteristics. In the present invention, high purity ZrO
_{Since 2} is formed with high crystallinity and high surface properties, almost no hysteresis occurs.

Furthermore, when the single crystal substrate is rotated in the plane, a uniform and high quality oxide thin film having a large area of 10 cm ² or more can be obtained. On the other hand, conventionally, when an oxide thin film is formed on a single crystal substrate, the maximum substrate area is about 2.25 cm ² (about 15 × 15 mm ² ).

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a MIS semiconductor device refers to a semiconductor device having a metal oxide insulating layer on a Si single crystal substrate. Examples of the MIS semiconductor device include a MIS capacitor and a MISFET.
Is mentioned.

As shown in FIG. 1, the MIS capacitor of the present invention comprises a Si single crystal substrate 11, a ZrO ₂ thin film formed as a dielectric layer 12 on the Si single crystal substrate 11, and a pair of electrodes. 13 and 14 are provided. That is, in the MIS capacitor, the metal oxide insulating layer is used as the dielectric layer.

As shown in FIG. 2, the MISFET of the present invention has a Si single crystal substrate 21 and a ZrO 2 formed as a gate oxide layer 22 on the Si single crystal substrate 21.
₂ thin film, source and drain 23, 24, gate electrode 25, source and drain electrodes 26, 27,
And an insulating layer 28. That is, in the MISFET, the metal oxide insulating layer is used as the gate oxide layer.

In the present invention, the MIS capacitor and the MI
The composition, crystal structure, and the like of the ZrO ₂ thin film used for the SFET are common.

The above-mentioned ZrO ₂ thin film is a single-oriented epitaxial film containing ZrO ₂ as a main component, and converts Zr to 93 mol% or more, particularly 95 mol% or more, more preferably 98 mol% or more, in terms of constituent elements excluding oxygen. It is preferably at least 99.5 mol%. The higher the purity, the smaller the hysteresis that appears in the CV characteristic curve. Also, Z
It was confirmed by experiments that the insulation resistance of rO ₂ was increased and the leak current was also reduced. When the leakage current increases,
When the MIS capacitor is applied to a semiconductor circuit, not only noise but also circuit operation becomes impossible. Also, MIS
The same applies to the case of FETs, especially when MISFETs are used in DRAMs, the storage retention characteristics deteriorate.

The upper limit of the Zr content is 99.99% at present. The oxide thin film may contain impurities such as rare earth metals and P at less than 7 mol%.

The crystal of the ZrO ₂ thin film has only a single orientation plane, and 80% or more, preferably 90% or more, particularly 95% or more of the surface has a ten-point average roughness at a reference length of 500 nm. It is desirable that Rz be 2 nm or less. When the substrate has only a single orientation plane and has good surface properties, the interface with an electrode or a semiconductor formed thereon is good. Therefore, since the interface characteristics can be improved, satisfactory insulation properties can be maintained and good device characteristics can be obtained. Note that the above percentage is a value obtained by measuring 10 or more arbitrary locations distributed on average over the entire surface of the ZrO ₂ thin film.

The thickness of the ZrO ₂ thin film is 0.5 to 50 nm,
Particularly, 1 to 30 nm is preferable. When the thickness of the ZrO ₂ thin film is 0.
If it is less than 5 nm, a leak tends to occur when a device is constructed. It is considered that this is because the possibility that pinholes occur in the film increases. If the film thickness is too large, the MIS capacity will decrease.

Reflection high-speed electron diffraction of ZrO ₂ thin film (Ref
lection High Energy Electr on Diffraction-
The RHEED image) has a high streak property. That is, the RHEED image is streak and sharp. As described above, the Zr of the present invention
The O ₂ thin film is a single crystal, and when used for a dielectric layer of a MIS capacitor, does not disturb the physical quantity due to grain boundaries, and exhibits a good function.

The MIS capacitor of the present invention and M
In the ISFET, the substrate surface of the Si single crystal substrate, that is, the thin film forming surface side is shallow (for example, about 5 nm or less).
It may be oxidized to form a layer such as SiO ₂ . This is because oxygen in the ZrO ₂ thin film may diffuse to the substrate surface of the Si single crystal substrate. Also, depending on the method of deposition, Si on Si substrate surface during ZrO ₂ thin film formation
An oxide layer may remain.

Next, the MIS capacitor of the present invention and M
Method for producing ISFET, particularly composition Z used for these
The MI is centered on the single oriented epitaxial film of rO _2.
A method for manufacturing a semiconductor device that is an S capacitor or a MISFET will be described in detail.

In carrying out the manufacturing method of the present invention, it is desirable to use a vapor deposition apparatus 1 as shown in FIG.

The vapor deposition apparatus 1 has a vacuum chamber 1a, in which a holder 3 for holding a single crystal substrate 2 is disposed. The holder 3 is connected to a motor 5 via a rotation shaft 4 and is rotated by the motor 5 so that the single crystal substrate 2 can be rotated in the substrate plane. In the holder 3,
A heater 6 for heating the single crystal substrate 2 is incorporated.

The vapor deposition apparatus 1 further includes an oxidizing gas supply device 7, and an oxidizing gas supply port 8 of the oxidizing gas supply device 7 is disposed immediately below the holder 3. Thus, the partial pressure of the oxidizing gas is increased near the single crystal substrate 2. Below the holder 3, a Zr evaporator 9 is disposed. This Zr
In the evaporating section 9, an energy supply device for supplying energy for evaporation to a metal source such as an electron beam generator is arranged in addition to the metal source. In the drawings, P is a vacuum pump.

In the method of manufacturing a MIS semiconductor device according to the present invention, first, a single crystal substrate is set on the holder. At this time, a single crystal semiconductor substrate of Si is used as a single crystal substrate, and a (100) plane or a (111) plane is selected as a substrate surface on which a target oxide thin film is formed. This is because the functional film formed on the substrate surface is made into a single crystal epitaxially grown, and the crystal is oriented in an appropriate direction. Preferably, the substrate surface is etched and cleaned using a mirror-finished wafer. The etching cleaning is performed with a 40% ammonium fluoride aqueous solution or the like.

The Si single crystal substrate used to manufacture the MIS capacitor of the present invention can have a substrate area of, for example, 10 cm ² or more. As a result, the MIS capacitor can be made extremely inexpensive as compared with the related art. There is no particular upper limit on the area of the substrate.
It is about 00 cm ² . As a result, a semiconductor process using a 2-inch to 8-inch Si wafer, in particular, a 6-inch type semiconductor process is mainly used, but it is possible to cope with this.

Since the cleaned Si single crystal substrate has extremely high reactivity, the substrate of the Si single crystal substrate is used for the purpose of protecting the substrate and growing a good epitaxial film containing ZrO ₂ as a main component. The surface is surface-treated as follows.

First, a Si single crystal substrate whose surface has been cleaned is placed in a vacuum chamber and heated while introducing an oxidizing gas to form a Si oxide layer on the surface of the Si single crystal substrate. Oxidizing gases include oxygen, ozone, atomic oxygen,
NO ₂ or the like can be used. Since the surface of the cleaned Si single crystal substrate is extremely reactive as described above, it is used as a protective film to protect the surface of the Si single crystal substrate from rearrangement and contamination. The thickness of the Si oxide layer is preferably about 0.2 to 10 nm.
If the thickness is less than 0.2 nm, the protection of the Si surface is incomplete. The reason for setting the upper limit to 10 nm will be described later.

The above heating is carried out at a temperature of 300 to 700 ° C. for about 0 to 10 minutes. At this time, the heating rate is about 30 to 70 ° C./min. If the temperature is too high,
If the rate of temperature rise is too fast, the formation of the Si oxide film will be insufficient, and conversely, if the temperature is too low or the holding time is too long,
The Si oxide film is too thick.

When oxidizing gas is introduced, for example, when oxygen is used as the oxidizing gas, the inside of the vacuum chamber is initially 1 × 10 ⁻⁷ to 1
It is preferable that the vacuum is set to about × 10 ⁻⁴ Torr, and the introduction of an oxidizing gas is performed so that at least the oxygen partial pressure of the atmosphere near the Si single crystal substrate becomes 1 × 10 ⁻⁴ .
The state in which the oxygen partial pressure of this atmosphere has an upper limit is a pure oxygen state, but it may be air, particularly preferably about 1 × 10 ⁻¹ Torr or less.

After the above steps, heating is performed in a vacuum. Since the Si surface crystal is protected by the protective film, there is no contamination such as formation of a SiC film by reacting with hydrocarbons as residual gas.

The heating temperature is 600 to 1200 ° C., especially 7
The temperature is preferably set to 00 to 1100 ° C. If the temperature is lower than 600 ° C., a 1 × 1 structure described later cannot be obtained on the surface of the Si single crystal substrate. If the temperature exceeds 1200 ° C., Si
The protection of the surface crystal is not sufficient, and the crystallinity of the Si single crystal substrate is disturbed.

Next, Zr and an oxidizing gas are supplied to the surface. In this process, the metal that is Zr replaces the Sr formed in the previous process.
The protective film made of the i-oxide is reduced and removed. At the same time, a 1 × 1 surface structure is formed on the exposed Si surface crystal surface by Zr and oxygen.

The surface structure was determined by reflection high-energy electron diffraction (Reflec
tion High Energy Electron Diffraction: RH
(Referred to as EED). For example, in the case of a 1 × 1 surface structure aimed at by the present invention, the electron beam incident direction is [110], and a complete streak pattern with a one-time period C1 as shown in FIG. Is exactly the same pattern when [1-10] is set. On the other hand, the Si single crystal clean surface is 1 × 2, 2 ×
1 or a surface structure in which 1 × 2 and 2 × 1 are mixed. In such a case, the pattern of the RHEED image is as shown in FIG. 15B in one or both of the electron beam incident directions [110] and [1-10].
The pattern has a one-time period C1 and a two-time period C2. In the 1 × 1 surface structure of the present invention, the incident directions are [110] and [1-1] in the RHEED pattern.
0], the double cycle C2 of FIG. 15B is not observed in both cases.

Also, the clean Si (100) surface may show a 1 × 1 structure. Although it has been observed several times in our experiments, it is impossible at present to obtain 1 × 1 on a Si-clean surface with an unclear, stable and reproducible condition showing 1 × 1.

S of any structure of 1 × 2, 2 × 1, 1 × 1
The i-clean surface is easily contaminated at high temperatures in a vacuum, and reacts particularly with hydrocarbons contained in the residual gas to form SiC on the surface, and the crystal on the substrate surface is disturbed. Therefore, it has not been possible to stably form a 1 × 1 structure suitable for crystal growth of an oxide film on a Si substrate.

The Si (100) plane has been described above as an example, but the (111) plane has a similar structure although the structure of the clean surface is different, and an oxide film is grown on a Si substrate. Until now, it has been impossible to stably form a suitable 1 × 1 structure.

The supply amount of Zr is 0.3 ZrO ₂ conversion.
It is preferably from 10 to 10 nm, particularly preferably from about 3 to 7. If it is less than 0.3 nm, the effect of reducing the Si oxide cannot be sufficiently exhibited, and
If the thickness exceeds nm, atomic level irregularities are likely to occur on the surface, and the crystal arrangement on the surface may not be a 1 × 1 structure due to the irregularities. The reason why the preferable upper limit of the thickness of the Si oxide layer is set to 10 nm is as follows.
If the thickness exceeds nm, there is a possibility that the Si oxide layer cannot be sufficiently reduced even if the metal is supplied as described above.

When oxygen is used as the oxidizing gas, 2
It is preferable to supply about 50 cc / min. The optimum amount of oxygen is determined by the size of the vacuum chamber, the pumping speed of the pump, and other factors, and the optimum flow rate is determined in advance.

The above-described Si substrate surface treatment has the following effects.

The surface structure in several atomic layers on the crystal surface is as follows:
This is generally different from a virtual surface atomic arrangement structure that can be considered when a bulk (three-dimensional large crystal) crystal structure is cut. This is because the disappearance of the crystal on one side changes the situation around the atoms that have appeared on the surface, and correspondingly tries to become a stable state with lower energy. The structural change mainly includes a case where the atomic position is merely relaxed and a case where the rearrangement of atoms occurs to form a rearranged structure. The former is present on most crystal surfaces. The latter generally form a superlattice structure on the surface. When the magnitudes of the unit vectors of the bulk surface structure are a and b, a superlattice structure having a magnitude of ma and nb is called an m × n structure. The surface of the cleaned Si (100) has a 1 × 2 or 2 × 1 structure, and the Si (111) surface has a complex superstructure having a large unit mesh of a 7 × 7 or 2 × 8 structure. In addition, these purified S
The i-surface is highly reactive, and reacts particularly with a residual gas in a vacuum, especially a hydrocarbon, at a temperature (700 ° C. or higher) at which an oxide thin film is epitaxially formed, and the Si surface is formed on the surface.
The formation of C contaminates the substrate surface and disturbs surface crystals.

To epitaxially grow an oxide on a Si substrate, the structure of the Si surface must be stable and play a role of transmitting crystal structure information to the grown oxide film. In the oxide epitaxial film crystal,
Since the atomic arrangement structure considered when cutting the bulk crystal structure is a 1 × 1 structure, the surface structure of the substrate for epitaxially growing an oxide is 1 × 2, 2 × 1, 7
Complex superstructures with large unit meshes of × 7 or 2 × 8 structures are not preferred and require a stable 1 × 1 structure. In addition, since the epitaxial growth is performed at a temperature of 700 ° C. or more, it is necessary to protect the reactive Si surface.

Next, as described above, S
A single orientation epitaxial film of ZrO ₂ is formed using an i single crystal substrate.

In forming a single-oriented epitaxial film containing ZrO ₂ as a main component, first, a Si single crystal substrate whose surface has been treated is heated. The heating temperature at the time of film formation is desirably 400 ° C. or higher for crystallization of ZrO ₂ ,
Furthermore, the crystallinity is excellent at about 750 ° C. or more, and particularly preferably 850 ° C. or more in order to obtain the crystal surface flatness at the molecular level film. Note that the upper limit of the heating temperature of the single crystal substrate is 1300
It is about ° C.

Next, Zr is heated by an electron beam or the like to evaporate. Zr metal and an oxidizing gas are supplied to the single crystal substrate to obtain a thin film containing ZrO ₂ as a main component. Here, the deposition rate is 0.05 to 1.00 nm / s, preferably 0.1 to 1.00 nm / s.
It is desirable to set it to 00 to 0.500 nm / s. The reason for this is that if it is too slow, the substrate will be oxidized, and if it is too early, the formed thin film will have poor crystallinity and cause irregularities on the surface. Therefore, the optimum value of the film formation rate is determined by the amount of oxygen introduced. For this reason, prior to the deposition of the ZrO ₂ thin film, the amount of evaporation per unit time and the formation of the Zr and ZrO ₂ deposited films are determined by the amount of power applied to the Zr metal deposition source near the substrate in the vacuum deposition tank. Measure and calibrate with the thickness gauge installed in As the oxidizing gas, oxygen, ozone, atomic oxygen, NO ₂ or the like can be used. Here, description will be made on the assumption that oxygen is used. Oxygen is continuously exhausted from the chamber by a vacuum pump, and a nozzle provided in the vacuum evaporation chamber is used to supply 2 to 50 cc / oxygen.
Min, preferably 5 to 25 cc / min of oxygen gas is continuously injected, and 10 ^-3 is supplied at least to the vicinity of the single crystal substrate in the vacuum chamber.
An oxygen atmosphere of about 10 ^-1 Torr is created. The optimal amount of oxygen is
An appropriate flow rate is determined in advance depending on the size of the chamber, the pumping speed of the pump, and other factors. Here, the upper limit of the oxygen gas pressure is set to 10 ^-1 Torr so that the metal source in the evaporation source in the vacuum chamber is not degraded and the evaporation rate is deposited at a constant rate. Further, when introducing oxygen gas into the vacuum deposition tank, it is preferable to inject oxygen gas from the vicinity of the surface of the single crystal substrate to create an atmosphere with a high oxygen partial pressure only in the vicinity of the single crystal substrate. The reaction on the substrate can be further promoted by the amount introduced. At this time, since the inside of the vacuum chamber is continuously evacuated, most of the vacuum chamber is 10 ^-4 to 10
^-6 The pressure is as low as ⁶ Torr.

[0051] In narrow region ² of about 1cm of the single-crystal substrate, it is possible to promote the oxidation reaction on the single crystal substrate in this manner, the substrate area of 10 cm ² or more, for example, a diameter of 2
Fig. 1
By rotating the substrate as described above and supplying a high oxygen partial pressure to the entire surface of the substrate, a large-area film can be formed. At this time, the rotation speed of the substrate is desirably 10 rpm or more. This is because if the number of rotations is low, a film thickness distribution occurs in the substrate surface. Although there is no particular upper limit on the number of rotations of the substrate, it is usually about 120 rpm due to the mechanism of the vacuum apparatus.

Although the details of the manufacturing method have been described above, this manufacturing method is particularly clear in comparison with the conventional vacuum evaporation method, sputtering method, and laser ablation method, and has no room for the presence of impurities and is controlled. Since it can be carried out under easy operation conditions, it is suitable for obtaining a target substance with high reproducibility and high completeness over a large area. In addition, the method
Even if a BE apparatus is used, a target thin film can be obtained in exactly the same manner.

The MIS capacitor material obtained as described above has electrodes formed thereon and is finely processed by a semiconductor process to obtain a large number of MIS capacitors. In the MIS capacitor of the present invention, since high-purity ZrO ₂ is formed with high crystallinity, almost no hysteresis is generated in the CV characteristic. The voltage width (hereinafter, referred to as a hysteresis value) is about 0.3 V or less. MIS (Metal-Insulator-Semiconduct
or) The apparent dielectric constant of the insulating layer (Insulator) having the structure can be increased to about 20. The MIS capacitor as described above can be formed as a MISFET for DRAM by forming a source and a drain by a semiconductor process using a single-oriented epitaxial film of the above composition ZrO ₂ as a gate oxide layer.
Compared to a conventional MIS capacitor using SiO ₂ for the insulating layer, the MIS capacitor of the present invention has a dielectric constant of 1 for the insulating layer.
Since it is 0 to 20, which is 5 to 10 times the conventional value, it is possible to further increase the integration density which is currently at the limit.

[0054]

EXAMPLES Hereinafter, the present invention will be described in more detail by showing specific examples of the present invention.

Embodiment 1 As Embodiment 1, the case of a MIS capacitor will be described below.

As a single crystal substrate for growing an oxide thin film, a Si single crystal cut and mirror-polished so that the surface becomes (100) plane, and a Si single crystal which is cut and mirror-polished so that the surface becomes (111) A single crystal wafer was used.
After the purchase, the mirror surface was cleaned by etching with a 40% ammonium fluoride aqueous solution. Note that a circular substrate having a diameter of 2 inches was used as the single crystal substrate.

The single crystal substrate was fixed to a substrate holder provided in a vacuum chamber and provided with a rotation and heating mechanism, and the vacuum evaporation chamber was evacuated to 10 ^-6 Torr by a pump. Then, in order to protect the cleaning surface of the substrate using Si oxide, 6
At 00 ° C., oxygen was introduced into the vicinity of the substrate from the nozzle at a rate of 25 cc / min, and an approximately 1 nm Si oxide film was formed on the surface of the substrate by thermal oxidation. Then, the vacuum evaporation tank was evacuated again to 10 ^-6 Torr, and the substrate was heated to 900 ° C. and rotated. The rotation speed was 20 rpm.

Thereafter, metal Zr was supplied from an evaporation source.
At the same time, the oxygen partial pressure of the atmosphere near the substrate is 10 ^−2.
Oxygen gas was introduced at a rate of 10 cc / min from the nozzle so that the pressure became Torr, and a metal Zr was placed on the (100) plane substrate.
Is evaporated from an evaporation source to supply 5 nm in terms of the thickness of a Zr metal oxide to provide a Si surface-treated substrate having a 1 × 1 surface structure, and b to deposit metal Zr on the (111) plane substrate. By evaporating from the evaporation source, 5 nm in terms of the thickness of the Zr metal oxide was supplied to obtain Si surface-treated substrates each having a 1 × 1 surface structure. Pattern images of these surfaces measured by RHEED are shown in FIGS.
Shown in

All of these were measured in the incident direction [110], and the patterns were exactly the same even when rotated by 90 °. That is, S having a stable 1 × 1 surface structure
It is confirmed that an i-surface treated substrate has been obtained.

Further, metal Zr is supplied from the evaporation source onto the Si surface-treated substrate while the substrate temperature is 900 ° C., the rotation speed is 20 rpm, and oxygen gas is introduced from the nozzle at a rate of 25 cc / min. A 10 nm thick ZrO ₂ film
Obtained on the substrates a and b.

X measured for the two types of obtained thin films
The results of the line diffraction pattern are shown in FIGS. In FIG. 6, the (002) peak of ZrO ₂ is observed. In FIG. 7, the (111) peak of ZrO ₂ completely overlaps the peak of the Si substrate. It can be seen that a crystal film strongly oriented in the direction reflecting the crystal structure and symmetry of ZrO ₂ was obtained. Particularly, these peaks are reflections from only one reflection surface, respectively, and it can be seen that the ZrO ₂ film is a single-orientation highly crystalline film which is not seen in the conventional example. Further, the half-widths of the rocking curve of this reflection were 0.7 ° (actual value) and 0.7 ° (actual value including the Si substrate), respectively, and it was also confirmed that the orientation was excellent.

FIGS. 8 and 9 show the RHE of this thin film.
ED (Reflection High Energy Electron Diffraction
) Shows the pattern. The incident direction of the electron beam is [1] on the Si substrate.
10] direction. As can be seen from the results, the diffraction pattern on the surface of the thin film having this structure is a completely streak pattern, which is completely different from the pattern in which the streak is partially close to a spot in the conventional example. This completely streak pattern is ZrO ₂
Is excellent in crystallinity and surface properties. FIG. 10 shows a surface image of the ZrO ₂ film formed on the processing substrate a, which was observed with an AFM. The surface state of the ZrO ₂ film on the b-treated substrate was almost the same. In addition, with respect to the above two types of films, JIS B0610 was applied to 10 places over almost the entire surface of each.
Was measured, the ZrO ₂ film on the Si (100) substrate had an average of 0.70 nm, a maximum of 0.95 nm, and a minimum of 0.1
0, on the average on a ZrO ₂ film on a Si (111) substrate.
It was flat at a molecular level of 80 nm, 1.00 nm at the maximum, and 0.08 at the minimum.

Further, the two types of Z were determined by X-ray fluorescence analysis.
When the composition of the rO ₂ thin film was measured, Zr, O ₂
Other impurities were not detected below the detection limit.

Next, the surface of the above-mentioned ZrO ₂ film having an area of about 0.
A Pt electrode film of 15 mm ² was formed and used as an upper electrode, and an MIS capacitor having an Si ohmic electrode provided with an ohmic electrode of Al was produced. The Si wafer is a 5Ωcm p-type wafer.

FIGS. 11 and 12 show CV characteristics of the MIS capacitor thus manufactured. The CV characteristic is 1MHz,
The measurement was performed while changing the bias voltage at 0.4 V / sec. As is clear from the CV characteristics shown in these figures, the samples using the present invention show no hysteresis in the CV characteristics. FIG. 13 shows CV characteristics of a MIS capacitor manufactured using a conventional YSZ thin film for comparison. In FIG. 13, when the bias voltage is changed, a large hysteresis width value of about 1.5 V or more is seen.

The leakage current is 2 when YSZ is used.
In contrast to ³ μA / cm ² , in this example, ² μA / cm ^2
2 and more than 10 times improved.

Embodiment 2 Next, a case of a MISFET will be described as Embodiment 2.

As shown in FIG. 14A, an Si single crystal wafer which was cut so that its surface became a (100) plane and mirror-polished was used as a single crystal substrate. This substrate is a p-type circular wafer having a resistivity of 10 Ωcm and a diameter of 2 inches. First, this substrate 101 is
As shown in FIG. 4B, the local oxidation method (hereinafter referred to as LOC)
(OS method). The thickness of the SiO ₂ oxide film 102 used for the LOCOS separation is 600 nm. Then, 40% for removing the natural oxide film on the substrate 101
Etching cleaning was performed with an ammonium fluoride aqueous solution.

The substrate 101 was fixed to a substrate holder provided with a rotation and heating mechanism installed in a vacuum chamber, and the vacuum evaporation chamber was evacuated to 10 ^-6 Torr by a pump. After that, in order to protect the substrate cleaning surface using the Si oxide film, 6
At 00 ° C., oxygen was introduced into the vicinity of the substrate from the nozzle at a rate of 25 cc / min, and an approximately 1 nm Si oxide film was formed on the surface of the substrate by thermal oxidation. Then, the vacuum evaporation tank was evacuated again to 10 ^-6 Torr, and the substrate was heated to 900 ° C. and rotated. The rotation speed was 20 rpm.

Thereafter, metal Zr was supplied from an evaporation source.
At the same time, oxygen gas is introduced from the nozzle at a rate of 25 cc / min to allow the metal and oxygen to react, thereby causing a Zr having a thickness of about 50 nm.
The O ₂ film 103 was formed as shown in FIG.

[0071] The obtained results of the measured X-ray for the ZrO ₂ thin film 103 is similar to FIG. 6, the ZrO ₂ (002)
The peak was clearly observed, and it was confirmed that a crystal film strongly oriented in an orientation reflecting the crystal structure and symmetry of ZrO ₂ was obtained. When the surface of the ZrO ₂ film was observed by AFM, flatness at the molecular level could be confirmed, and the ten-point average roughness Rz (reference length L: 500 nm) was measured at 10 places over the entire surface of the film according to JIS B0610. The average was 0.60 nm, the maximum was 1.2 nm, and the minimum was 0.20 nm.

Further, when the composition of the region where the ZrO ₂ thin film was formed was examined using EPMA, the impurities were below the detection limit.

When the dielectric constant of this ZrO ₂ film was determined, a value of 20 was obtained, which was at least 6 times higher than the value of 3 of SiO ₂ .

Next, as shown in FIG. 14D, a polycrystalline silicon 104 serving as a gate electrode was formed by a CVD method. The film was formed at a pressure of 5 × 10 ⁻¹ Torr and a substrate temperature of 650 ° C. to form a film having a thickness of 250 nm. Then Figure 1
As shown in (e) of FIG. 4, after patterning by photolithography, RIE etching (reactive ion etching) was performed to obtain an MIS structure.

Thereafter, as shown in FIG.
After P was implanted by ion implantation to form the source and drain 105, annealing was performed at 900 ° C. for 20 minutes. Finally, as shown in FIG. 14 (g), the Al electrode 106 is formed by sputtering, and Al wiring is formed by etching, and the MISFET of Example 2-1 is formed.
Was completed. Using the (111) plane of the Si single crystal substrate as the substrate surface, a ZrO ₂ thin film having a thickness of about 50 nm to be a gate oxide layer is formed thereon in the same manner as described above, and further similar to the above. Then, a gate electrode and the like were formed to obtain a MISFET of Example 2-2.

The semiconductor device processing method described above is a specific example for obtaining the FET according to the present embodiment, and is not particularly limited.

Examples 2-1 and 2 thus obtained
-2 FET uses a ZrO ₂ as MIS capacitors. ZrO ₂ has a dielectric constant of 20 and is at least 6 times larger than that of conventional SiO ₂ , and therefore, it is possible to improve the degree of integration in a planar type without greatly changing the conventional FET manufacturing process. Also, F of Examples 2-1 and 2-2
As described above, the MIS structure in the ET has CV characteristics with very little hysteresis,
When the conventional YSZ is used for the MIS structure, the threshold value at T changes from -1 to 5 V, which is not practical but is stable in the present invention.
It only changed between 4V. In addition, since the leak current was 10 times smaller than that of YSZ, stable transistor characteristics were obtained.

According to the present invention, it is possible to improve the degree of integration and stabilize the threshold value, and it is possible to greatly improve the conventional transistor characteristics.

[0079]

As described above, the ZrO ₂ film epitaxially grown according to the present invention has a high crystallinity and surface property with a purity of 98% or more, and therefore has a CV characteristic like a YSZ film. In addition, good MOS characteristics can be obtained without any hysteresis. This MIS structure is S
It is very useful as an MIS capacitor for an i-device.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a basic structure of a MIS capacitor.

FIG. 2 is a sectional view showing a basic structure of a MISFET.

FIG. 3 is a view showing one example of a vapor deposition apparatus used in the method for manufacturing an electronic device substrate of the present invention.

FIG. 4 is a drawing substitute photograph showing the surface structure of the Si substrate a in Example 1 having a 1 × 1 surface structure formed of Zr metal and oxygen, showing a RHEED pattern, It is a diffraction pattern in which an electron beam was incident from the crystal [110] direction.

FIG. 5 is a drawing substitute photograph showing a surface structure of a Si substrate b in Example 2 having a 1 × 1 surface structure formed of Zr metal and oxygen, showing a RHEED pattern, It is a diffraction pattern in which an electron beam was incident from the crystal [110] direction.

FIG. 6 is an X-ray diffraction diagram of a film structure of ZrO ₂ obtained on a Si (100) substrate.

FIG. 7 is an X-ray diffraction diagram of a film structure of ZrO ₂ obtained on a Si (111) substrate.

FIG. 8 is a drawing substitute photograph showing the crystal structure of ZrO ₂ obtained on a Si (100) substrate, showing a RHEED diffraction pattern when an electron beam is incident from [110] on a Si single crystal substrate. It is.

FIG. 9 is a drawing substitute photograph showing the crystal structure of ZrO ₂ obtained on a Si (111) substrate, showing a RHEED diffraction pattern when an electron beam is incident from [110] on a Si single crystal substrate. It is.

FIG. 10 is a drawing substitute photograph showing the surface of a ZrO ₂ thin film on a Si (100) substrate, and is a thin film surface image of the ZrO ₂ film by an atomic force microscope.

FIG. 11 is a graph showing CV characteristics of a MIS capacitor using a ZrO ₂ film on a Si (100) substrate according to an embodiment of the present invention.

FIG. 12 is a graph showing CV characteristics of a MIS capacitor using a ZrO ₂ film on a Si (111) substrate according to an example of the present invention.

FIG. 13 is a graph showing CV characteristics of a conventional MIS capacitor using a YSZ film.

FIG. 14 is an explanatory diagram for explaining the method for manufacturing the MISFET according to one embodiment of the present invention.

FIG. 15A is a schematic diagram illustrating a RHEED pattern having a 1 × 1 surface structure, and FIG. 15B is a schematic diagram illustrating 2 × 1, 1 ×.
2 or R of the surface structure when they are mixed
It is a schematic diagram which shows a HEED pattern.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Evaporation apparatus 1a Vacuum tank 2 Single crystal substrate 3 Holder 4 Rotating shaft 5 Motor 6 Heater 7 Oxidizing gas supply device 8 Oxidizing gas supply port 9 Zr evaporator 11 Si single crystal substrate 12 Dielectric layer 13 Electrode 14 Electrode 21 Si Single crystal substrate 22 Gate oxide layer 23 Source and drain 24 Source and drain 25 Gate electrode 26 Source and drain electrode 27 Source and drain electrode

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/04 27/108 (56) References JP-A-8-264524 (JP, A) JP-A 8-181289 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/314 H01L 21/316 H01L 21/203 H01L 21/31 H01L 27/04 H01L 27/10

Claims (14)

(57) [Claims] 1. An MIS semiconductor device comprising a Si single-crystal substrate and an insulating layer formed on the Si single-crystal substrate, wherein the insulating layer contains 93 mol% or more of Zr in terms of a constituent element excluding oxygen. A MIS semiconductor device comprising a single-oriented epitaxial film containing ZrO ₂ as a main component. 2. The MIS according to claim 1, wherein a half-width of a rocking curve of reflection of a (002) plane or a (111) plane of the epitaxial film forming the insulating layer is 1.5 ° or less.
Semiconductor device. 3. The epitaxial film forming the insulating layer has at least 80% of its surface a reference length of 500 nm.
3. The MIS semiconductor device according to claim 1, wherein the ten-point average roughness Rz is 2 nm or less. 4. The Si single crystal substrate according to claim 1, wherein the substrate surface is a Si surface-treated substrate having a 1 × 1 surface structure formed by Zr metal and oxygen. MIS semiconductor device. 5. An Si single crystal as the single crystal substrate,
5. The MIS semiconductor device according to claim 1, wherein said (100) plane or (111) plane is used as a substrate surface. 6. The MIS semiconductor device according to claim 1, wherein a dielectric layer is a MIS capacitor constituted by said insulating layer. 7. The MIS semiconductor device according to claim 1, wherein the gate oxide layer is a MISFET including the insulating layer. 8. The method for manufacturing a MIS semiconductor device according to claim 1, wherein the S
i. heating the single crystal substrate, introducing an oxidizing gas into the vacuum chamber, and supplying Zr by evaporation to the surface of the single crystal substrate, and epitaxially growing a ZrO ₂ thin film on the substrate surface of the single crystal substrate. A method for manufacturing a MIS semiconductor device, comprising forming an insulating layer which is a single-oriented epitaxial film containing ZrO ₂ as a main component. 9. The MI according to claim 8, wherein an oxidizing gas is jetted onto the surface of the single crystal substrate from the vicinity thereof, and an atmosphere having a higher partial pressure of the oxidizing gas than other portions is formed only in the vicinity of the single crystal substrate.
A method for manufacturing an S semiconductor device. 10. The single-crystal substrate having a substrate surface area of 1
0 cm ² or more, and by rotating in the substrate plane, the Zr evaporate is supplied over the entire single crystal substrate in the oxidizing gas high partial pressure atmosphere, and over the entire substrate surface of the single crystal substrate. 10. The method for manufacturing a MIS semiconductor device according to claim 8, wherein a substantially uniform single-oriented epitaxial film is formed. 11. A Si single crystal substrate which has been pre-treated so that the substrate surface has a 1 × 1 surface structure formed by Zr and oxygen is used as the Si single crystal substrate. 10. The method for manufacturing a MIS semiconductor device according to any one of the above items. 12. The method of claim 1, further comprising the step of: adding 0.1% to the surface of the Si single crystal substrate.
After forming a Si oxide layer of 2 to 10 nm, the substrate temperature is set at 600 to 1200 ° C. in a vacuum chamber,
An oxidizing gas is introduced into the vacuum chamber to at least set the atmosphere near the substrate to 1 × 10 ⁻⁴ to 1 × 10 ⁻¹ Torr. In this state, Zr is applied to the surface of the substrate on which the Si oxide layer is formed. The method for manufacturing a MIS semiconductor device according to claim 8, wherein a pretreated Si single crystal substrate supplied by evaporation is used. 13. When forming the Si oxide, the Si single crystal substrate is placed in a vacuum chamber into which an oxidizing gas has been introduced.
13. The method for manufacturing a MIS semiconductor device according to claim 12, wherein the Si oxide layer is formed by heating to 700 ° C. and setting the oxygen partial pressure of the atmosphere in the vacuum chamber at least near the substrate to 1 × 10 ⁻⁴ Torr or more. 14. The M according to claim 8, wherein a Si single crystal is used as the Si single crystal substrate so that the (100) plane or the (111) plane becomes the substrate surface.
Manufacturing method of IS semiconductor device.