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JP3227295B2 - Light emitting diode manufacturing method - Google Patents

Light emitting diode manufacturing method

Info

Publication number
JP3227295B2
JP3227295B2 JP33748493A JP33748493A JP3227295B2 JP 3227295 B2 JP3227295 B2 JP 3227295B2 JP 33748493 A JP33748493 A JP 33748493A JP 33748493 A JP33748493 A JP 33748493A JP 3227295 B2 JP3227295 B2 JP 3227295B2
Authority
JP
Japan
Prior art keywords
emitting diode
light emitting
substrate
circuit pattern
diode chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP33748493A
Other languages
Japanese (ja)
Other versions
JPH07202271A (en
Inventor
俊之 鈴木
勲二 中嶋
純 松山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP33748493A priority Critical patent/JP3227295B2/en
Publication of JPH07202271A publication Critical patent/JPH07202271A/en
Application granted granted Critical
Publication of JP3227295B2 publication Critical patent/JP3227295B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/85Packages
    • H10H20/8506Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/85Packages
    • H10H20/857Interconnections, e.g. lead-frames, bond wires or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、薄型の表面実装型発光
ダイオードの製造方法に関するものである。
The present invention relates to a method for manufacturing a surface mount-type light-emitting <br/> diodes thin.

【0002】[0002]

【従来の技術】従来から表面実装型発光ダイオードとし
ては、ガラスエポキシ樹脂積層板などの積層板を基板と
するものが提供されており、この基板にドリル等を用い
てザグリ加工することによって凹部を設け、この凹部内
に発光ダイオードを搭載して製造するようにしている。
しかし、ザグリ加工で形成した凹部のダイボンディング
面となる底面は平坦面にならず、ダイボンディングで発
光ダイオードを搭載することができない。
2. Description of the Related Art Conventionally, as a surface-mount type light emitting diode, a light emitting diode having a laminated board such as a glass epoxy resin laminated board as a substrate has been provided, and a concave portion is formed on this substrate by counterboring using a drill or the like. The light emitting diode is mounted in the concave portion and manufactured.
However, the bottom surface serving as the die bonding surface of the recess formed by the counterbore processing is not flat, and the light emitting diode cannot be mounted by die bonding.

【0003】そこで、図12に示すように、ガラスエポ
キシ樹脂積層板などの積層板で作成される基板1に回路
パターン3を設けると共に基板1の表面に枠状の反射ケ
ース14を接着することによって、ザグリ加工の必要な
く、この反射ケース14の内側に凹部2が形成されるよ
うにし、そして凹部2内において基板1の表面に発光ダ
イオードチップ4を搭載し、さらに発光ダイオードチッ
プ4と回路パターン3との間に金線等のワイヤー5をボ
ンディングした後に、凹部2内に液状の透明樹脂15を
注型して発光ダイオードチップ4とワイヤー5を封止し
て表面実装型発光ダイオードを製造するようにしている
(図12において回路パターン3を斜線で示す)。しか
しこのものでは、基板1の厚みに反射ケース14の厚み
が付加し、全体としての厚みが厚くなって薄型化ができ
ないという問題がある。
Therefore, as shown in FIG. 12, a circuit pattern 3 is provided on a substrate 1 made of a laminate such as a glass epoxy resin laminate, and a frame-like reflection case 14 is adhered to the surface of the substrate 1. The concave portion 2 is formed inside the reflective case 14 without the need for counterboring, and the light emitting diode chip 4 is mounted on the surface of the substrate 1 in the concave portion 2. Then, after bonding a wire 5 such as a gold wire, a liquid transparent resin 15 is poured into the concave portion 2 to seal the light emitting diode chip 4 and the wire 5 to manufacture a surface mount light emitting diode. (In FIG. 12, the circuit pattern 3 is indicated by oblique lines). However, in this case, there is a problem that the thickness of the reflection case 14 is added to the thickness of the substrate 1, so that the overall thickness becomes large and the thickness cannot be reduced.

【0004】このために、特開平1−283883号公
報にみられるような発光ダイオードが提供されるに至っ
ている。このものは図13(a)や図13(b)に示す
ように、熱可塑性樹脂の射出成形で凹部2を設けた基板
1を作成し、立体パターンニングを施して凹部2の底面
に回路パターン3を形成した後に、凹部2内に発光ダイ
オードチップ4を搭載すると共に発光ダイオードチップ
4と凹部2内の回路パターン3との間にワイヤー5をボ
ンディングし、そして凹部2内に液状の透明樹脂15を
注型して発光ダイオードチップ4とワイヤー5を封止し
て表面実装型発光ダイオードを製造するようにしている
(図13において回路パターン3を斜線で示す)。
For this reason, a light emitting diode as disclosed in Japanese Patent Application Laid-Open No. 1-283883 has been provided. As shown in FIGS. 13 (a) and 13 (b), a substrate 1 provided with a concave portion 2 by injection molding of a thermoplastic resin is formed and subjected to three-dimensional patterning to form a circuit pattern on the bottom surface of the concave portion 2 as shown in FIGS. After the formation of the light emitting diode chip 3, the light emitting diode chip 4 is mounted in the recess 2 and the wire 5 is bonded between the light emitting diode chip 4 and the circuit pattern 3 in the recess 2; And the light emitting diode chip 4 and the wire 5 are sealed to manufacture a surface mounted light emitting diode (the circuit pattern 3 is shown by oblique lines in FIG. 13).

【0005】[0005]

【発明が解決しようとする課題】しかし、上記特開平1
−283883号公報の図13(a)や図13(b)の
ものは、凹部2内に発光ダイオードチップ4とワイヤー
5を封止するために、凹部2の深さは発光ダイオードチ
ップ4の上に突出するワイヤー5が納められるように深
く形成する必要があり、この結果、基板1の厚みが厚く
なってしまうものであった。また凹部2の底面に発光ダ
イオードチップ4及びワイヤー5を接続する回路パター
ン3を形成するために、凹部2の面積を大きく形成する
必要があり、基板1もこれに伴って大きく形成する必要
があった。しかも図13(a)や図13(b)のもので
は発光ダイオードチップ4の発光の反射のために凹部2
の側面を傾斜させて反射傾斜面16を形成するようにし
ており、この反射傾斜面16によって凹部2の面積がさ
らに大きくなって基板1もさらに大きくなるものであっ
た。
However, Japanese Patent Application Laid-Open No.
In FIGS. 13 (a) and 13 (b) of JP-A-283883, the depth of the concave portion 2 is set above the light emitting diode chip 4 in order to seal the light emitting diode chip 4 and the wire 5 in the concave portion 2. Therefore, it is necessary to form the substrate 5 deeply so that the wire 5 protruding from the substrate 1 can be accommodated. As a result, the thickness of the substrate 1 is increased. Further, in order to form a circuit pattern 3 for connecting the light emitting diode chip 4 and the wire 5 on the bottom surface of the concave portion 2, it is necessary to increase the area of the concave portion 2, and the substrate 1 also needs to be enlarged accordingly. Was. Moreover, in the case of FIGS. 13A and 13B, the concave portion 2
Are inclined to form the reflection inclined surface 16, and the reflection inclined surface 16 further increases the area of the concave portion 2 and further increases the size of the substrate 1.

【0006】このように特開平1−283883号公報
のものにあっても、小型化や薄型化が困難であるという
問題があった。本発明は上記の点に鑑みてなされたもの
であり、小型化し、薄型化した発光ダイオードを効率良
く製造することができる発光ダイオードの製造方法を提
供することを目的とするものである。
As described above, even in Japanese Patent Application Laid-Open No. 1-283883, there is a problem that it is difficult to reduce the size and thickness. The present invention has been made in view of the above points, and it has been proposed that a small-sized and thin light-emitting diode can be efficiently used.
It is an object of the present invention to provide a method for manufacturing a light emitting diode which can be manufactured with high efficiency.

【0007】[0007]

【課題を解決するための手段】本発明に係る発光ダイオ
ードの製造方法は、基板1の凹部2内に発光ダイオード
チップ4を搭載して発光ダイオードチップ4と基板1の
表面の回路パターン3とをワイヤーボンディングし、発
光ダイオードチップ4とワイヤー5を覆うように透明樹
脂をモールド成形して基板1の表面にモールド部6を設
けて形成される発光ダイオードを製造するにあたって、
樹脂成形して表面に多数の凹部2を複数列配列して設け
ると共に凹部2の各列を分離する分離スリット18を設
けた成形板17を作製し、成形板17の表面にめっきし
て回路パターン3を形成した後、隣り合う凹部2の間に
おいて各分離スリット18を横切って通る線で成形板1
7を切断することによって、凹部2及び回路パターン3
を有する多数の基板1を分離するようにしたことを特徴
とするものである。
According to the present invention, there is provided a method for manufacturing a light emitting diode , comprising the steps of:
The chip 4 is mounted on the light emitting diode chip 4 and the substrate 1.
Wire bonding with circuit pattern 3 on the surface
A transparent tree covering the photodiode chip 4 and the wire 5
A resin is molded to form a mold portion 6 on the surface of the substrate 1.
In manufacturing the light emitting diode formed by
A number of recesses 2 are arranged in a plurality of rows on the surface by resin molding
And a separation slit 18 for separating each row of the recess 2.
A beam forming plate 17 is prepared, and the surface of the forming plate 17 is plated.
After forming the circuit pattern 3 between the concave portions 2 adjacent to each other
In the forming plate 1, a line passing through each separation slit 18 is used.
7 is cut to form the recess 2 and the circuit pattern 3.
, And a large number of substrates 1 having the same are separated .

【0008】[0008]

【0009】[0009]

【0010】[0010]

【作用】基板1の表面に凹部2を形成すると共に基板1
の表面に回路パターン3を設け、発光ダイオードチップ
4を凹部2内に搭載すると共に発光ダイオードチップ4
と基板1の表面の回路パターン3とをワイヤーボンディ
ングするようにしているために、凹部2内にはワイヤー
5を納める必要がないと共に凹部2の底面にワイヤー5
を接続するためのスペースを設ける必要がなく、凹部2
は発光ダイーオドチップ4のみを納める深さと大きさに
形成すればよく、基板1の厚みを薄く、小さく作成する
ことが可能になる。
The concave portion 2 is formed on the surface of the substrate 1 and the substrate 1
A circuit pattern 3 is provided on the surface of the light emitting diode chip 4 and the light emitting diode chip 4 is
The wire 5 is bonded to the circuit pattern 3 on the surface of the substrate 1 by wire bonding.
There is no need to provide a space for connecting
The substrate 1 may be formed to a depth and size that can accommodate only the light emitting diode chip 4, and the substrate 1 can be made thin and small.

【0011】[0011]

【実施例】以下本発明を実施例によって詳述する。図1
及び図2は本発明の一実施例を示すものであり、その製
造の工程を図3に基づいて説明する。まず、熱可塑性樹
脂を射出成形して基板1を作成する。この成形に用いる
熱可塑性樹脂としては、半田付け時の熱処理に対する耐
熱性があり、被めっき性のある樹脂が好ましく、例えば
液晶ポリマー(ポリプラスチックス社製「ベクトラーC
−820」など)や、ポリエーテルイミド(PEI:ゼ
ネラルエレトリック社製「ウルテム」など)、ポリフタ
ルアミド(アモコ社製「アモデル」など)、ポリフェニ
レンオキサイド(PPS:大日本インキ社製など)を用
いることができる。またこの樹脂を成形する成形機とし
ては、射出速度700mm/sec以上の超高速射出成
形機を使用して凹部2の底の薄肉部に十分に樹脂が充填
されるようにするのがよく、例えば日精樹脂工業社製の
「PS80E5H成形機」を用いることができる。
The present invention will be described below in detail with reference to examples. FIG.
2A and 2B show an embodiment of the present invention, and the manufacturing process will be described with reference to FIG. First, a substrate 1 is prepared by injection molding of a thermoplastic resin. As the thermoplastic resin used for this molding, a resin having heat resistance to heat treatment at the time of soldering and a plating property is preferable. For example, a liquid crystal polymer ("Vectra C" manufactured by Polyplastics Co., Ltd.)
-820 "), polyetherimide (PEI:" Ultem "manufactured by General Electric Co., Ltd.), polyphthalamide (Amoco" Amodel ", etc.), and polyphenylene oxide (PPS: manufactured by Dainippon Ink and the like) Can be used. As a molding machine for molding the resin, it is preferable to use an ultra-high-speed injection molding machine having an injection speed of 700 mm / sec or more so that the thin portion at the bottom of the concave portion 2 is sufficiently filled with the resin. A “PS80E5H molding machine” manufactured by Nissei Plastic Industry Co., Ltd. can be used.

【0012】上記のように樹脂の成形で図3(a)のよ
うな表面に凹部2が形成された基板1を作成することが
できるものである。ここで、基板1は多数のものを連続
させると共にこれを複数列配列した図4のような多数個
取り用の成形板17として成形するようにしてある。図
4において18は基板1の各列を分離している分離スリ
ットである。
As described above, the substrate 1 having the concave portion 2 formed on the surface as shown in FIG. 3A can be formed by molding the resin. Here, a large number of substrates 1 are made continuous and formed into a multi-piece molding plate 17 as shown in FIG. In FIG. 4, reference numeral 18 denotes a separation slit separating each row of the substrate 1.

【0013】次に、ソフトエッチング等の処理をして
形板17を構成する各基板1の全面を粗面化した後、無
電解銅めっき等の無電解めっきをおこなって、図3
(b)のように成形板17を構成する各基板1の全面に
1μm程度の厚みの無電解めっき層19を形成する。次
で、成形板17を構成する各基板1の両面に図3(c)
のようにドライフィルムレジスト20をラミネートす
る。ドライフィルムレジスト20としては銅めっきやニ
ッケルめっき、金めっき等の耐めっき製を有するものが
用いられるものであり、例えはデュポン社製の厚み30
μmのネガタイプのものを使用することができる。そし
て図3(d)のようにマスク21をドライフィルムレジ
スト20の表面に重ねて露光し、さらにマスク21を外
して現像することによって、図3(e)に示すように回
路パターン3を形成しない部分を残してドライフィルム
レジスト20を除去してパターンニングする。図5に成
形板17の全体のパターンニングの状態を示す(図5に
おいてドライフィルムレジスト20を斜線で示す)。
[0013] Next, formed by a process such as soft etching
After roughening the entire surface of each substrate 1 constituting the shaped plate 17 , electroless plating such as electroless copper plating is performed, and FIG.
As shown in (b), an electroless plating layer 19 having a thickness of about 1 μm is formed on the entire surface of each substrate 1 constituting the molded plate 17 . Next, both sides of each substrate 1 forming the forming plate 17 are shown in FIG.
The dry film resist 20 is laminated as described above. As the dry film resist 20, a resist having plating resistance such as copper plating, nickel plating, or gold plating is used.
A μm negative type can be used. Then, as shown in FIG. 3D, the mask 21 is overlaid on the surface of the dry film resist 20 and exposed, and the mask 21 is removed and developed, so that the circuit pattern 3 is not formed as shown in FIG. The dry film resist 20 is removed leaving a portion to perform patterning. FIG. 5 shows a patterning state of the entire molding plate 17 (in FIG. 5, the dry film resist 20 is indicated by oblique lines).

【0014】次に、成形板17を構成する各基板1に電
気銅めっき等の電気めっきをおこなって、無電解めっき
層19のうちドライフィルムレジスト20で覆われてい
ない表面に図3(f)のように電気めっき層22を形成
し、さらに電気ニッケルめっき及び金めっきをおこなっ
て、図3(g)のように表面めっき層23を形成する。
このようにして、ドライフィルムレジスト20で覆われ
ていない部分に、無電解めっき層19と電気めっき層2
2と表面めっき層23からなる回路パターン3を形成す
ることができるものであり、この回路パターン3の厚み
は例えば、銅20μm、ニッケル5μm、金0.3μm
である。この後、ドライフィルムレジスト20を図3
(h)のように剥離した後、ドライフィルムレジスト2
0の剥離で露出する無電解めっき層19をソフトエッチ
ングして図3(i)のように除去する。
Next, each substrate 1 constituting the molded plate 17 is subjected to electroplating such as electrocopper plating, and the surface of the electroless plating layer 19 which is not covered with the dry film resist 20 is formed as shown in FIG. The electroplating layer 22 is formed as described above, and further, electroplating nickel and gold are performed to form the surface plating layer 23 as shown in FIG.
In this way, the electroless plating layer 19 and the electroplating layer 2
2 and a surface plating layer 23. The thickness of the circuit pattern 3 is, for example, 20 μm for copper, 5 μm for nickel, and 0.3 μm for gold.
It is. After this, the dry film resist 20 is
After peeling as in (h), dry film resist 2
The electroless plating layer 19 exposed by the separation of 0 is soft-etched and removed as shown in FIG.

【0015】上記のようにして、図6のように成形板1
7を構成する各基板1に回路パターン3を形成すること
ができ(図6において回路パターン3を斜線で示す)、
図6の鎖線の位置で成形板17を切断することによっ
て、回路パターン3を形成した図1に示すような基板1
に分離することができるものである。図1の実施例で
は、回路パターン3は基板1の一方の側部側の回路パタ
ーン3aと他方の側部側の回路パターン3bの離隔され
た一対のもので形成されるようにしてあり(図1におい
て回路パターン3を斜線で示す)、各回路パターン3
a,3bの端部は基板1の側端面から下面にかけて取り
出し用の電極端子部9,9として形成するようにしてあ
る。また凹部2の底面には回路パターン3bの一部をな
すようにダイボンディング部24がめっきで形成してあ
り、さらに凹部2の内側面の全面に回路パターン3bの
一部をなすように反射層25がめっきで形成してあっ
て、発光ダイオードチップ4からの光を反射させて発光
効率を高めるようにしてある。
As described above, as shown in FIG.
7, a circuit pattern 3 can be formed on each substrate 1 (the circuit pattern 3 is shown by oblique lines in FIG. 6),
By cutting the molded plate 17 at the position indicated by the chain line in FIG.
It can be separated into In the embodiment of FIG. 1, the circuit pattern 3 is formed by a pair of circuit patterns 3a on one side of the substrate 1 and a circuit pattern 3b on the other side, which are separated from each other. 1, the circuit pattern 3 is indicated by oblique lines), and each circuit pattern 3
The end portions of a and 3b are formed as extraction electrode terminal portions 9 from the side end surface of the substrate 1 to the lower surface. A die bonding portion 24 is formed by plating on the bottom surface of the concave portion 2 so as to form a part of the circuit pattern 3b, and a reflection layer is formed on the entire inner surface of the concave portion 2 so as to form a part of the circuit pattern 3b. Reference numeral 25 is formed by plating so as to reflect light from the light emitting diode chip 4 to increase luminous efficiency.

【0016】そして、発光ダイオードチップ4をダイボ
ンディング等で凹部2内に固定することによって、回路
パターン3bに電気的に接続した状態で搭載すると共
に、発光ダイオードチップ4と基板1の表面の回路パタ
ーン3aとの間に金線等のワイヤー5をボンディングし
て発光ダイオードチップ4と回路パターン3aとを電気
的に接続し、さらに発光ダイオードチップ4とワイヤー
5を覆うように透明樹脂を成形してモールド部6を基板
1の表面に設けることによって、図1および図2に示す
ような表面実装型の発光ダイオードを作成することがで
きるものである。モールド部6を成形する透明樹脂とし
ては、光を散乱させるための充填剤を含有させたエポキ
シ樹脂等を用いるのが好ましく、基板1を金型にセット
して射出成形等することによって、図12の従来例のよ
うな反射ケース14を用いるような必要なく、モールド
成形でモールド部6を成形するようにしてある。
The light emitting diode chip 4 is fixed in the recess 2 by die bonding or the like, so that the light emitting diode chip 4 is mounted in a state of being electrically connected to the circuit pattern 3b. The light emitting diode chip 4 is electrically connected to the circuit pattern 3a by bonding a wire 5 such as a gold wire between the light emitting diode chip 3a and the transparent resin 3a. By providing the portion 6 on the surface of the substrate 1, a surface-mounted light emitting diode as shown in FIGS. 1 and 2 can be produced. As the transparent resin for molding the mold portion 6, it is preferable to use an epoxy resin or the like containing a filler for scattering light. By setting the substrate 1 in a mold and performing injection molding or the like, FIG. The molding part 6 is formed by molding without the necessity of using the reflection case 14 as in the conventional example.

【0017】上記のように作成される表面実装型の発光
ダイオードにあって、発光ダイオードチップ4と基板1
の表面の回路パターン3aとをワイヤー5で接続するよ
うにしているために、凹部2内にはワイヤー5を納める
必要がないと共に、凹部2の底面にワイヤー5を接続す
るためのスペースを設ける必要がなく、凹部2は発光ダ
イーオドチップ4のみを納める深さと大きさに形成すれ
ばよくなる。従って図13の従来のものに比べて、基板
1の厚みを薄く、小さく作成することが可能になり、発
光ダイオードを薄く小型化して作成することが可能にな
るものである。また、上記のようにモールド部6を成形
する透明樹脂として光を散乱させるための充填剤を含有
させたものを用いると反射効率が高くなって、図13の
従来のもののように反射傾斜面16を凹部2の内側面に
設けるような必要がなく、凹部2の内側面は基板1の表
面に対して垂直面に形成することができ、この点でも基
板1の大きさを小さく形成することができるものであ
る。
In the surface-mounted light emitting diode produced as described above, the light emitting diode chip 4 and the substrate 1
Since the wire 5 is connected to the circuit pattern 3a on the surface of the recess 2, it is not necessary to house the wire 5 in the recess 2 and it is necessary to provide a space for connecting the wire 5 on the bottom surface of the recess 2. The recess 2 may be formed to have a depth and a size that can accommodate only the light emitting diode chip 4. Therefore, the thickness of the substrate 1 can be made thinner and smaller than that of the conventional device shown in FIG. 13, and the light emitting diode can be made thinner and smaller. Further, when a transparent resin containing a filler for scattering light is used as the transparent resin for molding the mold portion 6 as described above, the reflection efficiency is increased, and the reflection inclined surface 16 as shown in FIG. Need not be provided on the inner surface of the recess 2, and the inner surface of the recess 2 can be formed in a plane perpendicular to the surface of the substrate 1. In this regard, the size of the substrate 1 can be reduced. You can do it.

【0018】図1の実施例では例えば、基板1の大きさ
を2.1mm×1.25mm×厚み0.40mm、凹部
2の大きさを直径0.7mm×深さ0.15mm、モー
ルド部6の厚みを0.3mmに形成してあり、回路パタ
ーン3a,3b間の絶縁距離を0.1mmにしてある。
図7は本発明の他の実施例を示すものであり(図7にお
いて回路パターン3を斜線で示す)、凹部2内に複数の
発光ダイオードチップ4を搭載するようにしてある。例
えば赤と緑のように2色の発光ダイオードチップ4を搭
載することによって、3色発光の表面実装型発光ダイオ
ードを作成することができる。勿論、発光ダイオードチ
ップ4の搭載個数は2個(2種類)に限らず、3個の発
光ダイオードチップ4、例えば赤、緑、青の3種類の発
光ダイオードチップ4を搭載するようにすれば、フルカ
ラーの表面実装型発光ダイオードを作成することができ
る。またこの実施例では複数の発光ダイオードチップ4
の共通電極となる凹部2の底面のダイボンディング部2
4は基板1の裏面に形成した回路パターン3bにスルー
ホール26を介して導通接続するようにしてある。勿
論、ダイボンディング部24を各発光ダイオードチップ
4毎に分離して形成すると共に回路パターン3bを同様
に分離して形成するようにしてもよい。
In the embodiment shown in FIG. 1, for example, the size of the substrate 1 is 2.1 mm × 1.25 mm × thickness 0.40 mm, the size of the concave portion 2 is 0.7 mm in diameter × 0.15 mm in depth, Is formed to have a thickness of 0.3 mm, and the insulation distance between the circuit patterns 3a and 3b is set to 0.1 mm.
FIG. 7 shows another embodiment of the present invention (the circuit pattern 3 is shown by oblique lines in FIG. 7), in which a plurality of light emitting diode chips 4 are mounted in the recess 2. For example, by mounting light emitting diode chips 4 of two colors such as red and green, a surface mounted light emitting diode of three colors can be produced. Of course, the number of mounted light emitting diode chips 4 is not limited to two (two types), and if three light emitting diode chips 4, for example, three types of red, green and blue light emitting diode chips 4 are mounted, A full-color surface-mounted light-emitting diode can be manufactured. In this embodiment, a plurality of light emitting diode chips 4
Bonding portion 2 on the bottom surface of concave portion 2 serving as common electrode
Reference numeral 4 denotes a conductive connection through a through hole 26 to a circuit pattern 3b formed on the back surface of the substrate 1. Of course, the die bonding portion 24 may be formed separately for each light emitting diode chip 4 and the circuit pattern 3b may be formed separately.

【0019】図8は本発明のさらに他の実施例を示すも
のであり、基板1の裏面の凹部2に対応する箇所に放熱
用ランド7を設けるようにしてある(図8において回路
パターン3及び放熱用ランド7を斜線で示す)。この放
熱用ランド7は銅めっき等の金属めっきによる金属膜で
凹部2の直径よりも大きな直径の円形に形成してある。
このように放熱用ランド7を設けることによって、凹部
2内に搭載した発光ダイオードチップ4の発熱を効率良
く放熱することができ、また凹部2の底部の薄肉となる
部分を放熱用ランド7で補強することができるものであ
る。
FIG. 8 shows still another embodiment of the present invention, in which a heat radiation land 7 is provided at a position corresponding to the concave portion 2 on the back surface of the substrate 1 (in FIG. The radiating lands 7 are indicated by oblique lines). The heat radiating land 7 is a metal film formed by metal plating such as copper plating and is formed in a circular shape having a diameter larger than the diameter of the concave portion 2.
By providing the radiating land 7 in this manner, the heat generated by the light emitting diode chip 4 mounted in the concave portion 2 can be efficiently radiated, and the thin portion at the bottom of the concave portion 2 is reinforced by the radiating land 7. Is what you can do.

【0020】図9の実施例では、基板1の裏面側に凹部
2に対応する位置において放熱板8をインサート成形し
て設けるようにしてある(図9において回路パターン3
及び放熱板8を斜線で示す)。放熱板8は銅板等の金属
板など熱伝導率が高くまた電気導通性のある材料で、凹
部2の直径よりも大きな直径の円形に形成してあり、放
熱板8の表面を凹部2の底に露出させるようにして凹部
2の底面を放熱板8で形成するようにしてある。また放
熱板8は反射層25を介して回路パターン3bに導通接
続されるようにしてあり、凹部2の底面を形成するこの
放熱板8に発光ダイオードチップ4を搭載することによ
って、発光ダイオードチップ4を回路パターン3bに電
気的に接続することができるようにしてある。このよう
に放熱板8を設けることによって、凹部2内に搭載した
発光ダイオードチップ4の発熱を効率良く放熱すること
ができ、また凹部2の底部の薄肉となる部分を放熱用板
8で補強することができるものである。
In the embodiment shown in FIG. 9, a heat radiating plate 8 is provided by insert molding at a position corresponding to the concave portion 2 on the back surface side of the substrate 1 (in FIG. 9, the circuit pattern 3 is formed).
And the radiator plate 8 is indicated by oblique lines). The heat radiating plate 8 is made of a material having high thermal conductivity and electrical conductivity, such as a metal plate such as a copper plate, and is formed in a circular shape having a diameter larger than the diameter of the concave portion 2. The bottom surface of the concave portion 2 is formed by the heat sink 8 so as to be exposed to the outside. The heat radiating plate 8 is electrically connected to the circuit pattern 3b via the reflection layer 25, and the light emitting diode chip 4 is mounted on the heat radiating plate 8 forming the bottom surface of the concave portion 2 so that the light emitting diode chip 4 is formed. Can be electrically connected to the circuit pattern 3b. By providing the heat radiating plate 8 in this manner, the heat generated by the light emitting diode chip 4 mounted in the concave portion 2 can be efficiently radiated, and the thin portion at the bottom of the concave portion 2 is reinforced by the heat radiating plate 8. Is what you can do.

【0021】図10の実施例では、基板1の表面に透明
樹脂でモールド部6をモールド成形して設けるにあたっ
て、モールド部6の表面を凸レンズなどのレンズの表面
形状に形成するようにしてある。このようにモールド部
6をレンズ形状に形成することによって、発光ダイオー
ドチップ4からの光を集光させて発光効率を高めること
ができるものである。
In the embodiment shown in FIG. 10, when the mold 6 is provided on the surface of the substrate 1 by molding with a transparent resin, the surface of the mold 6 is formed to have the surface shape of a lens such as a convex lens. By forming the mold portion 6 in the shape of a lens as described above, light from the light emitting diode chip 4 can be condensed to increase luminous efficiency.

【0022】図11の実施例は、電極端子部9を設けた
基板1の側端部の下端部に側面と裏面に開口するように
凹段部10を形成するようにしたものであり、マザーボ
ード28等に発光ダイオードを実装するに際して各電極
端子部9を半田29付けをするにあたって、半田29は
凹段部10内に充填されて他方の電極端子部9へと至る
ことを無くすることができ、発光ダイオードの小型化に
伴って電極端子部9の間隔が狭くなっても電極端子部9
が半田29でショートすることを防いで絶縁信頼性を高
めるようにしたものであり、さらに半田付け性も良くす
ることができるものである。
In the embodiment shown in FIG. 11, a concave step portion 10 is formed at the lower end of the side end of the substrate 1 provided with the electrode terminal portion 9 so as to open on the side surface and the back surface. In mounting the light emitting diode on the electrode 28 and the like, the solder 29 is attached to each of the electrode terminal portions 9, so that the solder 29 can be prevented from being filled in the concave step portion 10 and reaching the other electrode terminal portion 9. However, even if the distance between the electrode terminals 9 is reduced due to the miniaturization of the light emitting diode, the electrode terminals 9
Is designed to prevent short-circuiting with the solder 29 to enhance insulation reliability, and to further improve solderability.

【0023】[0023]

【発明の効果】上記のように本発明は、基板の凹部内に
発光ダイオードチップを搭載して発光ダイオードチップ
と基板の表面の回路パターンとをワイヤーボンディング
し、発光ダイオードチップとワイヤーを覆うように透明
樹脂をモールド成形して基板の表面にモールド部を設け
て発光ダイオードを形成するようにしたので、凹部内に
はワイヤーを納める必要がないと共に、凹部の底面にワ
イヤーを接続するためのスペースを設ける必要がなく、
凹部は発光ダイーオドチップのみを納める深さと大きさ
に形成すればよいものであり、基板の厚みを薄くまた小
さく作製することが可能になって、発光ダイオードを薄
く小型化して作製することが可能になるものである
As described above, according to the present invention , the recessed portion of the substrate
Light emitting diode chip mounted with light emitting diode chip
Wire bonding with the circuit pattern on the surface of the board
And transparent to cover the light emitting diode chip and wire
Molding resin to provide a mold part on the surface of the substrate
Since the light emitting diode is formed by the above, it is not necessary to put the wire in the concave portion, and it is not necessary to provide a space for connecting the wire on the bottom surface of the concave portion,
The recess may be formed to a depth and size that can accommodate only the light-emitting diode chip, and the thickness of the substrate can be made thinner and smaller, and the light-emitting diode can be made thinner and smaller. Things .

【0024】[0024]

【0025】[0025]

【0026】また、樹脂成形して表面に多数の凹部を複
数列配列して設けると共に凹部の各列を分離する分離ス
リットを設けた成形板を作製し、成形板の表面にめっき
して回路パターンを形成した後、隣り合う凹部の間にお
いて各分離スリットを横切って通る線で成形板を切断す
ることによって、凹部及び回路パターンを有する多数の
基板を分離るようにしたので、一枚の成形板から多数
の基板を製造することができ、発光ダイオードの製造効
率を高めることができるものであり、しかも成形板から
基板を切り離すときには、各分離スリットを通る一方向
に成形板を切断することによって、この切断線と分離ス
リットで各基板を分離することができるものであり、成
形板からの基板の分離作業を容易に行なうことができる
ものである
Further, to produce a molded plate having a separation slit which separates each column of recesses provided with a number of recesses in the surface and the resin molded multiple column array, the circuit pattern by plating on the surface of the molded plate after forming the, by cutting the molded plate by a line passing across each separation slit between the recess adjacent, since the so that to separate the multiple substrates having a recess and a circuit pattern, a single molding A large number of substrates can be manufactured from a plate, and the production efficiency of light-emitting diodes can be increased.Moreover, when the substrate is separated from the formed plate, by cutting the formed plate in one direction passing through each separation slit. The substrate can be separated by the cutting line and the separation slit, and the work of separating the substrate from the molded plate can be easily performed.
Things .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示すものであり、(a)は
平面図、(b)は正面断面図、(c)は底面図である。
1 shows an embodiment of the present invention, wherein (a) is a plan view, (b) is a front sectional view, and (c) is a bottom view.

【図2】同上の実施例の斜視図である。FIG. 2 is a perspective view of the embodiment.

【図3】同上の製造方法を示すものであり、(a)乃至
(i)は各工程の断面図である。
FIG. 3 is a cross-sectional view of each of the steps, showing a manufacturing method of the above.

【図4】図3(a)の工程における成形板の平面図であ
る。
FIG. 4 is a plan view of a formed plate in the step of FIG.

【図5】図3(e)の工程における成形板の平面図であ
る。
FIG. 5 is a plan view of a formed plate in the step of FIG.

【図6】図3(i)の工程における成形板の平面図であ
る。
FIG. 6 is a plan view of the formed plate in the step of FIG. 3 (i).

【図7】本発明の他の実施例を示すものであり、(a)
は平面図、(b)は正面断面図、(c)は底面図、
(d)は正面図である。
FIG. 7 shows another embodiment of the present invention, in which (a)
Is a plan view, (b) is a front sectional view, (c) is a bottom view,
(D) is a front view.

【図8】本発明のさらに他の実施例を示すものであり、
(a)は平面図、(b)は正面断面図、(c)は底面図
である。
FIG. 8 shows still another embodiment of the present invention;
(A) is a plan view, (b) is a front sectional view, and (c) is a bottom view.

【図9】本発明のさらに他の実施例を示すものであり、
(a)は平面図、(b)は正面断面図、(c)は底面図
である。
FIG. 9 shows still another embodiment of the present invention;
(A) is a plan view, (b) is a front sectional view, and (c) is a bottom view.

【図10】本発明のさらに他の実施例を示す正面断面図
である。
FIG. 10 is a front sectional view showing still another embodiment of the present invention.

【図11】本発明のさらに他の実施例を示すものであ
り、(a)は正面断面図、(b)は底面図、(c)は底
面側の斜視図である。
11A and 11B show still another embodiment of the present invention, wherein FIG. 11A is a front sectional view, FIG. 11B is a bottom view, and FIG. 11C is a bottom perspective view.

【図12】従来例を示すものであり、(a)は平面図、
(b)は正面断面図である。
FIG. 12 shows a conventional example, in which (a) is a plan view,
(B) is a front sectional view.

【図13】他の従来例を示すものであり、(a),
(b)はそれぞれ正面断面図である。
FIG. 13 shows another conventional example, in which (a),
(B) is a front sectional view, respectively.

【符号の説明】[Explanation of symbols]

1 基板 2 凹部 3 回路パターン 4 発光ダイオードチップ 5 ワイヤー 6 モールド部 7 放熱用ランド 8 放熱板 9 電極端子部 10 凹段部17 成形板 18 分離スリット 24 ダイボンディング部 26 スルーホール  DESCRIPTION OF SYMBOLS 1 Substrate 2 Concave part 3 Circuit pattern 4 Light emitting diode chip 5 Wire 6 Mold part 7 Heat radiating land 8 Heat radiating plate 9 Electrode terminal part 10 Concave step part17 Molded plate 18 Separation slit 24 Die bonding part 26 Through Hole

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平4−354073(JP,A) 特開 平5−11718(JP,A) 特開 平5−46100(JP,A) 特開 平5−29659(JP,A) 実開 平5−8959(JP,U) 実開 昭64−13167(JP,U) (58)調査した分野(Int.Cl.7,DB名) H01L 33/00 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-354073 (JP, A) JP-A-5-11718 (JP, A) JP-A-5-46100 (JP, A) 29659 (JP, A) Japanese Utility Model Hei 5-8959 (JP, U) Japanese Utility Model Sho 64-13167 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 33/00

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板の凹部内に発光ダイオードチップを
搭載して発光ダイオードチップと基板の表面の回路パタ
ーンとをワイヤーボンディングし、発光ダイオードチッ
プとワイヤーを覆うように透明樹脂をモールド成形して
基板の表面にモールド部を設けて形成される発光ダイオ
ードを製造するにあたって、樹脂成形して表面に多数の
凹部を複数列配列して設けると共に凹部の各列を分離す
る分離スリットを設けた成形板を作製し、成形板の表面
にめっきして回路パターンを形成した後、隣り合う凹部
の間において各分離スリットを横切って通る線で成形板
を切断することによって、凹部及び回路パターンを有す
る多数の基板を分離するようにしたことを特徴とする発
光ダイオードの製造方法。
A light emitting diode chip is provided in a recess of a substrate.
Mounted light emitting diode chip and circuit pattern on substrate surface
Wire bonding to the light emitting diode chip.
Mold the transparent resin to cover the loop and wire
Light emitting diode formed by providing a mold part on the surface of the substrate
When manufacturing a resin, a large number of
Provide multiple rows of recesses and separate each row of recesses
A molded plate with a separation slit
After forming a circuit pattern by plating
Between the forming plates with a line passing across each separation slit
Has a concave portion and a circuit pattern by cutting
A large number of substrates separated from each other.
A method for manufacturing a photodiode.
JP33748493A 1993-12-28 1993-12-28 Light emitting diode manufacturing method Expired - Lifetime JP3227295B2 (en)

Priority Applications (1)

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JP33748493A JP3227295B2 (en) 1993-12-28 1993-12-28 Light emitting diode manufacturing method

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Application Number Priority Date Filing Date Title
JP33748493A JP3227295B2 (en) 1993-12-28 1993-12-28 Light emitting diode manufacturing method

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JP3227295B2 true JP3227295B2 (en) 2001-11-12

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