JP3223903B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect transistor (Field Effect Transistor).
r; “FET”) and a method of manufacturing the same, and more particularly, to a heterojunction field-effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art An example of this kind of conventional technology is "Electronic Information Communication Society 1996 Electronics Society Conference Park Paper Collection 2: Naoto Yoshida, Hideaki Katayama, Akira Inoue, Kazuo Hayashi, Takahiro Nakamoto, Tomoyuki Asada, Yutaka Torihime , Noriyuki Tanino, Masahide Yamauchi, 8
Line 0, line 18 and Figure 1, Date of issue August 30, 1996
Date.

[0003] GaAs FETs are widely and generally used as high frequency devices. In particular, in the high-output device, a multi-stage recess structure is adopted to reduce source resistance and secure gate breakdown voltage.

The "recess structure" refers to a structure in which the source and drain regions are masked and the vicinity of the gate is dug by etching, and the "multi-step recess structure" refers to a structure in which a plurality of steps are dug.

[0005] Such a multi-step recess structure is, for example, Ga
Using selective etching of As / AlGaAs stacked structure
It is formed. FIG. 18 shows a conventional field effect transistor.
FIG. 801 in FIG. 18 is a semi-insulating GaAs group
802, a GaAs buffer layer having a thickness of 400 nm;
03 is undoped Al_0.2 Ga_0.8 As buffer
Layer 804 is Si-doped Al_0.2 Ga_0.8 As Den children
Feed layer, 805 is undoped Al_0.2 Ga_0.8 As Spec
Layer 806 is undoped In_0.2 Ga_0.8As Chi
Channel layer, 807 is undoped Al _0.2 Ga_0.8 As
Spacer layer, 808 is Si-doped Al_0.2 Ga_0.8 
As electron supply layer, 809 is undoped Al _0.2 Ga_0.8
 As gate contact layer, 810 is GaAs gate buried
Embedded layer, 811 is Si-doped Al_0.2 Ga_0.8 As
Wide recess stopper layer, 812 is Si-doped GaAs
A cap layer, 813 is a gate electrode, 814 is a source electrode.
The pole 815 is a drain electrode.

In such a recess structure, first, a mask (not shown) in which a first recess (wide recess) portion 821 is opened is formed, and the GaAs layer 812 is selectively etched using the AlGaAs layer 811 as a wide recess stopper.
Next, a mask (not shown) having an opening in the second recess (gate recess) portion 822 is formed, and the GaAs layer 810 is selectively etched using the AlGaAs layer 809 as a gate recess stopper layer.

FIG. 18 schematically shows a distribution constant electric resistance generated in each portion of the FET having the conventional structure.
R1 is the contact resistance from the ohmic electrodes (source electrode 814 and drain electrode 815) to the cap layer 812, R2 is the contact resistance from the cap layer 812 to the channel layer 806, and R3 is the sheet resistance below the gate 813. The on-resistance of the FET is equal to the source electrode 814.
To the drain electrode 815.

[0008] Another document "1996 IEEE Ga"
As described in “As IC Symposium, page 119”, low on-resistance is important for obtaining high output and high efficiency in low voltage operation.

[0009] Other examples of this type of prior art are disclosed in Japanese Patent Application Laid-Open No. 9-102600 and Japanese Patent No. 2626213.

[0010]

However, the prior art has a disadvantage that the contact resistance R2 from the cap layer to the channel layer is high. The reason is that the potential barrier of the AlGaAs stopper layer used for forming the multi-stage recess structure is high, and the tunnel probability from the cap layer to the channel layer is small. However, it is difficult to make this layer thin because it is used as a stopper layer for selective etching.

An object of the present invention is to provide a field effect transistor capable of reducing the contact resistance from the cap layer to the channel layer and a method for manufacturing the same.

[0012]

According to the present invention, there is provided a channel layer made of InGaAs or GaAs, and an AlGaAs doped with a first n-type impurity.
Layer, an AlGaAs / GaAs superlattice layer, a GaAs layer, an AlGaAs layer doped with a second n-type impurity, and a cap layer composed of InGaAs or GaAs doped with an n-type impurity for an ohmic electrode. And
A first recess formed in the second AlGaAs layer and the cap layer; and a second recess formed in the first recess and in the AlGaAs / GaAs superlattice layer and the GaAs layer. And a gate electrode provided in the second recess.

Another invention according to the present invention relates to InGaAs.
s or GaAs channel layer, first n-type
AlGaAs layer doped with pure material , AlGaAs / Ga
Doping an As superlattice layer, a GaAs layer, and a second n-type impurity
N-type impurity for the AlGaAs layer and the ohmic electrode
A first step of sequentially laminating a cap layer made of InGaAs or GaAs doped with GaAs, and a second step of forming a first recess in the second AlGaAs layer and the cap layer after the first step. And, after the second step, in the first recess and the AlGa
A third step of forming a second recess in the As / GaAs superlattice layer and the GaAs layer; and a fourth step of providing a gate electrode in the second recess after the third step. And

According to the present invention and another invention according to the present invention, AlGaAs / Ga is formed on the first AlGaAs layer.
Since the As superlattice layer is stacked, the contact resistance can be reduced.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings. First, the first embodiment will be described. The first embodiment relates to the first and eighth aspects of the present invention.

FIG. 1 is a cross-sectional view showing the structure of the first embodiment of the present invention, FIGS. 2 to 4 are cross-sectional views in the manufacturing process of the same embodiment, and FIG. 5 is a flowchart showing the manufacturing process of the same embodiment. . Hereinafter, the first embodiment will be described with reference to FIGS.

First, on a semi-insulating GaAs substrate 101,
GaAs buffer layer 102 having a thickness of 400 nm and a thickness of 10
0 nm undoped Al _0.2 Ga _0.8 As buffer layer 103, 4 n thick doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
m Al _0.2 Ga _0.8 As electron supply layer 104, thickness 2
nm undoped Al _0.2 Ga _0.8 As spacer layer 1
05, undoped In _0.2 Ga _0.8 A with a thickness of 15 nm
s channel layer 106, undoped Al _{0.2 with} a thickness of 2 nm
Ga _0.8 As spacer layer 107, Si is 4 × 10 ¹⁸ c
9 nm thick Al _0.2 Ga _0.8 As electron supply layer 108 doped with m ⁻³ , 17 nm thick undoped Al _0.2
Ga _0.8 As Schottky gate contact layer 109,
Al _0.2 Ga _0.8 As (0.5 nm) / GaAs
(0.5 nm) × 3-period superlattice layer 110, film thickness 30n
m undoped GaAs buried layer 111, 4 ×
10 ¹⁸ cm ^-3 doped thickness 6nm of Al _0.2 Ga _0.8
As wide recess stopper layer 112, 4 × 10 Si
^A 100 nm-thick GaAs cap layer 113 doped with ¹⁸ cm ^-3 is sequentially epitaxially grown by molecular beam epitaxy or metal organic chemical vapor deposition (S1). FIG. 2 shows the structure after the epitaxial growth.

Next, a mask 901 having a wide recess is formed on the wafer prepared as shown in FIG.
2), a GaAs cap layer 113 using the Al _0.2 Ga _0.8 As wide recess stopper layer 112 as a stopper layer.
Is selectively etched (S3). Such selective etching uses an ECR etching apparatus or an RIE apparatus, and uses a mixed gas (for example, B2) of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine as a halogen element.
Cl ₃ ⁺ SF _6, etc.) can be by dry etching was introduced.

After the mask is removed, a mask 902 having a new gate recess is formed as shown in FIG. 4 (S4), and the GaAs gate buried layer is formed by using the Al _0.2 Ga _0.8 As gate contact layer 109 as a stopper layer. 1
10, Al _0.2 Ga _0.8 As (0.5 nm) / GaAs
The superlattice layer 110 of s (0.5 nm) × 3 periods is selectively etched (S5).

Next, Al _0.2 exposed as a result of the etching is used.
Exposed portion 10 of Ga _0.8 As gate contact layer 109
A gate electrode 114 is formed on 9a (S6), and AuGe is vapor-deposited by lift-off and alloying (for example, 400 ° C./min).
To form a source electrode 115 and a drain electrode 116 as ohmic electrodes (S7).

According to the structure of the first embodiment, A acts as a potential barrier between the source and the drain.
AlGaAs / G is formed on the lGaAs Schottky layer 108.
Since the aAs superlattice layer 110 is laminated, Ga
The bending of the conduction band occurring at the interface with the As buried layer 111 is reduced, and the sheet resistance at this portion is reduced. Immediately below the gate Schottky, φB (Schottky barrier height; unit electron volt, hereinafter the same) which is effective in forming the Schottky layer since the AlGaAs / GaAs superlattice layer 110 is shaved during gate recess formation is Al _0.2 Ga _0.8 As. Take the value of
As a result, the 0.1 Ω · mm on-resistance is reduced.

Next, a second embodiment will be described. The second embodiment relates to the second and ninth aspects of the present invention.

FIG. 6 is a sectional view showing the structure of the second embodiment of the present invention, and FIG. 7 is a flowchart showing the manufacturing process of the same embodiment. In the following embodiments, a cross-sectional view of the same embodiment in a manufacturing process is omitted. Hereinafter, FIG.
A second embodiment will be described with reference to FIG.

On a semi-insulating GaAs substrate 201, a film thickness of 4
GaAs buffer layer 202 of 00 nm, thickness of 100 nm
Undoped Al_0.2 Ga_0.8 As buffer layer 20
3, 4 × 10 Si¹⁸cm^-34 nm thick doped A
l_0.2 Ga_0.8 As electron supply layer 204, 2 nm thick
Undoped Al_0.2 Ga_0.8 As spacer layer 205,
Undoped In with a thickness of 15 nm_0.2 Ga_0.8 As Cha
Tunnel layer 206, undoped Al having a thickness of 2 nm_0.2 Ga
_0.8 As spacer layer 207, 4 × 10 Si¹⁸cm^-3
Al doped 9nm thick_0.2 Ga_0.8 As Den children
Supply layer 208, undoped Al with a thickness of 17 nm_0.2 Ga
_0.8 Schottky gate contact layer 209, thickness 30
undoped GaAs buried layer 210 nm,
× 10¹⁸cm ^-3Al doped 3nm thick_0.2 Ga
_0.8 As wide recess stopper layer 211, Si is 4 ×
10¹⁸cm^-3Al doped 3nm thick_0.1 Ga_0.9
 As layer 212, 4 × 10 Si¹⁸cm^-3Doped film thickness
A 100 nm GaAs cap layer 213 is sequentially formed with a molecular beam.
Epitaxial growth by long method or metalorganic vapor phase epitaxy
(S11).

A wide recess is opened on the formed wafer.
A mask is formed (S12). _0.2 Ga_0.8 As
Using the wide recess stopper layer 211 as the stopper layer,
l_{0. 1} Ga_0.9 As layer 212, GaAs cap layer 2
The 13 layers are selectively etched (S13).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0027] After removing the mask, to form a new mask gate recess is opened (S14), Al _0.2 G
The GaAs gate buried layer 210 is selectively etched using the a _0.8 As gate contact layer 209 as a stopper layer (S15). A gate electrode 214 is formed on the gate contact layer 209 exposed on the surface (S1)
6). Next, AuGe is subjected to vapor deposition lift-off and alloying (for example, 400 ° C./min), and
A source electrode 215 and a drain electrode 216 are formed (S17).

According to the structure of the second embodiment, AlG
Since the aAs wide recess stopper layer has a two-stage structure (211 layers and 212 layers), the sheet resistance in this portion is reduced. As a result, 0.05Ω · mm
ON resistance is reduced.

Next, a third embodiment will be described. The third embodiment relates to the third and tenth aspects of the present invention.

FIG. 8 is a sectional view showing the structure of the third embodiment of the present invention, and FIG. 9 is a flow chart showing the manufacturing process of the third embodiment. Hereinafter, the third embodiment will be described with reference to FIGS.

On a semi-insulating GaAs substrate 301, a film having a thickness of 4
GaAs buffer layer 302 of 00 nm, thickness of 100 nm
Undoped Al_0.2 Ga_0.8 As buffer layer 30
3, 4 × 10 Si¹⁸cm^-34 nm thick doped A
l_0.2 Ga_0.8 As electron supply layer 304 having a thickness of 2 nm
Undoped Al_0.2 Ga_0.8 As spacer layer 305,
Undoped In with a thickness of 15 nm_0.2 Ga_0.8 As Cha
Flannel layer 306, 2 nm-thick undoped Al_0.2 Ga
_0.8 As spacer layer 307, 4 × 10 Si¹⁸cm^-3
Al doped 9nm thick_0.2 Ga_0.8 As Den children
Supply layer 308, undoped Al with a thickness of 17 nm_0.2 Ga
_0.8 As Schottky gate contact layer 309, thickness
30 nm undoped GaAs buried layer 310, Si
Is 4 × 10¹⁸cm^-3Al doped 3nm thick_0.2 
Ga_0.8 As layer 311, Si is 4 × 10¹⁸cm^-3Do
0.5nm thick Al_0.18Ga_0.82As layer 31
2, 4 × 10 Si¹⁸cm^-30.5nm doped film thickness
Al_0.15Ga_0.85As layer 313, Si is 4 × 10¹⁸c
m^-30.5 nm thick doped Al_0.12Ga_0.88As
Layer 314, 4 × 10 Si¹⁸cm^-3Doped film thickness
5nm Al_0.09Ga_0.91As layer 315, Si 4 × 1
0¹⁸cm^-30.5 nm thick doped Al_0.06Ga
_0.94As layer 316, 4 × 10 Si¹⁸cm^-3Doped
0.5 nm thick Al_{0. 03}Ga_0.97As layer 317, Si
Is 4 × 10¹⁸cm^-3100 nm doped GaAs
The s cap layer 318 is sequentially formed by a molecular beam growth method or an organic metal
Epitaxial growth is performed by a phase growth method (S21).

A wide recess is opened on the formed wafer.
A mask is formed (S22). _0.2 Ga_0.8 As
Using the wide recess stopper layer 311 as a stopper layer,
lGaAs layers 312-317, GaAs cap layer 31
The three layers are selectively etched (S23).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chlorine gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0034] After removing the mask, to form a new mask gate recess is opened (S24), Al _0.2 G
The GaAs gate buried layer 310 is selectively etched using the a _0.8 As gate contact layer 309 as a stopper layer (S25).

Gate contact layer 309 exposed on the surface
A gate electrode 319 is formed thereon (S26). Then Au
Ge is vapor-deposited by lift-off and alloy (for example, 400 ° C./m
in), and the source electrode 32 is formed as an ohmic electrode.
0 and a drain electrode 321 are formed (S27).

According to the structure of the third embodiment, AlG
Since the aAs wide recess stopper layer has a two-stage structure (311 layers and 312 to 317 layers), the sheet resistance in this portion is reduced. As a result, 0.05
Ω · mm ON resistance is reduced.

Next, a fourth embodiment will be described. The fourth embodiment relates to the fourth and eleventh inventions.

FIG. 10 is a sectional view showing the structure of the fourth embodiment of the present invention, and FIG. 11 is a flowchart showing the manufacturing steps of the fourth embodiment. Hereinafter, the fourth embodiment will be described with reference to FIGS.

On a semi-insulating GaAs substrate 401, a film having a thickness of 4
GaAs buffer layer 402 having a thickness of 100 nm and a thickness of 100 nm
Undoped Al _0.2 Ga _0.8 As buffer layer 40
3, 4 nm thick A doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
l _0.2 Ga _0.8 As electron supply layer 404, undoped Al _0.2 Ga _0.8 As spacer layer 405 having a thickness of 2 nm,
Undoped In _0.2 Ga _0.8 As channel layer 406 with a thickness of 15 nm, undoped Al _0.2 Ga with a thickness of 2 nm
_0.8 As spacer layer 407, Si is 4 × 10 ¹⁸ cm ⁻³
A doped 9-nm thick Al _0.2 Ga _0.8 As electron supply layer 408, a 17-nm thick undoped Al _0.2 Ga
_0.8 As Schottky gate contact layer 409, undoped Al _0.1 Ga _0.9 As layer 410 having a thickness of 3 nm,
An undoped GaAs buried layer 411 having a thickness of 30 nm;
3 nm thick Al _0.2 G doped with 4 × 10 ¹⁸ cm ⁻³ of Si doped with 4 × 10 ¹⁸ cm ⁻³ of Si
a _0.8 As wide recess stopper layer 412, 4 × Si
10 ¹⁸ cm ^-3 Al _0.1 Ga _0.9 of doped thickness 3nm
An AsAs layer 413 and a 100 nm-thick GaAs cap layer 414 doped with Si at 4 × 10 ¹⁸ cm ⁻³ are sequentially epitaxially grown by molecular beam growth or metal organic chemical vapor deposition (S31).

A wide recess is opened on the created wafer.
A mask is formed (S32). _0.2 Ga_0.8 As
Using the wide recess stopper layer 412 as a stopper layer,
aAs cap layer 414 layer and AlGaAs 413 layer were selected.
It is selectively etched (S33).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0042] After removing the mask, to form a new mask gate recess is opened (S34), Al _0.2 G
a _0.8 As gate contact layer 409 is used as a stopper layer to form a GaAs gate buried layer 411 and Al _0.1 G
a _0.9 As layer 410 is selectively etched (S3
5).

Gate contact layer 409 exposed on the surface
A gate electrode 415 is formed thereon (S36). Then Au
Ge is vapor-deposited by lift-off and alloy (for example, 400 ° C./m
in), and the source electrode 41 is formed as an ohmic electrode.
6 and a drain electrode 417 are formed (S37).

According to the structure of the fourth embodiment, A which acts as a potential barrier between the source and the drain is used.
The lGaAs Schottky layer has a two-stage structure (41).
With two layers and 413 layers), the sheet resistance in this portion is reduced. Moreover, [phi] B come into play in the Schottky layer formed since the scraping Schottky layer 410 layer at the gate recess formed in the gate Schottky immediately below Al _0.2
Take the value of Ga _0.8 As. As a result, 0.15Ω
mm on-resistance is reduced.

Next, a fifth embodiment will be described. The fifth embodiment relates to the fifth and twelfth aspects.

FIG. 12 is a sectional view showing the structure of the fifth embodiment of the present invention, and FIG. 13 is a flowchart showing the manufacturing steps of the fifth embodiment. Hereinafter, the fifth embodiment will be described with reference to FIGS.

On a semi-insulating GaAs substrate 501, a film thickness of 4
GaAs buffer layer 502 of 00 nm, thickness of 100 nm
Undoped Al _0.2 Ga _0.8 As buffer layer 50
3, 4 nm thick A doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
l _0.2 Ga _0.8 As electron supply layer 504, undoped Al _0.2 Ga _0.8 As spacer layer 505 having a thickness of 2 nm,
Undoped In _0.2 Ga _0.8 As channel layer 506 with a thickness of 15 nm, undoped Al _0.2 Ga with a thickness of 2 nm
_0.8 As spacer layer 507, Si is 4 × 10 ¹⁸ cm ⁻³
Doped 9 nm thick Al _0.2 Ga _0.8 As electron supply layer 508, 17 nm thick undoped Al _0.2 Ga
_0.8 As Schottky gate contact layer 509, Al
_0.2 Ga _0.8 As (0.5 nm) / GaAs (0.5
nm) × 3-period superlattice layer 510, 30 nm-thick undoped GaAs buried layer 511, Si is 4 × 10 ¹⁸ c
Al _0.2 Ga _0.8 As wide recess stopper layer 512 with a thickness of 3 nm doped with m ⁻³ doped Si with a thickness of 4 nm and 4 × 10 ¹⁸ cm ^−3, and a 3 nm thick Si doped with 4 × 10 ¹⁸ cm ⁻³ doped Si with a thickness of 4 × 10 ¹⁸ cm ⁻³ . Al _0.1 Ga _0.9 As layer 513, S
i is 4 × 10 ¹⁸ cm ⁻³ doped Ga having a thickness of 100 nm
The As cap layer 514 is sequentially epitaxially grown by a molecular beam growth method or a metal organic chemical vapor deposition method (S41).

A wide recess is opened on the formed wafer.
A mask is formed (S42). _0.2 Ga_0.8 As
Using wide recess stopper layer 512 as a stopper layer,
a Cap layer 514 and AlGaAs layer 513 are selected.
It is selectively etched (S43).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0050] After removing the mask, to form a new mask gate recess is opened (S44), Al _0.2 G
Using the a _0.8 As gate contact layer 509 as a stopper layer, the GaAs gate buried layer 511, Al _0.2 G
a _0.8 As (0.5 nm) / GaAs (0.5 nm)
The superlattice layer 510 of × 3 periods is selectively etched (S45).

Gate contact layer 509 exposed on the surface
A gate electrode 515 is formed thereon (S46). Then Au
Ge is vapor-deposited by lift-off and alloy (for example, 400 ° C./m
in), and the source electrode 51 is formed as an ohmic electrode.
6 and a drain electrode 517 are formed (S47).

According to the structure of the fifth embodiment, A acts as a potential barrier between the source and the drain.
The 1-GaAs Schottky layer has a two-stage structure (51).
With two layers and 513 layers), the sheet resistance in this portion is reduced. Moreover, [phi] B come into play in the Schottky layer formed since the scraping AlGaAs layer 510 layer at the gate recess formed in the gate Schottky immediately below Al _0.2
Take the value of Ga _0.8 As. As a result, 0.15Ω
mm on-resistance is reduced.

Next, a sixth embodiment will be described. The sixth embodiment relates to the sixth and thirteenth inventions.

FIG. 14 is a sectional view showing the structure of the sixth embodiment of the present invention, and FIG. 15 is a flowchart showing the manufacturing steps of the sixth embodiment. Hereinafter, the sixth embodiment will be described with reference to FIGS. 14 and 15.

On a semi-insulating GaAs substrate 601, a film thickness of 4
00 nm GaAs buffer layer 602, 100 nm thick
Undoped Al _0.2 Ga _0.8 As buffer layer 60
3, 4 nm thick A doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
l _0.2 Ga _0.8 As electron supply layer 604, an undoped Al _0.2 Ga _0.8 As spacer layer 605 having a thickness of 2 nm,
Undoped In _0.2 Ga _0.8 As channel layer 606 with a thickness of 15 nm, undoped Al _0.2 Ga with a thickness of 2 nm
_0.8 As spacer layer 607, 4 × 10 ¹⁸ cm ^{−3 of} Si
Doped 9 nm thick Al _0.2 Ga _0.8 As electron supply layer 608, 17 nm thick undoped Al _0.2 Ga
_0.8 As Schottky gate contact layer 609, undoped Al _0.1 Ga _0.9 As layer 610 having a thickness of 3 nm,
An undoped GaAs buried layer 611 having a thickness of 30 nm;
3 nm thick Al doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
_0.2 Ga _0.8 As layer 612, Si is 4 × 10 ¹⁸ cm ⁻³
0.5 nm doped Al _0.18 Ga _0.82 As layer 6
13. Film thickness 0.5n doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
m Al _0.15 Ga _0.85 As layer 614, Si is 4 × 10 ¹⁸
0.5 nm thick Al _0.12 Ga _0.88 A doped with cm ^-3
s layer 615, Al _0.09 Ga _0.91 As layer 616 with a thickness of 0.5 nm doped with 4 × 10 ¹⁸ cm ^{−3 of} Si, 4
× 10 ¹⁸ cm ^-3 doped Al _0.06 G with a thickness of 0.5 nm
a _0.94 As layer 617, Al _0.03 Ga _0.97 As layer 618 doped with Si at 4 × 10 ¹⁸ cm ^-3 and having a thickness of 0.5 nm, S
i is 4 × 10 ¹⁸ cm ⁻³ doped Ga having a thickness of 100 nm
The As cap layer 619 is epitaxially grown sequentially by a molecular beam growth method or a metal organic chemical vapor deposition method (S51).

A wide recess is opened on the created wafer.
A mask is formed (S52). _0.2 Ga_0.8 As
Using the wide recess stopper layer 612 as the stopper layer,
aAs cap layer 614, AlGaAs layers 613-6
18 is selectively etched (S53).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chlorine gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0058] After removing the mask, to form a new mask gate recess is opened (S54), Al _0.2 G
Using the a _0.8 As gate contact layer 609 as a stopper layer, the GaAs gate buried layer 611, Al _0.1 G
a _0.9 As layer 610 is selectively etched (S5
5).

Gate contact layer 609 exposed on the surface
A gate electrode 620 is formed thereon (S56). Then Au
Ge is vapor-deposited by lift-off and alloy (for example, 400 ° C./m
in) to form a source electrode 62 as an ohmic electrode.
1 and a drain electrode 622 are formed (S57).

According to the structure of the sixth embodiment, A acts as a potential barrier between the source and the drain.
The lGaAs Schottky layer has a two-stage structure (61).
With two layers and 613 to 618 layers), the sheet resistance in this portion is reduced. Immediately below the gate Schottky, since the AlGaAs layer 610 is shaved during the formation of the gate recess, φB effective for forming the Schottky layer has a value of Al _0.2 Ga _0.8 As. As a result, 0.
15 Ω · mm on-resistance is reduced.

Next, a seventh embodiment will be described. The seventh embodiment relates to the seventh and fourteenth aspects of the present invention.

FIG. 16 is a sectional view showing the structure of the seventh embodiment of the present invention, and FIG. 17 is a flow chart showing the manufacturing steps of the seventh embodiment. Hereinafter, the seventh embodiment will be described with reference to FIGS. 16 and 17.

On a semi-insulating GaAs substrate 701, a film thickness of 4
GaAs buffer layer 702 of 00 nm, thickness of 100 nm
Undoped Al_0.2 Ga_0.8 As buffer layer 70
3, 4 × 10 Si¹⁸cm^-34 nm thick doped A
l_0.2 Ga_0.8 As electron supply layer 704 having a thickness of 2 nm
Undoped Al_0.2 Ga_0.8 As spacer layer 705,
Undoped In with a thickness of 15 nm_0.2 Ga_0.8 As Cha
Flannel layer 706, undoped Al 2 nm thick_0.2 Ga
_0.8 As spacer layer 707, 4 × 10 Si¹⁸cm^-3
Al doped 9nm thick_0.2 Ga_0.8 As Den children
Feed layer 708, undoped Al with a thickness of 17 nm_0.2 Ga
_0.8 As Schottky gate contact layer 709, Al
_0.2 Ga_0.8 As (0.5 nm) / GaAs (0.5
nm) × 3-period superlattice layer 710, 30 nm thick
Doped GaAs buried layer 711, 4 × 10¹⁸c
m^-3Al doped 3nm thick_0.2 Ga_0.8 As layer
712, 4 × 10 Si¹⁸cm^-30.5 doped film thickness
nm Al_0.18Ga_0.82As layer 713, Si is 4 × 10
¹⁸cm^-30.5 nm thick doped Al_0.15Ga_0.85
As layer 714, Si 4 × 10¹⁸cm^-3Doped film thickness
0.5 nm Al_0.12Ga_0.88As layer 715, Si 4
× 10¹⁸cm^-30.5 nm thick doped Al _0.09G
a_0.91As layer 716, 4 × 10 Si¹⁸cm^-3Dope
Al with a thickness of 0.5 nm_0.06Ga_0.94As layer 717, S
i is 4 × 10¹⁸cm^-30.5 nm thick doped Al
_0.03Ga_0.97As layer 718, 4 × 10¹⁸cm^-3Do
GaAs cap layer 719 with a thickness of 100 nm
Epitaxy by sequential molecular beam epitaxy or metalorganic vapor phase epitaxy
It grows axially (S61).

A wide recess is opened on the created wafer.
A mask is formed (S62). _0.2 Ga_0.8 As
Using wide recess stopper layer 712 as a stopper layer,
aAs cap layer 714, AlGaAs layers 713 to 71
8 is selectively etched (S63).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0066] After removing the mask, to form a new mask gate recess is opened (S64), Al _0.2 G
Using the a _0.8 As gate contact layer 709 as a stopper layer, the GaAs gate buried layer 711 and the Al _0.2 G
a _0.8 As (0.5 nm) / GaAs (0.5 nm)
The superlattice layer 710 of × 3 periods is selectively etched (S65).

Gate contact layer 709 exposed on the surface
A gate electrode 720 is formed thereon (S66). Then Au
Ge is vapor-deposited by lift-off and alloy (for example, 400 ° C./m
in), and the source electrode 72 is formed as an ohmic electrode.
1 and a drain electrode 722 are formed (S67).

According to the structure of the seventh embodiment, A acts as a potential barrier between the source and the drain.
The 1-GaAs Schottky layer has a two-stage structure (71).
With two layers and 713 to 718 layers), the sheet resistance in this portion is reduced. Immediately below the gate Schottky, when forming the second recess, the AlGaAs layer 710 is formed.
ΦB which is effective for Schottky layer formation because the layer is shaved
Takes a value of Al _0.2 Ga _0.8 As. As a result, 0.
15 Ω · mm on-resistance is reduced.

[0069]

According to the present invention, InGaAs or Ga
A channel layer composed of As, a first AlGaAs layer,
An AlGaAs / GaAs superlattice layer, a GaAs layer, a second AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode are sequentially laminated, and further formed in the second AlGaAs layer and the cap layer. A first recess formed in the first recess and in the AlGaAs / GaAs superlattice layer and the GaAs.
Since the field effect transistor was configured to include the second recess formed in the layer and the gate electrode provided in the second recess, an Al layer was formed on the first AlGaAs layer.
A GaAs / GaAs superlattice layer will be laminated,
Thereby, the contact resistance can be reduced.

According to another aspect of the present invention, In
A channel layer composed of GaAs or GaAs, a first AlGaAs layer, an AlGaAs / GaAs superlattice layer,
a first step of sequentially laminating an aAs layer, a second AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode; and, after the first step, a second step is formed in the second AlGaAs layer and the cap layer. A second step of forming the first recess, and following the second step, in the first recess and in the AlGaAs / Ga
A third step of forming a second recess in the As superlattice layer and the GaAs layer; and a fourth step of providing a gate electrode in the second recess after the third step. Because the manufacturing method is configured, the first
The AlGaAs / GaAs superlattice layer is laminated on the AlGaAs layer of the above, so that the contact resistance can be reduced.

More specifically, according to the present invention, first, the Al of the Schottky barrier layer is changed as in the conventional structure.
Providing a superlattice layer between the GaAs rather than a constant GaAs composition as described above lowers the potential barrier and can reduce the contact resistance between the channel and the gate by 0.1 Ω · mm. At this time, since the gate electrode is provided in a portion having a high Al composition, a high φB can be maintained. As a result, the structure of the present invention enables a high-output operation and a high-efficiency operation of the field-effect transistor while maintaining a high reverse breakdown voltage.

Second, the potential barrier is lowered by reducing the AlGaAs composition of the wide recess stopper layer to a two-stage structure instead of the conventional structure as in the conventional structure, thereby reducing the contact resistance between the channel gates by 0.05 Ω · mm. it can. This enables a high-output operation and a high-efficiency operation of the field-effect transistor.

Third, unlike the conventional structure, the composition of the AlGaAs of the wide recess stopper layer is not constant, but a gradient Al composition structure is used as described above to lower the potential barrier and reduce the contact resistance between the channel gates to 0.0.
5 Ω · mm can be reduced. This enables a high-output operation and a high-efficiency operation of the field-effect transistor.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a sectional view of the same embodiment in a manufacturing process.

FIG. 3 is a sectional view of the same embodiment in a manufacturing process.

FIG. 4 is a sectional view of the same embodiment in a manufacturing process.

FIG. 5 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 6 is a sectional view showing a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 8 is a sectional view showing a configuration of a third exemplary embodiment of the present invention.

FIG. 9 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 10 is a sectional view showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 11 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 12 is a sectional view showing a configuration of a fifth exemplary embodiment of the present invention.

FIG. 13 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 14 is a sectional view showing a configuration of a sixth exemplary embodiment of the present invention.

FIG. 15 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 16 is a sectional view showing a configuration of a seventh embodiment of the present invention.

FIG. 17 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 18 is a sectional view of a conventional field-effect transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Substrate 102,103 Buffer layer 104,108 Electron supply layer 105,107 Spacer layer 106 Channel layer 109 Schottky gate contact layer 110 Super lattice layer 111 Undoped GaAs buried layer 112 Wide recess stopper layer 113 Cap layer 114 Gate electrode 115 Source electrode 116 Drain electrode 212 AlGaAs layer 312 to 317 AlGaAs layer 410 AlGaAs layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-188931 (JP, A) JP-A-10-135242 (JP, A) JP-A-5-121451 (JP, A) JP-A-2- 232942 (JP, A) JP-A-10-270463 (JP, A) JP-A-10-56168 (JP, A) JP-A-3-16228 (JP, A) JP-A-9-246531 (JP, A) JP-A-3-256338 (JP, A) JP-A-60-89979 (JP, A) JP-A-8-148873 (JP, A) JP-A-11-251575 (JP, A) (58) (Int.Cl. ⁷ , DB name) H01L 29/778 H01L 21/338 H01L 29/812

Claims (14)

(57) [Claims] 1. A channel layer made of InGaAs or GaAs, and AlGaAs doped with a first n-type impurity.
s layer, AlGaAs / GaAs superlattice layer, GaAs layer,
An AlGaAs layer doped with a second n-type impurity and a cap layer made of InGaAs or GaAs doped with an n-type impurity for an ohmic electrode are sequentially laminated, and the second AlGaAs layer and the second AlGaAs layer; A first recess formed in the cap layer, and in the first recess and in the AlGaAs / GaAs superlattice layer and GaAs.
A field effect transistor comprising: a second recess formed in a layer; and a gate electrode provided in the second recess. 2. A channel layer made of InGaAs or GaAs, and AlGaAs doped with a first n-type impurity.
s layer, GaAs layer, Al doped with a second n-type impurity
GaAs layer, AlGaAs doped with third n-type impurity
InGaAs or GaAs for s layer and ohmic electrode
Are sequentially laminated, and the second
The band gap of the AlGaAs layer is the third AlG
a first recess that is larger than the band gap of the aAs layer and is formed in the second and third AlGaAs layers and the cap layer;
A field effect transistor comprising: a second recess formed in an aAs layer; and a gate electrode provided in the second recess. 3. A channel layer made of InGaAs or GaAs, and AlGaAs doped with a first n-type impurity.
s layer, GaAs layer, Al doped with a second n-type impurity
Doping n-type impurity for GaAs layer and ohmic electrode
And a first recess formed in the second AlGaAs layer and the cap layer, and a first recess formed in the second AlGaAs layer and the cap layer.
Formed in the recess and in the GaAs layer.
And a gate electrode provided in the second recess, and the second AlGaAs layer has an Al composition ratio that increases stepwise from the cap layer toward the GaAs layer.
A field-effect transistor formed of a semiconductor layer composed of a plurality of AlGaAs layers . 4. A channel layer made of InGaAs or GaAs, and AlGaAs doped with a first n-type impurity.
s layer, second AlGaAs layer, GaAs layer, third n-type
AlGaAs layer doped with impurities, fourth n-type impurity
The de - n for up the AlGaAs layer and the ohmic electrode
A cap layer made of InGaAs or GaAs doped with a type impurity, and the first Al
The band gap of the GaAs layer is the second AlGaAs.
The third AlGaAs being larger than the band gap of the layer.
The band gap of the s layer is higher than that of the fourth AlGaAs layer.
And the third and fourth Al
A first recess formed in the GaAs layer and the cap layer; and a second recess formed in the first recess and in the second AlGaAs.
A field effect transistor including a second recess formed in the s layer and the GaAs layer, and a gate electrode provided in the second recess. 5. A channel layer composed of InGaAs or GaAs, AlGaAs doped with a first n-type impurity.
s layer, AlGaAs / GaAs superlattice layer, GaAs layer,
An AlGaAs layer doped with a second n-type impurity ;
n-type impurities de - flop the AlGaAs layer and the n-type impurity to de for ohmic electrode - flop the InGaAs or Ga
Sequentially formed by laminating the formed cap layer in As, the
The band gap of the second AlGaAs layer is equal to that of the third AGaAs layer.
a first recess formed in the second and third AlGaAs layers and the cap layer, the first recess being larger than the band gap of the lGaAs layer, and in the first recess and in the AlGaAs / GaAs superlattice layer and GaAs A field effect transistor comprising: a second recess formed in a layer; and a gate electrode provided in the second recess. 6. A channel layer made of InGaAs or GaAs, and AlGaAs doped with a first n-type impurity.
s layer, second AlGaAs layer, GaAs layer, third n-type
Impurities de - flop the AlGaAs layer and the n-type impurity to de for ohmic electrode - flop the InGaAs or GaAs
And a first recess formed in the third AlGaAs layer and the cap layer, and a first recess formed in the first recess and in the first and second recesses. The third AlGaAs layer includes an AlGaAs layer and a second recess formed in the GaAs layer, and a gate electrode provided in the second recess.
l composition ratio is stepped from the cap layer to the GaAs layer direction.
Semiconductor layer composed of a plurality of AlGaAs layers that rise in height
In field effect transistor being formed. 7. A channel layer made of InGaAs or GaAs, and AlGaAs doped with a first n-type impurity.
s layer, AlGaAs / GaAs superlattice layer, GaAs layer,
An AlGaAs layer doped with a second n-type impurity and a cap layer made of InGaAs or GaAs doped with an n-type impurity for an ohmic electrode are sequentially laminated, and the second AlGaAs layer and the second AlGaAs layer; A first recess formed in the cap layer, and in the first recess and in the AlGaAs / GaAs superlattice layer and GaAs.
A second recess formed in the layer; a gate electrode provided in the second recess;
The GaAs layer has an Al composition ratio from the cap layer to the Ga content.
A plurality of AlGaAs layers gradually increasing in the direction of the As layer
A field-effect transistor formed in a graded structure in which the semiconductor layers are made higher in order. 8. A channel layer made of InGaAs or GaAs, AlGaAs doped with a first n-type impurity.
s layer, AlGaAs / GaAs superlattice layer, GaAs layer,
A first layer in which an AlGaAs layer doped with a second n-type impurity and a cap layer made of InGaAs or GaAs doped with an n-type impurity for an ohmic electrode are sequentially stacked;
Step, and after the first step, the second AlG
a second step of forming a first recess in the aAs layer and the cap layer; and a second step in the first recess and in the AlGaAs / GaAs superlattice layer and the GaAs layer following the second step. A method for manufacturing a field effect transistor, comprising: a third step of forming a recess; and a fourth step of providing a gate electrode in the second recess after the third step. 9. A channel layer made of InGaAs or GaAs, and AlGaAs doped with a first n-type impurity.
s layer, GaAs layer, Al doped with a second n-type impurity
The GaAs layer and the third AlGaAs layer
AlGaAs doped with n-type impurity with small gap
I doped with n-type impurity for s layer and ohmic electrode
a first step of sequentially stacking a cap layer made of nGaAs or GaAs, and a second step of forming a first recess in the second and third AlGaAs layers and the cap layer after the first step. A third step of forming a second recess in the first recess and in the GaAs layer after the second step, and a gate electrode in the second recess after the third step. And providing a fourth step. 10. A channel layer made of InGaAs or GaAs, AlGa doped with a first n-type impurity.
As layer, GaAs layer, A doped with a second n-type impurity
Doping the n-type impurity for the lGaAs layer and the ohmic electrode
A first step of sequentially laminating a cap layer made of InGaAs or GaAs, a second step of forming a first recess in the second AlGaAs layer and the cap layer subsequent to the first step, A third step of forming a second recess in the first recess and in the GaAs layer following the two steps; and providing a gate electrode in the second recess after the third step. 4
And the second AlGaAs layer comprises Al
The composition ratio is stepwise from the cap layer to the GaAs layer.
A method for manufacturing a field-effect transistor, comprising a semiconductor layer composed of a plurality of AlGaAs layers which is gradually increased . 11. A channel layer made of InGaAs or GaAs, and AlGa doped with a first n-type impurity.
An As layer and a bandgap from the second AlGaAs layer.
AlGaAs doped with n-type impurity with small gap
Layer, GaAs layer, AlG doped with a third n-type impurity
aAs layer, fourth band from the third AlGaAs layer
AlGaAs doped with n-type impurity with small gap
In doped with n-type impurities for layers and ohmic electrodes
A first step of sequentially laminating a cap layer made of GaAs or GaAs; and a second step of forming a first recess in the third and fourth AlGaAs layers and the cap layer after the first step. After the second step, in the first recess and in the second AlGaAs
A third step of forming a second recess in the first layer and the GaAs layer; and a fourth step of providing a gate electrode in the second recess after the third step. Manufacturing method. 12. A channel layer made of InGaAs or GaAs, AlGa doped with a first n-type impurity.
As layer, AlGaAs / GaAs superlattice layer, GaAs
Layer, a second n-type impurity doped AlGaAs layer, and a third band gap smaller than the second AlGaAs layer.
A first step of sequentially laminating an AlGaAs layer doped with an n-type impurity and a cap layer composed of InGaAs or GaAs doped with an n-type impurity for an ohmic electrode; 2nd, 3rd A
a second step of forming a first recess in the lGaAs layer and the cap layer; and a second step in the first recess and in the AlGaAs / GaAs superlattice layer and the GaAs layer following the second step. A method for manufacturing a field effect transistor, comprising: a third step of forming a recess; and a fourth step of providing a gate electrode in the second recess after the third step. 13. A channel layer made of InGaAs or GaAs, AlGa doped with a first n-type impurity.
As layer, AlGaAs doped with a second n-type impurity
Layer, GaAs layer, AlG doped with a third n-type impurity
Doping n-type impurities for aAs layer and ohmic electrode
A first step of sequentially laminating a cap layer made of InGaAs or GaAs, a second step of forming a first recess in the third AlGaAs layer and the cap layer after the first step, Subsequent to the second step, in the first recess and in the first and second AlG
a third step of forming a second recess in the aAs layer and the GaAs layer, and a fourth step of providing a gate electrode in the second recess after the third step, and the third AlGaAs The plurality of A layers whose Al composition ratios increase stepwise from the cap layer in the direction of the GaAs layer.
A method for manufacturing a field effect transistor, comprising a semiconductor layer made of an lGaAs layer . 14. A channel layer made of InGaAs or GaAs, and AlGa doped with a first n-type impurity.
As layer, AlGaAs / GaAs superlattice layer, GaAs
Layer, an AlGaAs layer doped with a second n-type impurity, and InGaAs doped with an n-type impurity for an ohmic electrode.
a first step of sequentially laminating a cap layer made of s or GaAs, and the second step after the first step.
a second step of forming a first recess in the IGaAs layer and the cap layer; and a second step in the first recess and in the AlGaAs / GaAs superlattice layer and the GaAs layer following the second step. A third step of forming a recess, a fourth step of providing a gate electrode in the second recess subsequent to the third step, and
The plurality of AlGaAs layers whose Al composition ratios increase stepwise from the cap layer in the direction of the GaAs layer.
A method for manufacturing a field-effect transistor, comprising a semiconductor layer made of an s layer .