JP5666992B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a field effect transistor made of a semiconductor having a wurtzite crystal structure such as a nitride semiconductor and a method for manufacturing the same.

  Nitride semiconductors, semiconductors with a wurtzite crystal structure, have wide gaps, high breakdown electrolysis, high saturation electron velocities, and thermal stability, and are suitable for high-temperature, high-power, high-frequency field effect transistors. Applications are expected and development is underway. For example, a field effect type comprising a buffer layer, a barrier layer formed thereon, a gate electrode formed on the barrier layer, and a source electrode and a drain electrode formed on the barrier layer with the gate electrode interposed therebetween There is a transistor.

  In order to increase the speed and output of field effect transistors using nitride semiconductors, it is effective to make the band gap energy of the barrier layer wider, and to reduce the conduction band offset with the buffer layer. It is effective to increase. As a result, the leakage current of the field effect transistor can be reduced and the breakdown voltage can be improved.

  Furthermore, in a wurtzite crystal grown in the C-axis direction such as a nitride semiconductor, as is well known, polarization charges are generated at the interface of the heterostructure due to the polarity of the crystal in the C-axis direction. In the case of a nitride semiconductor, the polarization charge usually increases with the wide band gap energy. Therefore, by using a wider-gap barrier layer, the concentration of the two-dimensional electron gas at the heterointerface with the buffer layer increases, and it can be expected that the on-resistance of the field-effect transistor is reduced and the mutual conductance is improved.

  For example, in a field effect transistor using a nitride semiconductor, an AlGaN / GaN heterostructure composed of AlGaN as a barrier layer and GaN as a buffer layer is used, but the AlGaN barrier layer increases the Al composition. The band gap widens and the conduction band offset increases. Therefore, by using a barrier layer made of AlGaN having a high Al composition, it is possible to reduce the leakage current as described above, improve the breakdown voltage, and increase the two-dimensional electron gas concentration.

  For example, it is shown that high-speed operation is possible by using high Al composition AlGaN having an Al composition of 0.4 or more (see Non-Patent Document 1). Also, when InAlN having an In composition in the range of about 0.22 to 0.13 is used as the barrier layer, the InAlN / GaN heterostructure has a small lattice mismatch with GaN, a large spontaneous polarization charge, and a conduction with GaN. There are advantages such as a large band offset. As a result, by using InAlN having the above-described composition as a barrier layer, it can be expected that the performance of the field effect transistor is improved more effectively than the high Al composition AlGaN barrier layer (see Non-Patent Document 2).

  However, as the barrier layer becomes wider and the conduction band offset increases, there arises a problem that the contact resistance between the source electrode and the drain electrode increases. This problem is due to an increase in potential barrier height between the electrode and the semiconductor layer. Usually, in a nitride semiconductor, an electrode for ohmic connection is formed by heat-treating a Ti / Al-based metal multilayer film in the range of 600 to 900 ° C.

  The formation of the ohmic connection is characterized in that Ti sucks out N atoms of the nitride semiconductor by heat treatment, and high concentration nitrogen vacancies are formed on the contact surface of the nitride semiconductor. Since this nitrogen vacancy forms a shallow donor level, a high concentration of donor is formed on the contact surface between the nitride semiconductor and the electrode. Tunnel current is promoted by band bending of the semiconductor surface by this high-concentration donor, and the contact resistance between the nitride semiconductor and the electrode can be reduced.

  However, since a semiconductor having a wide gap and a high conduction band potential has a strong atomic bonding force, the desorption of N atoms is suppressed even when the heat treatment as described above is performed. For this reason, the tunnel current due to band bending is suppressed, and it becomes difficult to reduce the contact resistance with the electrode.

  Hereinafter, the above-described problem will be described by taking a field effect transistor using a general AlGaN / GaN heterostructure as an example. FIG. 10 is a cross-sectional view (a) schematically showing the configuration of the field effect transistor, and band diagrams (b) and (c) showing changes in the band potential in the stacking direction of the layers. This field effect transistor includes a buffer layer 1002 made of GaN formed on a substrate 1001, a barrier layer 1003 made of AlGaN formed thereon, and a gate electrode 1004 formed on the barrier layer 1003. , A source electrode 1005 and a drain electrode 1006 formed on the barrier layer 1003 with the gate electrode 1004 interposed therebetween.

In this field effect transistor, FIG. 10B is a band diagram when the barrier layer 1003 is made of Al _0.2 Ga _0.8 N, and FIG. 10C is a band diagram of the barrier layer 1003 made of Al _0.4 Ga _0.6. It is a band figure at the time of comprising from N. These band diagrams show band potentials of the barrier layer 1003 and the buffer layer 1002 on the substrate side viewed from the source electrode and the drain electrode which are ohmic electrodes.

When the Al composition is as low as 0.2, as shown in FIG. 10B, the barrier height on the surface of the barrier layer 1003 (left end in the figure) is low. Furthermore, in this case, an n ⁺ layer is formed by nitrogen vacancies in the vicinity of the interface with the electrode, and the band in the vicinity of the interface is greatly bent. As a result, electrons can easily tunnel through the ohmic electrode and the semiconductor (barrier layer 1003) and low contact resistance can be obtained.

  On the other hand, when the Al composition is as high as 0.4 and the barrier layer 1003 has a wide gap, as shown in FIG. 10C, the barrier height on the surface of the barrier layer 1003 (left end in the figure) becomes high. Furthermore, since the donor concentration in the vicinity of the interface with the electrode is also low, band bending is small. As a result, the tunneling probability of electrons between the ohmic electrode and the semiconductor decreases, and the contact resistance increases.

  As described above, when the barrier layer has a wide gap, the contact resistance with the electrode to be ohmic-connected increases. To reduce this contact resistance, for example, doping is performed on the barrier layer. It is conceivable to form a cap layer and to form an electrode on the cap layer. This technique is effective when the Al composition of the barrier layer made of AlGaN is not so high as about 0.3.

For example, in the field effect transistor described in Non-Patent Document 3, a cap layer made of n ⁺ -GaN is formed on the barrier layer, and recess etching is performed on the cap layer, and the recess portion is formed on the barrier layer. A gate electrode is formed. By using the cap layer in this way, the contact resistance with the source / drain electrodes formed on the cap layer is reduced, and a high mutual conductance is obtained.

  However, when the band gap energy of the barrier layer is larger, the conduction band offset between the cap layer and the barrier layer is increased, and it is considered that an ohmic junction can be obtained by the resulting barrier.

  Even if the surface of the barrier layer is directly doped, the impurity donor level becomes deep and the activation rate is reduced, so that the effect of reducing the contact resistance is hardly obtained even if doping is performed. For example, as described in Non-Patent Document 4, the activation energy of AlGaN increases rapidly when the Al composition is 0.5 or more. InAlN is also considered to have high activation energy.

  Hereinafter, the field effect transistor disclosed in Non-Patent Document 3 will be described as an example. FIG. 11 is a cross-sectional view (a) schematically showing the configuration of a field effect transistor using a cap layer, and band diagrams (b) and (c) showing changes in band potential in the stacking direction of the layers.

This field effect transistor includes a buffer layer 1102 made of GaN formed on a substrate 1101, a barrier layer 1103 made of undoped AlGaN formed thereon, and an n-type AlGaN formed thereon. An n-type barrier layer 1104, a gate electrode 1105 formed on the n-type barrier layer 1104, and two caps made of n ⁺ -GaN formed on the n-type barrier layer 1104 with the gate electrode 1105 interposed therebetween A layer 1106 and a source electrode 1107 and a drain electrode 1108 formed on each cap layer 1106 are provided.

The n-type barrier layer 1104 has an impurity concentration of 5 × 10 ¹⁸ cm ^−2, and the cap layer 1106 has an n-type impurity concentration of 1 × 10 ¹⁹ cm ⁻² . The barrier layer 1103 has a thickness of 5 nm, the n-type barrier layer 1104 has a thickness of 20 nm, and the cap layer 1106 has a thickness of 20 nm.

In this field effect transistor, FIG. 11B is a band diagram in the case where each barrier layer is formed from Al _0.2 Ga _0.8 N, and FIG. 11C is a band diagram obtained from Al _0.4 Ga _0.6 N. It is a band figure at the time of comprising a layer. These band diagrams show the band potentials of the cap layer 1106, the barrier layer 1103, and the buffer layer 1102 on the substrate side as viewed from the source electrode and the drain electrode that are ohmic electrodes.

  When the Al composition is as low as about 0.2, the barrier height of the cap layer 1106 lower than the n-type barrier layer 1104 and the barrier layer 1103, and the doping of the cap layer 1106, as shown in FIG. Due to the effect, the contact resistance with each electrode can be reduced.

  On the other hand, when the Al composition is 0.4 and each barrier layer has a wide gap, as shown in FIG. 11C, a good ohmic junction is obtained between each electrode to be ohmic-connected and the cap layer 1106. It is done. However, due to the increase in the conduction band offset between the cap layer 1106 and the n-type barrier layer 1104 and the difference in polarization charge, a high barrier is formed at the interface between the cap layer 1106 and the n-type barrier layer 1104. For this reason, the electrical conductivity between the two-dimensional electron gas and the ohmic electrode is lowered, and as a result, the contact resistance is increased.

M.Higashiwaki and T.Matsui, "AlGaN / GaN Heterostructure Field-Effect Transistors with Current Gain Cut-off Frequency of 152 GHz on Sapphire Substrates", Japanese Journal of Applied Physics, Vol.44, No.16, pp.L475- L478, 2005. J. Kuzmik, "Power Electronics on InAlN / (In) GaN: Prospect for a Record Performance", IEEE ELECTRON DEVICE LETTERS, VOL.22, NO.11, pp.510-512, 2001. H. Okita et al., "High transconductance AlGaN / GaN-HEMT with recessed gate on sapphire substrate", phys.stat.sol. (A), vol.200, No.1, pp.187-190, 2003. Y.Taniyasu et al., "Intentional control of n-type conduction for Si-doped AlN and AlXGa1AXN (0.42 ≦ x <1)", APPLIED PHYSICS LETTERS, vol.81, no.7, pp.1255-1257, 2002 .

  As described above, in a field effect transistor using a semiconductor having a wurtzite crystal structure such as a nitride semiconductor, the barrier layer is made of a semiconductor having a larger band gap energy, thereby reducing leakage current and withstand voltage. Improvements in performance can be expected, such as improvement in resistance, reduction in on-resistance, and improvement in transconductance. However, when the barrier layer is made of a semiconductor having a larger band gap energy, there arises a problem that the contact resistance between the source / drain electrodes is increased.

  The present invention has been made to solve the above problems, and is a field effect transistor using a semiconductor having a wurtzite crystal structure, and without increasing the contact resistance with the electrode, the band gap. It is an object of the present invention to make it possible to construct a barrier layer from a semiconductor having higher energy.

The field effect transistor according to the present invention includes a buffer layer made of a semiconductor having a wurtzite crystal structure formed on a substrate by crystal growth in the C-axis direction, and a buffer layer by crystal growth in the C-axis direction. A barrier layer made of an undoped semiconductor having a wurtzite crystal structure formed on the gate electrode, and a gate electrode formed on the barrier layer are separated from each other across the gate electrode by crystal growth in the C-axis direction. Two current tunnel layers made of a semiconductor having a wurtzite crystal structure formed in contact with the barrier layer, and a wurtzite type formed on each current tunnel layer by crystal growth in the C-axis direction. At least two cap layers made of a semiconductor having a crystal structure, a source electrode formed on one cap layer, and a drain electrode formed on the other cap layer, the conduction band potential of the barrier layer Le is higher than the conduction band potential of the buffer layer, the conduction band potential of the cap layer is lower than the conduction band potential of the barrier layer, polarization charges of the current tunnel layer is greater than the polarization charge of the barrier layer.

  In the field effect transistor, the cap layer may be n-type. The semiconductor may be a nitride semiconductor. For example, the buffer layer is composed of a nitride semiconductor selected from GaN and GaInN, and the barrier layer is selected from AlN, AlGaN, AlInN, and AlGaInN and has a composition with a higher conduction band potential than the buffer layer. The current tunnel layer is composed of a nitride semiconductor selected from AlN, AlGaN, AlInN, and AlGaInN and has a composition having a polarization charge larger than that of the barrier layer, and the cap layer is composed of GaN, AlGaN, It may be made of a nitride semiconductor selected from AlGaInN and GaInN and having a composition having a conduction band potential lower than that of the barrier layer.

The field effect transistor manufacturing method according to the present invention includes a step of forming a buffer layer made of a semiconductor having a wurtzite crystal structure on a substrate by crystal growth in the C-axis direction, and a crystal in the C-axis direction. A step of forming a barrier layer made of an undoped semiconductor having a wurtzite crystal structure on the buffer layer, and a crystal growth in the C-axis direction so as to be in contact with the barrier layer to form a wurtzite crystal structure. A step of forming a current tunnel layer made of a semiconductor, a step of forming a cap layer made of a semiconductor having a wurtzite crystal structure on the current tunnel layer by crystal growth in the C-axis direction, and the cap layer and the current tunnel layer Forming a trench on the barrier layer to form two current tunnel layers and two cap layers, and forming a gate electrode on the barrier layer between the two current tunnel layers And a step of forming a source electrode on one cap layer and a drain electrode on the other cap layer, and the barrier layer is made of a semiconductor having a higher conduction band potential than the buffer layer The cap layer is made of a semiconductor having a conduction band potential lower than that of the barrier layer, and the current tunnel layer is made of a semiconductor having a polarization charge larger than that of the barrier layer.

In addition, another field effect transistor manufacturing method according to the present invention includes a step of forming a buffer layer made of a semiconductor having a wurtzite crystal structure on a substrate by crystal growth in the C-axis direction, and a C-axis direction. A step of forming a barrier layer made of an undoped semiconductor having a wurtzite crystal structure on the buffer layer, and a step of forming a selective growth mask in the gate electrode formation region on the barrier layer; A step of forming two current tunnel layers made of a semiconductor having a wurtzite crystal structure in contact with the barrier layer by selectively growing crystals in the C-axis direction on the barrier layer not covered with the growth mask. And a step of forming two cap layers made of a semiconductor having a wurtzite crystal structure on each current tunnel layer by crystal growth in the C-axis direction, and removing the selective growth mask after the cap layer is formed. You At least a step of forming a gate electrode in a gate electrode formation region on the barrier layer, a step of forming a source electrode on one cap layer, and a drain electrode on the other cap layer. The barrier layer is made of a semiconductor having a conduction band potential higher than that of the buffer layer, the cap layer is made of a semiconductor having a conduction band potential lower than that of the barrier layer, and the current tunnel layer has a polarization charge higher than that of the barrier layer. Consists of large semiconductors.

  As described above, according to the present invention, since the current tunnel layer having a polarization charge larger than that of the barrier layer is provided between the barrier layer and the cap layer, the electric field using the semiconductor having the wurtzite crystal structure is used. In the effect transistor, it is possible to obtain an excellent effect that the barrier layer can be made of a semiconductor having a larger band gap energy without increasing the contact resistance with the electrode.

FIG. 1 is a cross-sectional view (a) schematically showing the configuration of the field effect transistor according to Embodiment 1 of the present invention and a band diagram (b) showing a change in band potential in the stacking direction of each layer. FIG. 2 is a cross-sectional view (a) schematically showing a configuration of a general nitride semiconductor field effect transistor and a band diagram (b) showing a change in band potential of each layer in the stacking direction. FIG. 3 is a band diagram showing a change in band potential in the stacking direction of each layer of the field effect transistor according to Embodiment 1 of the present invention. FIG. 4 shows a band diagram (a) showing a change in band potential in the stacking direction of each layer of the field effect transistor according to the first embodiment of the present invention, and a stack of each layer of the field effect transistor not using the current tunnel layer. It is a band figure (b) which shows the change of the band potential of a direction. FIG. 5 is a cross-sectional view schematically showing the configuration of the field effect transistor according to Embodiment 2 of the present invention. FIG. 6 is a cross-sectional view schematically showing the configuration of the field effect transistor according to Embodiment 3 of the present invention. FIG. 7 is a cross-sectional view schematically showing a configuration of a field effect transistor according to Embodiment 4 of the present invention. FIG. 8A is a cross-sectional view schematically showing a state in each step for describing Field Method Transistor Manufacturing Method Example 1 in the embodiment of the present invention. FIG. 8B is a cross-sectional view schematically showing a state in each step for explaining the manufacturing method example 1 of the field effect transistor in the embodiment of the present invention. FIG. 8C is a cross-sectional view schematically showing a state in each step for explaining the manufacturing method example 1 of the field effect transistor in the embodiment of the present invention. FIG. 8D is a cross-sectional view schematically showing a state in each step for explaining the manufacturing method example 1 of the field effect transistor in the embodiment of the present invention. FIG. 8E is a cross-sectional view schematically showing a state in each step for explaining the manufacturing method example 1 of the field effect transistor in the embodiment of the present invention. FIG. 8F is a cross-sectional view schematically showing a state in each step for explaining the manufacturing method example 1 of the field effect transistor in the embodiment of the present invention. FIG. 8G is a cross-sectional view schematically showing a state in each step for explaining the manufacturing method example 1 of the field effect transistor in the embodiment of the present invention. FIG. 9A is a cross-sectional view schematically showing a state in each step for explaining a field effect transistor manufacturing method example 2 in the embodiment of the present invention. FIG. 9B is a cross-sectional view schematically showing the state in each step for explaining the manufacturing method example 2 of the field effect transistor according to the embodiment of the present invention. FIG. 9C is a cross-sectional view schematically showing a state in each step for explaining the manufacturing method example 2 of the field effect transistor in the embodiment of the present invention. FIG. 9D is a cross-sectional view schematically showing a state in each step for explaining a field effect transistor manufacturing method example 2 in the embodiment of the present invention. FIG. 10 is a cross-sectional view (a) schematically showing the configuration of a field effect transistor, and band diagrams (b) and (c) showing changes in band potential in the stacking direction of the layers. FIG. 11 is a cross-sectional view (a) schematically showing the configuration of a field effect transistor using a cap layer, and band diagrams (b) and (c) showing changes in band potential in the stacking direction of the layers.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view (a) schematically showing the configuration of the field effect transistor according to Embodiment 1 of the present invention and a band diagram (b) showing a change in band potential in the stacking direction of each layer.

  In this field effect transistor, each layer made of a semiconductor is composed of a semiconductor having a wurtzite crystal structure formed on the substrate 101 by crystal growth in the C-axis <0001> direction. First, the buffer layer 102 and the barrier layer 103 are stacked from the substrate 101 side. A gate electrode 104 is formed on the barrier layer 103. The gate electrode 104 is formed, for example, by Schottky connection to the barrier layer 103.

  The field effect transistor is formed on two current tunnel layers 105 formed on and in contact with the barrier layer 103 while being spaced apart from each other with the gate electrode 104 interposed therebetween. Two cap layers 106. The source electrode 107 is formed on one cap layer 106, and the drain electrode 108 is formed on the other cap layer 106.

  In addition, in the field-effect transistor in this embodiment, the conduction band potential of the barrier layer 103 is higher than the conduction band potential of the buffer layer 102, and the conduction band potential of the cap layer 106 is higher than the conduction band potential of the barrier layer 103. The polarization charge of the current tunnel layer 105 is lower than that of the barrier layer 103.

For example, the buffer layer 102 is made of GaN. The barrier layer 103 is made of undoped Al _0.4 Ga _0.6 N and has a thickness of about 25 nm. The current tunnel layer 105 is made of AlN and has a thickness of about 1 nm. The cap layer 106 is made of AlGaN (n ⁺ -AlGaN) doped with n-type impurities of about 1 × 10 ¹⁹ cm ⁻² and has a thickness of about 20 nm.

  The gate electrode 104 may be formed of a Ni / Au metal laminated film. The source electrode 107 and the drain electrode 108 may be made of a Ti / Al / Ni / Au metal multilayer film. The shape of each electrode may be formed by a well-known lift-off method. After forming the shape of each electrode, an ohmic connection state is obtained by heat treatment at 850 ° C.

  According to the first embodiment, since the polarization charge of the current tunnel layer 105 is larger than that of the barrier layer 103, the potential of the barrier layer 103 at these interfaces is lowered as shown in FIG. As a result, the effective conduction band offset between the barrier layer 103 and the cap layer 106 is reduced. In addition, the current tunnel layer 105 functions with a layer thickness of about 1 nm, but if it is thin like this, electrons can pass by tunneling. Needless to say, a good ohmic junction is formed between the source electrode 107 and the drain electrode 108 and the cap layer 106. As a result, it is possible to obtain a low contact resistance between the source electrode 107 and the drain electrode 108 even if the barrier layer 103 is formed from a semiconductor having a wide gap with a larger band gap energy.

  Here, for comparison, a field effect transistor that does not use the current tunnel layer 105 will be described. FIG. 2 is a cross-sectional view (a) schematically showing a configuration of a general nitride semiconductor field effect transistor and a band diagram (b) showing a change in band potential of each layer in the stacking direction.

In this field effect transistor, a buffer layer 202 and a barrier layer 203 are stacked from the substrate 201 side. A gate electrode 204 is formed on the barrier layer 203. In addition, two cap layers 206 are formed in contact with each other on the barrier layer 203 with the gate electrode 204 interposed therebetween, and a source electrode 207 and a drain electrode 208 are formed on each cap layer 206. ing. This field effect transistor is the same as that of the first embodiment except that no current tunnel layer is used, and the barrier layer 203 is made of Al _0.4 Ga _0.6 N having a wide gap.

  In this field effect transistor, as shown in FIG. 2B, due to the influence of the conduction band offset between the barrier layer 203 and the cap layer 206 and the difference in polarization charge, a high potential barrier is formed at these interfaces. The For this reason, the contact resistance of the ohmic electrode is increased. As a result, unlike the first embodiment described above, a low contact resistance cannot be obtained between the source and drain electrodes 207 and 208 and the barrier layer 203.

  As described above, in this embodiment, since the current tunnel layer having a polarization charge larger than that of the barrier layer is used, the field effect transistor using the semiconductor having the wurtzite crystal structure is used to contact the electrode. Without increasing the resistance, the barrier layer can be formed from a semiconductor having a larger band gap energy.

By the way, the current tunnel layer 105 only needs to have a polarization charge larger than that of the barrier layer 103, and the current tunnel layer 105 is not limited to being composed of AlN in contrast to the barrier layer 103 composed of AlGaN. For example, when the barrier layer 103 is made of Al _0.4 Ga _0.6 N, the current tunnel layer 105 may be made of In _0.1 Al _0.9 N.

  In this case, as shown in FIG. 3A, the effective conduction band offset between the barrier layer 103 and the cap layer 106 can be reduced as described above, and the contact resistance can be reduced. However, the effect is small compared to the case where the current tunnel layer 105 is made of AlN.

Further, the effective conduction band offset can be further reduced by adjusting the composition of n ⁺ -AlGaN constituting the cap layer 106. For example, by forming the cap layer 106 from n ⁺ -Al _0.3 Ga _0.7 N having a high Al composition, the effective band offset can be further reduced as shown in FIG. It is possible to reduce the contact resistance by making the conduction band potential between the electrodes substantially flat.

Further, the barrier layer 103 is not limited to AlGaN having a high Al composition, but may be composed of InAlAs. For example, the buffer layer 102 is made of GaN, the barrier layer 103 is made of undoped In _0.17 Al _0.83 N to a thickness of 25 nm, the current tunnel layer 105 is made of AlN to a thickness of 1 nm, and the cap layer 106 May be made of Al _0.3 Ga _0.7 N (n ⁺ -AlGaN) doped with n-type impurities of about 1 × 10 ¹⁹ cm ⁻² to have a layer thickness of about 20 nm. FIG. 4A is a band diagram showing a change in band potential in the stacking direction of each layer in the first embodiment configured as described above.

Here, for comparison, a band diagram showing a change in band potential in the stacking direction of each layer in a field effect transistor having the same configuration as described above except that no current tunnel layer is used is shown in FIG. ). As shown in FIG. 4B, the barrier layer 203 made of In _0.17 Al _0.83 N with an In composition of 0.17 has a conduction band potential higher than that of Al _0.4 Ga _0.6 N and a large polarization charge. For this reason, a larger potential barrier is generated at the interface between the cap layer 206 and the barrier layer 203, and the contact resistance is further increased.

  On the other hand, by providing the current tunnel layer 105, as shown in FIG. 4A, between the cap layer 106 and the barrier layer 103, the effective conduction band offset between them is reduced. The contact resistance can be reduced.

[Embodiment 2]
Next, Embodiment 2 of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view schematically showing the configuration of the field effect transistor according to Embodiment 2 of the present invention. In this field effect transistor, each layer made of a semiconductor is composed of a semiconductor having a wurtzite crystal structure formed on a substrate 501 by crystal growth in the C-axis direction. First, the buffer layer 502 and the barrier layer 503 are stacked from the substrate 501 side. A gate electrode 504 is formed on the barrier layer 503. The gate electrode 504 is formed by Schottky connection to the barrier layer 503, for example.

  The field effect transistor is formed on two current tunnel layers 505 formed on and in contact with the barrier layer 503 with the gate electrode 504 interposed therebetween, and on each current tunnel layer 505. Two cap layers 506. The source electrode 507 is formed on one cap layer 506, and the drain electrode 508 is formed on the other cap layer 506.

  In the field-effect transistor in Embodiment 2, the conduction band potential of the barrier layer 503 is higher than the conduction band potential of the buffer layer 502, and the conduction band potential of the cap layer 506 is lower than the conduction band potential of the barrier layer 503. The polarization charge of the current tunnel layer 505 is larger than the polarization charge of the barrier layer 503.

  The configuration described above is the same as that of the first embodiment described above, and in the second embodiment, an intermediate layer 509 is newly provided between the buffer layer 502 and the barrier layer 503 in order to improve electron mobility. Yes.

For example, the buffer layer 502 is made of GaN, the barrier layer 503 is made of undoped Al _0.4 Ga _0.6 N and has a thickness of about 25 nm, and the current tunnel layer 505 is made of AlN and has a thickness of about 1 nm. The cap layer 506 may be made of AlGaN doped with n-type impurities of about 1 × 10 ¹⁹ cm ⁻² to have a layer thickness of about 20 nm. In the above structure, the intermediate layer 509 may be made of AlN or AlGaN.

  Also in the second embodiment, since the polarization charge of the current tunnel layer 505 is larger than that of the barrier layer 503, the effective conduction band offset between the barrier layer 503 and the cap layer 506 is reduced. Further, since the current tunnel layer 505 is as thin as about 1 nm, electrons can pass through by tunneling. In addition, a good ohmic junction is formed between the source electrode 507 and the drain electrode 508 and the cap layer 506. As a result, a low contact resistance can be obtained between the source electrode 507 and the drain electrode 508 even if the barrier layer 503 is formed from a semiconductor having a wide gap with a larger band gap energy. In addition to these, since the intermediate layer 509 is used in Embodiment 2, the electron mobility can be improved.

[Embodiment 3]
Next, Embodiment 3 of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view schematically showing the configuration of the field effect transistor according to Embodiment 3 of the present invention. In this field effect transistor, each layer made of a semiconductor is composed of a semiconductor having a wurtzite crystal structure formed on the substrate 101 by crystal growth in the C-axis direction. First, the buffer layer 102 and the barrier layer 103 are stacked from the substrate 101 side. A gate electrode 104 is formed on the barrier layer 103.

  The field effect transistor is formed on two current tunnel layers 105 formed on and in contact with the barrier layer 103 while being spaced apart from each other with the gate electrode 104 interposed therebetween. Two cap layers 106. The source electrode 107 is formed on one cap layer 106, and the drain electrode 108 is formed on the other cap layer 106.

  In the field-effect transistor in Embodiment 3, the conduction band potential of the barrier layer 103 is higher than the conduction band potential of the buffer layer 102, and the conduction band potential of the cap layer 106 is lower than the conduction band potential of the barrier layer 103. The polarization charge of the current tunnel layer 105 is larger than the polarization charge of the barrier layer 103.

The configuration described above is the same as that of the first embodiment described above. In the third embodiment, the gate electrode 104 is formed over the barrier layer 103 with the gate insulating layer 601 interposed therebetween. The gate insulating layer 601 may be made of, for example, silicon nitride (Si ₃ N ₄ ). The gate insulating layer 601 may be made of silicon oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ ). Thus, the present invention is also effective in a so-called MIS structure. Note that the gate insulating layer 601 may be formed only in a region below the gate electrode 104, or may extend to a part of the cap layer 106 as shown in FIG.

[Embodiment 4]
Next, Embodiment 4 of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view schematically showing a configuration of a field effect transistor according to Embodiment 4 of the present invention. In this field effect transistor, each layer made of a semiconductor is composed of a semiconductor having a wurtzite crystal structure formed on a substrate 701 by crystal growth in the C-axis direction. First, a buffer layer 702 and a barrier layer 703 are stacked from the substrate 701 side. A gate electrode 704 is formed on the barrier layer 703. The gate electrode 704 is formed by Schottky connection to the barrier layer 703, for example.

  The field effect transistor is formed on two current tunnel layers 705 formed on and in contact with the barrier layer 703 with the gate electrode 704 interposed therebetween, and on each current tunnel layer 705. Two cap layers 706. The source electrode 707 is formed on one cap layer 706, and the drain electrode 708 is formed on the other cap layer 706.

  In the field-effect transistor in Embodiment 4, the conduction band potential of the barrier layer 703 is higher than the conduction band potential of the buffer layer 702, and the conduction band potential of the cap layer 706 is lower than the conduction band potential of the barrier layer 703. The polarization charge of the current tunnel layer 705 is larger than the polarization charge of the barrier layer 703.

  The configuration described above is the same as that in the first embodiment described above. In the fourth embodiment, a channel layer 710 in which a two-dimensional electron gas is formed is newly provided between the buffer layer 702 and the barrier layer 703. Yes.

For example, the buffer layer 702 is made of GaN, the channel layer 710 is made of InGaN, the barrier layer 703 is made of undoped Al _0.4 Ga _0.6 N and has a layer thickness of about 25 nm, and the current tunnel layer 705 is The cap layer 706 may be made of AlGaN (n ⁺ -AlGaN) doped with n-type impurities of about 1 × 10 ¹⁹ cm ⁻² and may have a layer thickness of about 20 nm. . In the above structure, the intermediate layer 709 may be made of AlN or AlGaN.

  Thus, the layer in which the two-dimensional electron gas is formed may be made of other materials such as InGaN instead of GaN.

  In the present invention, it is important to satisfy the condition that the conduction band potential of the cap layer is lower than that of the barrier layer, and the polarization charge of the current tunnel layer is larger than that of the barrier layer. There is no restriction on the layer structure. The present invention is effective regardless of the material of the current tunnel layer and the material of the cap layer. The present invention is effective in the range where the thickness of the tunnel layer and the cap layer is one atomic layer (approximately 0.3 nm) or more and smaller than the critical thickness.

[Production Method Example 1]
Next, a method 1 for manufacturing a field effect transistor according to the embodiment of the present invention will be described with reference to FIGS. 8A to 8G. 8A to 8G are cross-sectional views schematically showing states in respective steps for explaining a field effect transistor manufacturing method example 1 in the embodiment of the present invention.

First, as shown in FIG. 8A, on a substrate 101, a buffer layer 102 made of GaN, a barrier layer 103 made of undoped Al _0.4 Ga _0.6 N, a current tunnel layer 105 made of AlN, and a cap made of n ⁺ -AlGaN. Layer 106 is sequentially formed by well-known epitaxial growth techniques. Epitaxial growth is performed in the C-axis direction. Examples of the epitaxial growth method include a molecular beam epitaxy (MBE) method and a metal-organic vapor-phase epitaxy (Metal-Organic Vapor-Phase Epitaxy) method. Further, each of the stacked layers is patterned by a known lithography technique and dry etching technique to form a mesa structure.

  Here, the barrier layer 103 is made of a semiconductor having a conduction band potential higher than that of the buffer layer 102, the cap layer 106 is made of a semiconductor having a conduction band potential lower than that of the barrier layer 103, and the current tunnel layer 105 is made of a barrier. It is important that the layer 103 is made of a semiconductor having a polarization charge larger than that of the layer 103.

  Next, as shown in FIG. 8B, a source electrode 107 and a drain electrode 108 are formed on the cap layer 106 with a predetermined interval, for example, by a known lift-off method.

  Next, as shown in FIG. 8C, a resist pattern 801 having an opening 802 in a gate electrode formation region is formed by applying a photoresist to form a coating film and exposing and developing the coating film. Is formed on the cap layer 106. In the opening 802, the cap layer 106 is exposed. In other words, the opening 802 is formed so as to penetrate to the cap layer 106.

  Next, using the resist pattern 801 as a mask, the cap layer 106, the current tunnel layer 105, and a part of the barrier layer 103 are selectively etched to form a recess structure (groove) as shown in FIG. 8D.

  Next, after removing the resist pattern 801, the gate electrode 104 is formed on the barrier layer 103 between the source electrode 107 and the drain electrode 108 as shown in FIG. A field effect transistor is provided. Note that a recess structure may be formed before the source electrode 107 and the drain electrode 108 are formed.

  Moreover, it is good also as a MIS structure by showing below. First, a recess structure is formed in the cap layer 106 and the current tunnel layer 105 in the same manner as described with reference to FIGS. 8A to 8D. Next, as illustrated in FIG. 8F, the gate insulating layer 601 is formed over the barrier layer 103 between the source electrode 107 and the drain electrode 108.

  After the gate insulating layer 601 is formed as described above, the gate electrode 104 is formed on the gate insulating layer 601 between the source electrode 107 and the drain electrode 108 as shown in FIG. A field effect transistor including the tunnel layer 105 is obtained.

[Production Method Example 2]
Next, Method Example 2 of manufacturing a field effect transistor in the embodiment of the present invention will be described with reference to FIGS. 9A to 9D. 9A to 9D are cross-sectional views schematically showing states in respective steps for explaining a field effect transistor manufacturing method example 2 in the embodiment of the present invention.

First, as shown in FIG. 9A, a buffer layer 102 made of GaN and a barrier layer 103 made of undoped Al _0.4 Ga _0.6 N are sequentially formed on a substrate 101 by a well-known epitaxial growth technique. Next, as shown in FIG. 9B, a selective growth mask 901 covering the gate electrode formation region is formed. For example, the selective growth mask 901 can be formed by forming a silicon oxide film by a well-known sputtering method and patterning the silicon oxide film by a known photolithography and etching technique.

Next, as shown in FIG. 9C, the well-known epitaxial growth of the current tunnel layer 105 made of AlN and the cap layer 106 made of n ⁺ -AlGaN on the barrier layer 103 other than the formation region of the selective growth mask 901 is performed. Sequentially formed by selective growth by technology. Thereafter, if the selective growth mask 901 is removed, a recess structure can be formed in the current tunnel layer 105 and the cap layer 106 as shown in FIG. 9D. During the selective growth, before forming the current tunnel layer 105, undoped Al _0.4 Ga _0.6 N is deposited on the barrier layer 103 other than the formation region of the selective growth mask 901, and the barrier layer 103 in this region is formed. The thickness of the layer may be increased.

  After forming the recess structure as described above, if the source / drain electrodes are formed on the cap layer 106 and the gate electrode is formed on the barrier layer 103, a field effect transistor including the current tunnel layer 105 is obtained. can get. Also in this manufacturing method example 2, as in the manufacturing method example 1 described above, the gate electrode may be formed after forming the gate insulating layer.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, in the above description, the case of a nitride semiconductor as the semiconductor having a wurtzite crystal structure has been described as an example. However, the present invention is not limited to this. For example, ZnO may be used.

  Moreover, as a nitride semiconductor, the buffer layer should just be comprised from the nitride semiconductor selected from GaN and GaInN. The barrier layer may be made of a nitride semiconductor selected from AlN, AlGaN, AlInN, and AlGaInN and having a composition having a conduction band potential higher than that of the buffer layer. The current tunnel layer may be made of a nitride semiconductor selected from AlN, AlGaN, AlInN, and AlGaInN and having a composition having a polarization charge larger than that of the barrier layer. The cap layer may be made of a nitride semiconductor selected from GaN, AlGaN, AlGaInN, and GaInN and having a composition having a conduction band potential lower than that of the barrier layer.

In the above-described embodiment, the cap layer is n-type by doping Si with 1 × 10 ¹⁹ cm ⁻³ . However, the impurity concentration is not limited to this, and the cap layer may be undoped. . Further, the barrier layer may be composed of an undoped layer and an n-type layer.

  Further, the source electrode and the drain electrode are not limited to Ti / Al / Ni / Au, but may be formed of a multilayer structure of Ti / Al and heat-treated at 600 ° C. Further, it may be formed of a porous structure of Ti / Al / Ti / Au and heat-treated at 800 ° C. Regardless of the metal material, the source electrode and the drain electrode have no influence on the effects of the present invention as long as an ohmic junction is formed with the cap layer.

  The gate electrode is not limited to a Ni / Au metal laminate film, and may be a metal laminate film such as Pt / Au or Pd / Au. When the gate insulating layer is not used, the gate electrode may be made of a material that can form a Schottky junction with the barrier layer. In the case of a MIS structure using a gate insulating layer, the gate electrode can be made of various conductive materials.

  DESCRIPTION OF SYMBOLS 101 ... Substrate, 102 ... Buffer layer, 103 ... Barrier layer, 104 ... Gate electrode, 105 ... Current tunnel layer, 106 ... Cap layer, 107 ... Source electrode, 108 ... Drain electrode.

Claims (6)

A buffer layer made of a semiconductor having a wurtzite crystal structure formed on the substrate by crystal growth in the C-axis direction;
A barrier layer made of an undoped semiconductor having a wurtzite crystal structure formed on the buffer layer by crystal growth in the C-axis direction;
A gate electrode formed on the barrier layer;
Two current tunnel layers made of a semiconductor having a wurtzite crystal structure formed on the barrier layer in contact with each other with the gate electrode interposed therebetween by crystal growth in the C-axis direction;
Two cap layers made of a semiconductor having a wurtzite crystal structure formed on each of the current tunnel layers by crystal growth in the C-axis direction;
A source electrode formed on one of the cap layers;
And at least a drain electrode formed on the other cap layer,
The conduction band potential of the barrier layer is higher than the conduction band potential of the buffer layer;
The conduction band potential of the cap layer is lower than the conduction band potential of the barrier layer,
The field effect transistor according to claim 1, wherein a polarization charge of the current tunnel layer is larger than a polarization charge of the barrier layer. The field effect transistor according to claim 1, wherein
2. The field effect transistor according to claim 1, wherein the cap layer is n-type. The field effect transistor according to claim 1 or 2,
The field effect transistor according to claim 1, wherein the semiconductor is a nitride semiconductor. The field effect transistor according to claim 3, wherein
The buffer layer is made of a nitride semiconductor selected from GaN and GaInN,
The barrier layer is made of a nitride semiconductor selected from AlN, AlGaN, AlInN, and AlGaInN and having a composition having a higher conduction band potential than the buffer layer;
The current tunnel layer is composed of a nitride semiconductor selected from AlN, AlGaN, AlInN, and AlGaInN and having a composition having a polarization charge larger than that of the barrier layer,
The cap layer is composed of a nitride semiconductor selected from GaN, AlGaN, AlGaInN, and GaInN and having a composition having a conduction band potential lower than that of the barrier layer. Forming a buffer layer made of a semiconductor having a wurtzite crystal structure on a substrate by crystal growth in the C-axis direction;
Forming a barrier layer made of an undoped semiconductor having a wurtzite crystal structure on the buffer layer by crystal growth in the C-axis direction;
Forming a current tunnel layer made of a semiconductor having a wurtzite crystal structure in contact with the barrier layer by crystal growth in the C-axis direction;
Forming a cap layer made of a semiconductor having a wurtzite crystal structure on the current tunnel layer by crystal growth in the C-axis direction;
Forming a groove in the cap layer and the current tunnel layer to form two current tunnel layers and two cap layers on the barrier layer;
Forming a gate electrode on the barrier layer between the two current tunnel layers;
Forming a source electrode on one of the cap layers, and forming a drain electrode on the other cap layer,
The barrier layer is made of a semiconductor having a higher conduction band potential than the buffer layer,
The cap layer is made of a semiconductor having a conduction band potential lower than that of the barrier layer,
The method of manufacturing a field effect transistor, wherein the current tunnel layer is made of a semiconductor having a polarization charge larger than that of the barrier layer. Forming a buffer layer made of a semiconductor having a wurtzite crystal structure on a substrate by crystal growth in the C-axis direction;
Forming a barrier layer made of an undoped semiconductor having a wurtzite crystal structure on the buffer layer by crystal growth in the C-axis direction;
Forming a selective growth mask in a gate electrode formation region on the barrier layer;
Two current tunnel layers made of a semiconductor having a wurtzite crystal structure in contact with the barrier layer by selectively growing crystals in the C-axis direction on the barrier layer not covered with the selective growth mask Forming a step;
Forming two cap layers made of a semiconductor having a wurtzite crystal structure on each of the current tunnel layers by crystal growth in the C-axis direction;
Removing the selective growth mask after forming the cap layer;
Forming a gate electrode in the gate electrode formation region on the barrier layer;
Forming a source electrode on one of the cap layers, and forming a drain electrode on the other cap layer,
The barrier layer is made of a semiconductor having a higher conduction band potential than the buffer layer,
The cap layer is made of a semiconductor having a conduction band potential lower than that of the barrier layer,
The method of manufacturing a field effect transistor, wherein the current tunnel layer is made of a semiconductor having a polarization charge larger than that of the barrier layer.

Images