JP3215518B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device. In particular, it relates to improvement of a basic cell of a gate array type semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, a semiconductor integrated circuit device has been generally developed by a gate array system because of a short development period. In this gate array system, a master slice in which basic cells are spread is prepared in advance, and wiring in the basic cells and wiring between the basic cells are performed according to user design data. Thereafter, by performing packaging, a final semiconductor integrated circuit device is manufactured.

FIG. 5 is a plan view showing the structure of an example of a conventional basic cell. The basic cell shown in FIG.
Two NMOS transistors 10, 12 and two P
MOS type transistors 14 and 16 are provided.

[0004] The NMOS transistor 10 comprises a drain 20a, a gate 20b, and a source 20c. Drain 20a and the source 20c is composed of N-type diffusion layer, gate 20b is composed of a gate electrode provided in extended against the upper surface of the N-type diffusion layer side. The N-type diffusion layer and a P-type diffusion layer described later are indicated by hatching in the figure.

The NMOS transistor 12 has a source 2
0d, a gate 20e, and a drain 20f. Source 20d and the drain 20f is composed of N-type diffusion layer, gate 20e is composed of a metal wire provided in extended against the upper surface of the N-type diffusion layer side. The source 20d is the same member as the source 20c. That is, the source 20c of the NMOS transistor 10 is connected to the source 20d of the NMOS transistor 12.
Is connected to

[0006] The PMOS transistor 14 comprises a drain 22a, a gate 22b, and a source 22c. Drain 22a and the source 22c is composed of P-type diffusion layer, gate 22b is composed of a metal wire provided in extended against the upper surface of the P-type diffusion layer side.

The PMOS transistor 16 has a source 2
2d, a gate 22e, and a drain 22f. Source 22d and the drain 22f is composed of P-type diffusion layer, gate 22e is composed of a metal wire provided in extended against the upper surface of the P-type diffusion layer side. The source 22d is the same member as the source 22c. That is, the source 22 c of the PMOS transistor 16 is connected to the source 22 d of the PMOS transistor 16.
Is connected to

[0010] In FIG. 5, a grid indicated by a black circle represents a minimum interval at which wiring can be provided. That is, the wiring is mainly provided at a position along the black circle, and is connected to the semiconductor portion through a through hole or the like usually placed at the position of the black circle. The range of the area of one basic cell is a rectangular range surrounded by a dotted line.

A conventional basic cell including a total of four transistors of the NMOS type and the PMOS type has been configured as described above. However, when a static memory cell is constructed in a gate array, a flip-flop section is generally composed of two NMOS transistors and two PMOS transistors, and two NMOS transistors are additionally provided. Are used to form two pass gates.
That is, one static memory cell is constituted by a total of four NMOS transistors and two PMOS transistors. Therefore, when a conventional basic cell including four transistors is used, one memory cell is configured using two basic cells.
That is, a flip-flop section is formed using one basic cell, and a pass gate is formed using two NMOS transistors among the other basic cells. As a result, there is a problem that two PMOS transistors are not used.

In the case of configuring a ROM, generally, in order to improve the reading speed, all the transistors are configured with NMOS transistors. In this gate array, the utilization factor of the transistors is 50% (half of the PMOS transistors are not used).

In order to solve these problems, for example, Japanese Patent Application Laid-Open No. 63-306639 discloses
1 shows a semiconductor integrated circuit device having a basic cell including two PMOS transistors and four NMOS transistors. A plan view of the basic cell shown here is shown in FIG. Note that, as in FIG.
The type diffusion layer and the P type diffusion layer are indicated by hatching, and a grid representing the minimum interval between wirings is indicated by black circles. Similarly, the range of the area of one basic cell is a rectangular range indicated by a dotted line.

As shown in FIG. 6, this basic cell has the same configuration as the conventional basic cell of FIG.
It includes a formation section 30 and an NMOS formation section 32 which is a portion including only NMOS transistors. Newly NMOS forming section 32 made includes a two N-type diffusion layer 34 and 36, a configuration in which a gate <br/> gate electrode 38, extending for the upper surface side thereof. With such a configuration, the NMOS forming unit 32 includes the NMOS transistor 40,
42 are formed. The gate electrode pad 3 to which the wiring to the gate electrode 38 is connected through a through hole or the like.
Reference numeral 9 is located at an end of the NMOS forming section 32.

As described above, if the basic cell described in the above publication is used, one basic cell includes two PMOS transistors and four NMOS transistors. It is possible to configure a static memory cell with the basic cells. Also, NMOS transistors (4) are replaced by PMOS transistors (2).
Therefore, even when a ROM is configured, the utilization factor of the transistor is 2/3, which is 50% (1
/ 2) is improved.

A basic cell similar to that shown in FIG.
No. 43349. In particular, FIG. 4 of the same publication discloses an NMOS formation portion having substantially the same structure as that of FIG. 6 and including two NMOS transistors.

[0015]

Since the conventional semiconductor integrated circuit device is configured as described above, it is easy to configure a static memory cell. However, FIG.
As can be understood at a glance, an unused portion occurs in the basic cell. As described above, since the gate array is manufactured based on the master slice in which the basic cells are laid out, the ratio of the unused portion of the basic cell substantially matches the ratio of the entire unused portion. As a result, the gate array using the basic cells as shown in FIG.
The ratio of the unused portion becomes extremely large, and only a semiconductor integrated circuit device with low area efficiency can be realized.

This is a problem derived from the lateral width of the NMOS formation portion. That is, in the configuration of FIG. 5, the horizontal width of the basic cell is 3 grids, whereas in the configuration of FIG.
The width of the basic cell is 4 grids due to the width of the OS forming portion. This is because the basic cell of the conventional improved example shown in FIG. 6 has a gap of one grid between the two NMOS transistors 40 and 42.
If such a gap is not provided and the two transistors 40 and 42 are directly adjacent to each other, they are electrically coupled and one N
It becomes a MOS transistor.

As is apparent from a comparison between FIG. 5 and FIG. 6, the configuration of FIG. 5 requires only three grids in the width of the basic cell, whereas the configuration of FIG. You need a grid.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a gate array type semiconductor having a basic cell which can constitute a static memory cell by itself and having a small area. It is to obtain an integrated circuit device.

[0019]

SUMMARY OF THE INVENTION According to a first aspect of the present invention, a gate is provided.
An array-type semiconductor integrated circuit device, comprising: a CMOS forming unit including a same number of NMOS transistors and PMOS transistors and having a rectangular region; an NMOS forming unit including only NMOS transistors and including a rectangular region; containing the basic cell having a rectangular region with the NMOS forming portion includes a gate electrode pad located in the center, the first N of position on one side of the gate electrode pad
-Type diffusion layer, anda second N-type diffusion layer that position on the other side of the gate electrode pad, from the gate electrode pad, an upper surface of said first and second N-type diffusion layer side and a pair
Their respective gate electrodes are extended, of the gate electrode pad
An NMOS transistor is formed on each of the one side and the other side .

In this case, in the basic cell, the gate electrode
Pads can be located in the center of the NMOS formation
You.

[0021] The second aspect of the present invention, the upper Symbol of the first aspect of the present invention, wherein
A gate array type semiconductor integrated circuit device, comprising:
The MOS forming section includes a flat gate electrode extending on the upper surface of the diffusion layer, and gate electrode pads provided at both ends of the gate electrode, wherein the gate electrode pad is connected to the gate electrode. it characterized in that provided on the source side against.

Therefore, there is no gate electrode pad on the drain side of the CMOS formation portion. for that reason,
The wiring between the drains in the CMOS formation portion can be linearly wired, and the wiring length can be shortened.

[0023]

According to the first aspect of the present invention, since the gate electrode pad is disposed between the first and second diffusion layers, the first and second diffusion layers and the gate electrode pad are closely adjacent to each other. It is possible to arrange. Therefore, the area occupied by the NMOS formation portion is reduced.

According to the second aspect of the present invention, the wiring between the drains of the transistors in the CMOS formation portion can be made linearly without increasing the number of wiring layers.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a plan view showing the configuration of one basic cell of a semiconductor integrated circuit according to Embodiment 1 of the present invention. Also in this configuration plan view, similarly to FIG. 5, the N-type diffusion layer and the P-type diffusion layer are indicated by hatching, and a grid indicating the minimum interval between wirings is indicated by black circles. Similarly, the range of the area of one basic cell is a rectangular range indicated by a dotted line.

As shown in FIG. 1, this basic cell has the same configuration as the conventional basic cell of FIG.
It includes an S forming section 50 and an NMOS forming section 52 which is a portion including only an NMOS transistor. The newly added NMOS forming section 52 includes two NMOS transistors 60, similar to the conventional improved example shown in FIG.
62 are formed. That is, the NMOS forming section 52
Includes a and two N-type diffusion layer 54 56, a configuration in which a gate electrode 58, extending for the upper surface side thereof.

A feature of the present embodiment is that a gate electrode pad 59 to which a wiring to the gate electrode 58 is connected through a through hole or the like is located substantially at the center of the NMOS forming section 52. That is, the gate electrode pad 59 is located at the center, and the left and right
Two N- type diffusion layers 54 and 56 are provided. A gate electrode 58 is extended to each of the N-type diffusion layer side from the gate electrode pad 59 (the upper surface of).

As described above, in this embodiment, the NMO
The two NMOS transistors 60 and 6 in the S forming section 52
2, a gate electrode pad 59 is provided. With this configuration, as shown in FIG. 1, the horizontal width of the basic cell can be set to 3 grids. As described above, the basic cell of the conventional improved example shown in FIG.
Although a gap is required to separate the two NMOS transistors 40 and 42, according to the present embodiment, the gate electrode pad 59 is provided on the region separating the transistors 40 and 42 . And separate gate electrode
There is no need to provide a gap for providing a gate.

[0030] Therefore, the NMO
The width of the S forming portion 52 can be reduced, and as a result, the width of the basic cell can be suppressed to 3 grids.

FIG. 2 shows the state of the wiring of the flip-flop portion at the center when a static memory cell is formed using the basic cells according to the present embodiment. In the drawing, the wiring is indicated by a thick black line, and the through holes for connecting to the diffusion layers or the electrode pads are indicated by the squares. As shown in FIG. 2, an inverter including an NMOS transistor 10 and a PMOS transistor 14, an NMOS transistor 12 and a PM
The input and output of the inverter including the OS-type transistor 16 are connected to each other to form a flip-flop (static memory cell).

That is, the output signal of one inverter is taken out from the connection point between the drain 20a and the drain 22a, and the output signal is input to the connection point between the gates 20e and 22e which are the inputs of the other inverter. . Conversely, the output signal of the other inverter is taken out from the connection point between the drain 20f and the drain 22f, and the output signal is supplied to the gates 20b and 22 which are the inputs of one inverter.
It is input to the connection point with b. The VSS potential is supplied to the common source 20d of the NMOS transistor, and V.sub.SS is supplied to the common source 22d of the PMOS transistor.
The DD potential is supplied.

As described above, according to this embodiment, it is possible to obtain a gate array type semiconductor integrated circuit device in which the area of the unused portion in the region of the basic cell is reduced and the area utilization is high. .

Embodiment 2 According to the above embodiment, a static memory cell can be constituted by one basic cell, so that a static memory can be easily constructed. However, as understood from the wiring in FIG. 2, a part of the wiring protrudes from the area of the basic cell. That is, the wiring connecting the drain 20f and the drain 22f protrudes from the region of the basic cell and erodes other regions. There is also a problem that the wiring length becomes long. These problems can be solved by increasing the number of wiring layers of aluminum to two. However, increasing the number of wiring layers by one increases the number of masks, resulting in a significant increase in cost and time. . Conversely, if the number of wiring layers is reduced by one, significant cost reduction and time reduction can be achieved.

FIG. 3 is a plan view showing the configuration of a basic cell of a semiconductor integrated circuit according to a second embodiment of the present invention which solves the above problems. The characteristic of this embodiment is that NM
OS transistor 12 and PMOS transistor 1
The gate electrode pad of No. 6 has a gate electrode (20e, 22e).
e), the drain of the transistor (20f,
That is, it is provided on the common source (20d, 22d) side, not on the 22f) side. With this arrangement of the gate electrode pads, the drain 20f of the NMOS transistor 12 and the PMOS transistor 16
Can be provided to connect linearly with the drain 22f. That is, the wiring does not protrude outside the area of the basic cell.

FIG. 4 shows a state of wiring when a static memory cell is formed by the basic cells according to the present embodiment. As shown in FIG. 4, the gate electrode 20e
And 22e have a common source 20d,
It is provided toward the 22d side. Therefore, the drain 20f and the drain 22f can be connected in a straight line, and the wiring does not protrude from the region of the basic cell. In addition, the wiring can be extended at the shortest distance without increasing the number of wiring layers by one.

As described above, according to the present embodiment, when configuring a static memory cell, the wiring for the flip-flop can be configured with only one layer, and the wiring is formed within the area of the basic cell. It is possible to fit. Therefore, according to the semiconductor integrated circuit device using the basic cells of the present embodiment, when a static memory is configured, the area utilization efficiency is extremely good.

[0038]

As described above, according to the first aspect of the present invention, the first N-type diffusion layer, the gate electrode pad, and the second N-type diffusion layer are closely adjacent to each other. Can be provided. Therefore, the lateral width of the NMOS formation portion can be kept small, and the area of the unused portion in the basic cell can be kept very small.

Therefore, the use of the basic cell of the present invention has an effect that a semiconductor integrated circuit having extremely good area use efficiency can be obtained.

Further, according to the second aspect of the present invention, since the gate electrode pad of the CMOS formation portion is provided on the source side, an empty area is generated around the drain side. Therefore, the wiring between the adjacent drains can be arranged linearly without being disturbed by the wiring of the gate and the like.

Therefore, when the basic cell of the present invention is used, there is an effect that a semiconductor integrated circuit device in which wiring is easy when a static memory cell is formed can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration plan view of a basic cell of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a case where a wiring is provided to a basic cell of the semiconductor integrated circuit device according to the first embodiment of the present invention to configure a flip-flop;

FIG. 3 shows the basics of a semiconductor integrated circuit device according to a second embodiment of the present invention;
FIG. 3 is a plan view of a configuration of a cell .

FIG. 4 is an explanatory diagram of a case where a wiring is provided in a basic cell of a semiconductor integrated circuit device according to a second embodiment of the present invention to configure a flip-flop;

FIG. 5 is a configuration plan view of an example of a basic cell of a conventional semiconductor integrated circuit device.

FIG. 6 is a configuration plan view of an example of an improved basic cell of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 Reference Signs List 50 CMOS forming part 52 NMOS forming part 54, 56 N-type diffusion layer 58 Gate electrode 59 Gate electrode pad 60, 62 NMOS transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/118 H01L 21/822 H01L 21/8244 H01L 27/04 H01L 27/11

Claims (2)

(57) [Claims] 1. A CMOS transistor comprising a same number of NMOS transistors and PMOS transistors and having a rectangular region.
And S forming part includes only NMOS transistors, containing the basic cell having a rectangular region with the NMOS forming portion, a having a rectangular region, the NMOS forming portion includes a gate electrode pad located in the center, the gate a first N-type diffusion layer that position on one side of the electrode pad, anda second N-type diffusion layer that position on the other side of the gate electrode pad, from the gate electrode pad, the first first and the second N-type diffusion layer side upper surface a pair Shiteso respectively the gate electrode of and extension, the said one side of said gate electrode pad while
A gate array type semiconductor integrated circuit device , wherein an NMOS transistor is formed on each side . 2. The gate array type semiconductor integrated circuit device according to claim 1, wherein said CMOS forming portion comprises: a flat gate electrode extending on an upper surface of a diffusion layer; A gate array type semiconductor integrated circuit device, comprising: a gate electrode pad provided respectively; and wherein the gate electrode pad is provided on the source side with respect to the gate electrode.