JP2821063B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a basic cell (basic cell).
l) are regularly arranged, so-called master slice type semiconductor integrated circuits (gate arrays), and so-called complex LSIs in which basic cells are mixed with standard cells, CPU cores, analog circuits, etc. The present invention relates to a semiconductor integrated circuit including a basic cell.

For example, a master slice type semiconductor integrated circuit is configured by arranging basic cells in a central portion of a chip excluding an input / output region provided in a peripheral portion of the chip. The mainstream was a so-called wiring channel method in which a basic cell arrangement region and a wiring channel region were separated.

However, in recent years, in order to increase the number of gates, basic cells are laid all over the central portion of the chip.
A so-called master-slice type semiconductor integrated circuit (COS [sea of gate]) of a so-called gate spread type is becoming mainstream.

In such a master-slice type semiconductor integrated circuit of a gate-layout type, a logic unit cell such as an inverter or a NAND circuit is used together with an RA.
It is required to mount a large-scale macro cell such as M or ROM.

For this reason, it is necessary that the basic cells to be mounted on the gate-slipped master slice type semiconductor integrated circuit have a structure which can easily constitute a RAM cell or a ROM cell in addition to a logical unit cell. .

[0006]

2. Description of the Related Art Conventionally, as a basic cell mounted on a master slice type semiconductor integrated circuit, a cell whose plan view is shown in FIGS. 41 and 42 has been proposed.

In FIG. 41, reference numerals 1 to 3 denote N ⁺ diffusion layers, 4
6 to 6 are P ⁺ diffusion layers, and 7 to 10 are gate electrodes made of polysilicon. In this basic cell, the NMOS 11 is composed of the N ⁺ diffusion layers 1 and 2 and the gate electrode 7.
⁺ Diffusion layers 2 and 3 and gate electrode 8 constitute nMOS 12. Further, a pMOS 13 is constituted by the P ⁺ diffusion layers 4 and 5 and the gate electrode 9, and a pMOS 14 is constituted by the P ⁺ diffusion layers 5 and 6 and the gate electrode 10.
2 (see, for example, US Pat. No. 5,053,993)
, 15 to 23 are N ⁺ diffusion layers, and 24 to 26 are P ⁺
Diffusion layers 27 to 30 are gate electrodes made of polysilicon. In this basic cell, N ⁺ diffusion layers 15 and 1 are used.
6 and the gate electrode 27 constitute an nMOS 31, and N ⁺
The diffusion layers 16 and 17 and the gate electrode 28 constitute an nMOS 32. A pMOS 33 is composed of the P ⁺ diffusion layers 24 and 25 and the gate electrode 27, and the P ⁺ diffusion layer 2
5, 26 and the gate electrode 28 constitute a pMOS 34.

Further, N ⁺ diffusion layers 18 and 19 and the gate electrode 29 and at nMOS35 is constructed, N ⁺ diffusion layer 19, 2
0 and the gate electrode 30 form an nMOS 36, and N ⁺
Diffusion layers 21 and 22 and gate electrode 29 constitute nMOS 37, and N ⁺ diffusion layers 22 and 23 and gate electrode 30 constitute nMOS 38.

[0009]

In a master slice type semiconductor integrated circuit in which basic cells are arranged as shown in FIG. 41, as will be described later in detail, the arrangement of logical unit cells and the securing of a wiring channel region are performed. Although it has a high degree of freedom, there is a problem that it is difficult to form RAM cells and ROM cells.

In a master slice type semiconductor integrated circuit in which basic cells are arranged as shown in FIG.
Although the cells are easy to make, they are horizontal or vertical basic cells, so that the arrangement pitch of the basic cells is increased, and there is a problem that the degree of freedom in arranging the logic unit cells and securing the wiring channel area is reduced.

In a master slice type semiconductor integrated circuit in which basic cells are arranged as shown in FIG. 42, when a one-port RAM is configured, the basic cells can be used efficiently. When a three-port RAM is created, there are many gates that are not used, and there is a problem that the basic cells cannot be used efficiently.

The above problems are caused by the problems shown in FIGS.
The basic cells shown in the above are standard cells, CPU cores,
A similar problem exists in a composite LSI mixed with an analog circuit or the like.

In view of the above, the present invention has a high degree of freedom in arranging logic unit cells and in selecting a wiring channel region, and has a high degree of freedom in logic unit cells, RAM cells, and ROs.
It is an object of the present invention to provide a semiconductor integrated circuit in which the use efficiency of a basic cell in the case of forming an M cell or the like is increased, and the channel width of a transistor in the basic cell region is reduced to achieve high integration. And

[0014]

FIG. 1 is an explanatory view of the principle of the present invention, and shows a planar structure of a MOS forming portion constituting a basic cell provided in a semiconductor integrated circuit according to the present invention.

In the figure, 39 to 41 are wiring paths extending in the X direction orthogonal to the Y direction at a wiring pitch set in the Y direction, and 42 and 43 are intervals of an integral multiple of the wiring pitch set in the X direction. Is a wiring path extending in the Y direction.

Reference numerals 44 to 46 denote impurity diffusion layers used as a drain or a source. These impurity diffusion layers 44 to 46 are arranged in the Y direction in the substrate region below the wiring paths 39 to 41, respectively. I am.

Reference numerals 47 and 48 denote gate electrodes. The gate electrode 47 includes a narrow portion 49, a first wide portion 50,
The gate electrode 48 includes a narrow portion 52, a first wide portion 53, and a second wide portion 51.
And a wide portion 54.

Here, in the gate electrode 47, the narrow portion 49 is configured to extend in the X direction including above the substrate region (channel region) between the impurity diffusion layers 44 and 45. I have.

The first wide portion 50 is connected to the left end of the narrow portion 49, is located on the plane outside the left ends of the impurity diffusion layers 44 and 45, and intersects the wiring path 39 and the wiring path 42. , And below the intersection of the wiring path 40 and the wiring path 42, the gate contact regions 55 and 56 are provided, respectively.

The second wide portion 51 is connected to the right end of the narrow portion 49, is positioned on the plane outside the right end of the impurity diffusion layer 44, and is located below the intersection of the wiring path 39 and the wiring path 43. And a gate contact region 57.

In the gate electrode 48, the narrow portion 52 is configured to extend in the X direction including above the substrate region (channel region) between the impurity diffusion layers 45 and 46. .

The first wide portion 53 is connected to the left end of the narrow portion 52, is located on the plane outside the left end of the impurity diffusion layer 46, and is below the intersection of the wiring paths 41 and 42. And a gate contact region 58.

The second wide portion 54 is connected to the right end of the narrow portion 52 and located on the outside of the right end of the impurity diffusion layers 45 and 46 on the plane, and intersects the wiring path 40 and the wiring path 43. , And below the intersection of the wiring path 41 and the wiring path 43, respectively.

[0024]

In the present invention, the MOS 61 is constituted by the impurity diffusion layers 44 and 45 and the gate electrode 47, and the MOS 62 is constituted by the impurity diffusion layers 45 and 46 and the gate electrode. For example, when the impurity diffusion layers 44, 45, 46 are N ⁺ diffusion layers, the MOSs 61, 62 are nMOS, and when the impurity diffusion layers 44, 45, 46 are P ⁺ diffusion layers, the MOSs 61, 62 are used. Becomes a pMOS.

Further, the MOS forming portion shown in FIG.
When two basic cells are arranged in the X direction as the forming unit and the pMOS forming unit, and the basic cells are formed to have a width in the X direction, the minimum width of the logical unit cell and the wiring channel region is set to one basic cell. Can be width. Therefore,
A high degree of freedom can be ensured for the arrangement of the logic unit cells and the selection of the wiring channel region.

In the present invention, the gate electrode 47
Provides two gate contact regions 55 and 56 arranged in the Y direction in the first wide portion 50, and the gate electrode 48
In the second wide portion 54, two gate contact regions 59 and 60 arranged in the Y-walk are provided.

As a result, as described above, the MO shown in FIG.
The S forming portion is defined as an nMOS forming portion and a pMOS forming portion.
In the case where a basic cell having a width in the X direction is formed by arranging the power supply wirings in the X direction, a power supply wiring extending in the Y direction is provided above the gate contact region and in the second layer counted from the lower layer in the wiring layer. Can be formed, and it is not necessary to form a power supply wiring above the transistor in the basic cell region.

Therefore, according to the present invention, the channel width of the transistor in the basic cell region can be reduced, high integration can be achieved, and the logical unit cell, the RAM cell, and the ROM of the basic cell can be formed. The use efficiency can be increased and high integration can be achieved.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, advantages of the configuration shown in FIG. 1 and disadvantages of the configuration shown in FIG. 41 will be described.

Using the configuration shown in FIG. 1, for example, a complementary MOS transistor can be formed. FIG. 2A shows a CMOS transistor region using two configurations of FIG. Here, the configuration (transistor region) of FIG. 1 is indicated by reference numeral 200. The two transistor regions 200 are arranged symmetrically in the Y direction. One transistor region 200 is P-type, and the other transistor region 200 is N-type. In the figure, a portion indicated by “+” corresponds to, for example, a grid used in a CAD system. Each transistor region 200 in FIG. 2A has five grids in the X direction (corresponding to five wiring channels).
And three grids (corresponding to three wiring channels) in the Y direction. These transistor regions 200
Then, for example, wiring for forming the logic circuit in FIG. The logic circuit in FIG.
MOS inverters are connected in parallel.

In FIG. 2A, a thick solid line indicates a first-layer wiring, and a thick hatched line indicates a second-layer wiring. The symbol “•” indicates a contact between the first layer wiring and the bulk, and the symbol “■” indicates a contact between the first layer wiring and the second layer wiring. The wiring 210 is in contact with the four gate electrodes via the four gate contacts.
This constitutes the input terminal of the logic circuit of FIG. Wiring 21
2 is in contact with the central diffusion layer of the left transistor region 200 through one of the three contact regions, and is in contact with the central diffusion layer of the right transistor region 200 through one of the three contact regions. I have. Wiring 2
Reference numeral 12 denotes an output terminal of the logic circuit shown in FIG. The power supply line 214 of the potential VSS is in the second layer and extends in the X direction. Similarly, the power supply line 216 of the potential VDD is in the second layer and extends in the X direction. The plurality of substrate contact layers 222 extend in the X direction. The potential VDD is higher than the potential VSS. Each substrate contact layer 222 has a length corresponding to three grids. The power supply line 214 contacts one substrate contact layer 222 and the power supply line 21
6 is in contact with another substrate contact layer 222. The wiring 218 extending in the Y direction is in contact with two diffusion layers other than the diffusion layer at the center of the left transistor region 200. Further, the wiring 218 is connected to the second-layer power supply line 216. The wiring 220 extending in the Y direction is in contact with two diffusion layers other than the diffusion layer at the center of the transistor region 200 on the right side. Further, the wiring 220 is connected to the second-layer power supply line 214.

FIG. 3A shows a CMOS region having two conventional transistor regions 300. Each of the conventional transistor regions 300 has the configuration shown in FIG. In order to form the logic circuit in FIG. 4A, wirings described below are provided. The wiring 310 contacts four gate electrodes via four gate contacts, and forms an input terminal of a logic circuit. The wiring 312 is in contact with the diffusion layer at the center of the two transistor regions 300. Power lines 314 and 316 are provided as shown. Further, wirings 318 and 320 are provided like the wirings 218 and 220 described above. Power lines 314 and 31
6 extend over the substrate contact layer 322.

The configuration of FIG. 2A is superior to the configuration of FIG. 3A in the following points. In the Y direction, FIG.
The gate contact wiring 210 in (A) has a length corresponding to two grids. On the other hand, the corresponding wiring 310 in FIG. 3A has a length corresponding to three grids. Therefore, the configuration of FIG. 2A has a higher degree of freedom for other wirings than the configuration of FIG. For example, as illustrated in FIG. 2A, a wiring 212 which forms an output terminal of the logic circuit in FIG. 4A can be extended over a gate electrode (wide portion) of the transistor region 200. On the other hand, in the structure of FIG. 3A, the wiring 312 cannot be provided over the gate electrode of the transistor region 300 because the wiring 310 is provided. The wiring 312 passes under the power supply line 314.

In FIG. 2A, if it is necessary to contact the wiring 212 extending in the X direction and the wiring passing therethrough with the grid G1 or G2, such a contact can be formed without overlapping the contact. .
Overlapping contacts at the same grid location is technically possible, but leads to increased manufacturing costs. Therefore,
Normally, contact overlap is not preferred. On the other hand, FIG.
In (A), when the wiring 312 extending in the X direction and the wiring passing thereover are contacted by the grid G1 or G2, contact overlap occurs. The grids G1 and G2 are already used for contact with the wiring 312.

FIG. 2B shows a structure in which wiring for forming the logic circuit of FIG. 4B is provided in a CMOS region formed using two transistor regions 200 according to the present invention. The logic circuit of FIG. 4B has two cascaded CMOS inverters. Note that FIG.
2B, the same members as those in FIG. 2A are denoted by the same reference numerals. The wiring 224 connects the two gates in the first-stage CMOS inverter to each other, and forms an input terminal of the logic circuit in FIG. Wiring 226 is the second stage CM
The gates of the transistors of the OS inverter are connected to each other, and the drains of the transistors of the first inverter are connected to each other. The wiring 228 connects the drains of the transistors of the second-stage inverter to each other and forms an output terminal of a logic circuit.

FIG. 3B shows a case where the logic circuit of FIG. 4B is formed using two conventional transistor regions. In FIG. 3B, the same members as those in FIG. 2B are denoted by the same reference numerals. The wiring layer 324 is the first-stage CMO
By connecting the two gates in the S inverter to each other,
The input terminals of the logic circuit of FIG. The wiring 326 connects the gates of the transistors of the second-stage CMOS inverter to each other and connects the drains of the transistors of the first-stage inverter to each other. The wiring 328 is 2
The drains of the transistors of the inverter at the stage are connected to each other to form an output terminal of the logic circuit.

The configuration of FIG. 2B has the same advantages as FIG. 2A, and the configuration of FIG. 3B has the same disadvantages as the configuration of FIG. That is, the wiring 226 has a length corresponding to two grids in the Y direction, while the wiring 336
It has a length corresponding to three grids in the direction. Wiring 2
18 passes over the grids G1 and G2, while the wiring 318 passes under the power supply line 314. In FIG. 2B, the grid G1 or G2 can be formed without overlapping the contacts.
Thus, the second layer wiring (not shown) can be brought into contact with the first layer wiring 228. On the other hand, in the case of FIG. 3B, the second layer wiring (not shown) and the first layer wiring 328 cannot be contacted by the grid G1 or G2 unless the grids overlap.

The configuration of FIG. 2B has the following advantages, and the configuration of FIG. 3B has another disadvantage. FIG. 3 (B)
In the above, when it is necessary to contact a second layer wiring (not shown) with the wiring 328 without overlapping the contacts, it is necessary to extend the wiring 328 and make contact with the grid G3, for example. When such a contact is made in the grid G3, it is no longer possible to provide another first-layer wiring extending on the grid G3 and extending in the Y direction. In consideration of this point, each diffusion layer is usually designed to have a length of four grids. By doing so, even if the wiring 328 is brought into contact with the grid G3,
Another first layer wiring extending in the Y direction on the fourth grid can be provided. However, in this case, the degree of freedom of the wiring layout is very small. Further, since the diffusion layer needs to have a length of four grids, it is not suitable for miniaturization.

On the other hand, in FIG. 2B, when it is necessary to contact a second-layer wiring (not shown) with the wiring 228 without overlapping the contacts, the second wiring does not overlap with the contacts.
Contact can be made with the grid G1 or G2. Therefore, it is possible to easily provide the second layer wiring extending in the Y direction over the grid G3. That is, the length of the diffusion layer does not need to be 4 grids.

In FIGS. 2A and 2B,
The bent portion 250 of each gate electrode is provided to keep the distance between adjacent gate electrodes substantially constant. FIG.
By combining a plurality of the configurations described above, a basic cell described below can be configured. Hereinafter, various embodiments of the present invention will be described with reference to FIGS. 5 to 42, but the present invention is not limited to these embodiments.

First Embodiment FIG. 5 FIG. 5 is a plan view showing the entire first embodiment of the present invention.
In the figure, 63 is a chip body, 64 is an input / output cell, 65 is a basic cell area, and 66 is a basic cell. That is, the first embodiment is one in which the present invention is applied to a master slice type semiconductor integrated circuit, and is used, for example, when forming a semiconductor integrated circuit as shown in FIG.

In the figure, reference numeral 67 denotes a logic unit cell having a width in the X direction equal to the width of one basic cell, and reference numeral 68 denotes a logic unit having a width in the X direction equal to the width of two basic cells. Cell.

Reference numeral 69 denotes a wiring channel region having a width in the X direction corresponding to one basic cell, and 70 denotes a wiring channel region having a width in the X direction corresponding to two basic cells. , 71 are logical unit cells arranged without providing a wiring channel region, and 72A, 72B, 72C are RAMs.
Block 73 is a ROM block.

FIG. 7 is a plan view showing a part of the basic cell region 65. In the first embodiment, the basic cell 66 has two types of CMOS forming sections 74 and 7 having different structures.
5 are arranged side by side in the Y direction. Reference numeral 78 denotes a substrate contact region.

FIG. 8 is a plan view showing the CMOS forming section 74. The CMOS forming section 74 is composed of an nMOS forming section 79 and a pMOS forming section 8 which are juxtaposed in the X direction.
0. Here, 81 to 83 are wiring paths extending in the horizontal direction at wiring pitch intervals, and 84 to 93 are wiring paths extending in the Y direction at wiring pitch intervals.

Here, in the nMOS formation section 79, 9
4 to 96 are N ⁺ diffusion layer, these N ⁺ diffusion layer 94 to
Reference numerals 96 are juxtaposed in the Y direction in the substrate region below the wiring paths 81 to 83, respectively. Reference numeral 97 denotes a contact region.

Reference numerals 98 and 99 denote gate electrodes made of polysilicon.
, A first wide portion 101 and a second wide portion 102, and the gate electrode 99 also has a narrow portion 103.
, And a first wide portion 104 and a second wide portion 105.

Here, in gate electrode 98, narrow portion 100 extends in the X direction including above the channel region between N ⁺ diffusion layer 94 and N ⁺ diffusion layer 95. .

Also, the first wide portion 101 is
0, located on the plane outside the left ends of the N ⁺ diffusion layers 94 and 95, below the intersection of the wiring paths 81 and 84 and at the intersection of the wiring paths 82 and 84. Below, the gate contact regions 106 and 107, respectively,
Is provided.

Further, the second wide portion 102 is formed by the narrow portion 10.
0, is located outside the right end of the N ⁺ diffusion layer 94 on the plane, and has a gate contact region 108 below the intersection of the wiring path 81 and the wiring path 88.

The width of the gate electrode 99 is
The narrow portion 103 is N⁺Diffusion layer 95 and N ⁺Between diffusion layer 96
Extending in the X direction including above the channel region of
Have been.

Further, the first wide portion 104 is formed by the narrow portion 10.
3 and is located outside the left end of the N ⁺ diffusion layer 96 on the plane, and has a gate contact region 109 below the intersection of the wiring paths 83 and 84.

Further, the second wide portion 105 is connected to the narrow portion 10.
3 and located on the outside of the right ends of the N ⁺ diffusion layers 95 and 96 on the plane, below the intersection of the wiring paths 82 and 88 and at the intersection of the wiring paths 83 and 88. Below, the gate contact regions 110 and 111, respectively,
Is provided.

In the pMOS forming section 80, 11
Reference numerals ^{2 to} 114 denote P ⁺ diffusion layers.
2 to 114 are arranged in the Y direction in the substrate area below the wiring paths 81 to 83, respectively. Reference numeral 115 indicates a contact region.

Reference numerals 116 and 117 denote gate electrodes. The gate electrode 116 includes a narrow portion 118, a first wide portion 119, and a second wide portion 120. The electrode 117 also has a narrow portion 121, a first wide portion 122, and a second wide portion 123.

Here, for gate electrode 116, narrow portion 118 extends in the X direction including above the channel region between P ⁺ diffusion layer 112 and P ⁺ diffusion layer 113. I have.

Further, the first wide portion 119 includes the narrow portion 11
8 and is located outside the left end of the P ⁺ diffusion layer 112 on the plane, and has a gate contact region 124 below the intersection of the wiring path 81 and the wiring path 89.

Further, the second wide portion 120 is connected to the narrow portion 11.
8 and on the plane, the P ⁺ diffusion layers 112 and 11
3 and below the intersection of the wiring path 81 and the wiring path 93 and below the intersection of the wiring path 82 and the wiring path 93, respectively.
26.

The gate electrode 117 has a narrow width.
The part 121⁺Diffusion layer 113 and P ⁺With the diffusion layer 114
A configuration extending in the X direction, including above the channel region between
Have been.

The first wide portion 122 is formed by the narrow portion 12
1 and the P ⁺ diffusion layers 113 and 11 on a plane.
4 and below the intersection of the wiring paths 82 and 89 and below the intersection of the wiring paths 83 and 89, respectively.
28.

The second wide portion 123 is formed by the narrow portion 12
1 and is located outside the right end of the P ⁺ diffusion layer 114 on the plane, and has a gate contact region 129 below the intersection of the wiring paths 83 and 93.

The CMOS forming section 74 thus configured
In, N ⁺ diffusion layers 94, 95 and between the gate electrode 98 NMOS130 is configured, NMOS131 is constituted by the N ⁺ diffusion layer 95 and 96 and the gate electrode 99.

A pMOS 132 is composed of P ⁺ diffusion layers 112 and 113 and gate electrode 116, and a pMOS 133 is composed of P ⁺ diffusion layers 113 and 114 and gate electrode 117.
Is configured. FIG. 9 is an equivalent circuit diagram of the CMOS forming section 74. Note that the CMOS forming section 75 is a CMOS
The structure is such that the forming portion 74 is inverted with respect to the X axis.

FIG. 10 is a sectional view taken along line AA in FIG. 7, FIG. 11 is a sectional view taken along line BB in FIG.
FIG. 13 is a cross-sectional view taken along line CC of FIG. 7, and FIG.
It is sectional drawing along the D line. However, the gate oxide film is not shown. Reference numeral 134 denotes a P-type silicon substrate, 1
35 is an N ^- well.

The basic cell 66 thus configured can be used, for example, as shown in FIG. FIG.
FIG. 4A shows the arrangement of the basic cells 66 in the X direction.
4B and 14C show examples in which logic unit cells and wiring channels are arranged, FIG. 14D shows an example in which RAM cells are arranged, and FIG. 14E shows an example in which ROM cells are arranged.

That is, in the first embodiment, the minimum width of the logic unit cell and the wiring channel region is determined by the basic cell 1
It can be the width of an individual. Therefore, a high degree of freedom can be ensured in the arrangement of the logic unit cells and the selection of the wiring channel region. Also, a RAM cell, R
The width of the OM cell can be configured as the width of one basic cell.

Here, for example, an inverter whose circuit diagram is shown in FIG. 15 can be configured as shown in its plan view in FIG. In the figure, 136 and 137 are pM
OSs 138 and 139 are nMOS.

The dotted lines indicate the first-layer aluminum wiring, the hatched lines extending upward to the right indicate the second-layer aluminum wiring,
Black circles (●) indicate contact holes between the bulk or gate electrode and the first layer aluminum wiring, squares filled with black (■)
Denotes a contact hole between the first-layer aluminum wiring and the second-layer aluminum wiring, and a dot (•) denotes a grid on the layout (the same applies hereinafter).

FIG. 17 is a circuit diagram of the second embodiment.
The input NAND circuit can be configured as shown in a plan view of FIG. In the figure, 140 and 141 are pM
The OSs 142 and 143 are nMOS.

FIG. 19 shows a circuit diagram of N
The OR circuit can be configured as shown in a plan view of FIG. In the figure, 144 and 145 are pMOS, 14
6, 147 are nMOSs.

FIG. 21 is a circuit diagram of the circuit shown in FIG.
The port RAM cell can be configured as shown in the plan view of FIG. In the figure, WL is a word line, BL,
BL bar is a bit line.

Reference numerals 148 and 149 denote nMOSs forming transfer gates, 150 denotes a flip-flop forming a storage element, 151 and 152 denote pMOSs forming a flip-flop 150, and 153 and 154 denote nMOSs forming the flip-flop 150. is there.

FIG. 23 shows a circuit diagram of the second embodiment.
The port RAM cell can be configured as shown in a plan view in FIG. In the figure, WL1 is a word line of the first port, BL1 and BL1 bars are bit lines of the first port,
WL2 is a word line of the second port, and BL2 and BL2 are bit lines of the second port.

Reference numerals 155 and 156 denote nMOs forming transfer gates of the first port selected by the word line WL1.
S, 157 are flip-flops constituting a storage element, 1
58, 159 are pMs constituting the flip-flop 157
OS: 160 and 161 are also flip-flops 157
Is an nMOS.

Reference numerals 162 and 163 denote nMOs forming transfer gates of the second port selected by the word line WL2.
S, 164, 165 are inverters forming a buffer, 16
Reference numeral 6 denotes a pMOS that forms the inverter 164, 167 denotes an nMOS that also forms the inverter 164, 168 denotes a pMOS that forms the inverter 165, and 169 denotes an nMOS that also forms the inverter 165.

Further, as shown in FIG.
The OM can be configured as shown in the plan view of FIG. In the figure, WLn and WLp are word lines, and BL1 to BL1.
BL4 is a bit line, and 170 to 173 are n forming storage elements.
MOSs 174 to 177 are pMOSs serving as storage elements. The wirings with diagonal lines to the lower right are the third-layer aluminum wirings, and the black diamonds (◆) are the contact holes between the second-layer aluminum wirings and the third-layer aluminum wiring.

In this ROM, the nMOS 170-
Depending on whether or not the drain of 173 is connected to the bit lines BL1 to BL4, the program of the nMOS 170 to 173 can be performed.
177 can be programmed depending on whether or not the drains of the MOS transistors 177 to 177 are connected to the bit lines BL1 to BL4.

Here, as shown in FIG. 22, when forming a one-port RAM cell, as shown in FIG. 24, when forming a two-port RAM cell, as shown in FIG.
Most of the transistors can be used except for some of the transistors in the formation unit 80. Although illustration is omitted, 3
The same applies to the case of configuring a port RAM cell. In the case of configuring a ROM cell, all the transistors of the basic cell 66 can be used as shown in FIG.

That is, according to the first embodiment, the basic unit cells are efficiently used and the logical unit cells, the RAM cells,
An OM cell can be created.

According to the first embodiment, the power supply wiring can be constituted by the second layer aluminum wiring extending in the Y direction over the gate contact region. That is, there is no need to arrange a power supply line on the transistor in the basic cell region. As a result, the contact region between the drain and source and the first layer wiring can be used efficiently, so that the channel width of the transistor of the basic cell can be reduced.

As described above, according to the first embodiment,
With the configuration shown in FIG. 4 for the basic cell 66, a high degree of freedom can be ensured for the arrangement of the logic unit cells and the selection of the wiring channel region.
The use efficiency of the basic cells when producing the RAM cells and the ROM cells can be increased, and the channel width of the transistors in the basic cell region 65 can be reduced to achieve high integration.

FIG. 27 is a diagram showing a first relationship between the conductivity of the CMOS transistor region and the power supply line. In the figure, 7
Reference numerals 4 and 75 denote CMOS forming portions. The diffusion layers of the basic cell 66 on the left side of the figure are N ⁺ and P ⁺
Has the following conductivity type. The diffusion layer of the basic cell 66 on the right side of the drawing has P ⁺ and N ⁺ conductivity types from left to right. That is, the left and right facing diffusion layers have the same conductivity type P ⁺ . The power supply line extends in the Y direction.
Reference numeral 370 indicates a substrate contact area.

FIG. 28 is a diagram showing a second relationship between the conductivity of the CMOS transistor region and the power supply line. In the figure, 74
And 75 are CMOS formation parts. Basic cell 6 on the left side of the figure
The diffusion layer of No. 6 has N ⁺ and P ⁺
Has the following conductivity type. The diffusion layer of the basic cell 66 on the right side of the drawing has N ⁺ and P ⁺ conductivity types from left to right. That is, the left and right facing diffusion layers have different conductivity types P ⁺ . The power supply line extends in the Y direction. The power supply line in FIG. 28 is narrower than the power supply line in FIG.

FIG. 29 is a diagram showing a third relationship between the conductivity of the CMOS transistor region and the power supply line. In the figure, 7
Reference numerals 4 and 75 denote CMOS forming portions. Diffusion layer of Figure on the left side of the basic cell 66, N ⁺ and P from the left in order to right
^It has a positive conductivity type. The diffusion layer of the basic cell 66 on the right side of the drawing has P ⁺ and N ⁺ conductivity types from left to right. That is, the left and right facing diffusion layers have the same conductivity type P ⁺ . The power supply line extends in the X direction.

FIG. 30 is a diagram showing a fourth relationship between the conductivity of the CMOS transistor region and the power supply line. In the figure, 7
Reference numerals 4 and 75 denote CMOS forming portions. Basic cell 6 on the left side of the figure
The diffusion layer of No. 6 has N ⁺ and P ⁺
Has the following conductivity type. The diffusion layer of the basic cell 66 on the right side of the drawing has N ⁺ and P ⁺ conductivity types from left to right. That is, the diffusion layers facing the left side and the right side have the same conductivity type. The power supply line extends in the X direction.

The first to fourth relationships can be selected as appropriate according to the use of the basic cell.

Second Embodiment FIG. 31 FIG. 31 is a plan view showing a part of a basic cell region according to a second embodiment of the present invention. In the figure, reference numeral 178 denotes a basic cell. In the second embodiment, the basic cell 178 is configured by arranging CMOS forming parts 74, 75, 74.75 in the Y direction.

According to the second embodiment, the same operation and effect as those of the first embodiment can be obtained. In addition, the basic cell 66 is constituted by four CMOS forming portions 74, 75, 74, 75, and Since the contact area is reduced, higher integration can be achieved than in the first embodiment.

Third Embodiment FIG. 32 FIG. 32 is a plan view showing a part of a basic cell region according to a third embodiment of the present invention.
The basic cells 66 are arranged as the wiring pitch, and the other configuration is the same as that of the first embodiment.

According to the third embodiment, the same effects as those of the first embodiment can be obtained, and the VDD power supply line 197 can be obtained.
And the width of the VSS power supply line 180 can be increased.
Can be strengthened. Fourth Embodiment FIG. 33 FIG. 33 is a plan view showing a part of a basic cell region according to a fourth embodiment of the present invention. In the figure, reference numeral 181 denotes a basic cell. In the fourth embodiment, the basic cell 181 is configured by arranging CMOS forming parts 182 and 182 in the Y direction.

Here, the CMOS forming section 182 is a CMOS
NMO having the same structure as nMOS forming section 79 of S forming section 74
A pMOS having a structure in which the S formation section 184 and the pMOS formation section 80 of the CMOS formation section 74 are inverted with respect to the Y axis
The forming part 185 is arranged side by side in the X direction. In the fourth embodiment, the same operation and effect as those of the first embodiment can be obtained.

Fifth Embodiment FIG. 34 FIG. 34 is a plan view showing a part of a basic cell region according to a fifth embodiment of the present invention. In the drawing, reference numeral 186 denotes a basic cell. In the fifth embodiment, the basic cell 186 is configured by arranging CMOS forming parts 182 and 187 in the Y direction.

Here, the CMOS forming section 187 is a CMOS
The S light portion 182 has a structure that is inverted with respect to the X axis. According to the fifth embodiment, the same operation and effect as those of the first embodiment can be obtained.

Sixth Embodiment FIG. 35 FIG. 35 is a plan view showing a part of a basic cell region according to a sixth embodiment of the present invention. In the figure, 188 and 189 are basic cells. In the sixth embodiment, the basic cell 188 is a CM.
The OS forming portions 74 are arranged side by side in the Y direction. In addition, the basic cell 189 includes the CMOS forming portions 75 and 75
Are arranged side by side in the Y direction. According to the sixth embodiment, the same operation and effect as those of the first embodiment can be obtained.

FIG. 36 shows a first modification of the sixth embodiment shown in FIG. The arrangement of the gate electrodes in FIG.
5 is the same as that shown in FIG. In the first modification, the pMOS transistor region of the basic cell 188 is different from the basic cell 18.
The configuration differs from the configuration in FIG. 35 in that it faces the nMOS transistor region 9.

FIG. 37 shows a second modification of the sixth embodiment shown in FIG. The arrangement of the gate electrodes in FIG.
5 is the same as that shown in FIG. The power supply line shown in FIG.
Extending in the direction.

FIG. 38 shows a third modification of the sixth embodiment shown in FIG. This third modification is a modification of the basic cell 18.
8 pMOS transistor regions correspond to nM of the basic cell 189.
At the point facing the OS transistor region, FIG.
Configuration. The power supply line extends in the X direction as in FIG.

Seventh Embodiment FIG. 39 FIG. 39 is a plan view showing a part of a basic cell region different from the seventh embodiment of the present invention. Reference numerals 190 and 191 denote basic cells. In the basic cell 190, CMOS formation units 182 and 187 are arranged in the Y direction. Further, the basic cell 191 includes a CMOS forming portion 182,
182 are arranged side by side in the Y direction. This seventh
According to this embodiment, the same operation and effect as those of the first embodiment can be obtained.

The present invention can be applied to a composite LSI as shown in FIG. In the figure, 192 is a CPU core configured without using a basic cell, and 193 is an analog circuit that is similarly bypassed without using a basic cell.

[0100]

As described above, according to the present invention, the MOS
The gate electrode constituting the formation portion has a configuration having two gate contact regions arranged in the Y direction in one wide portion, thereby securing a high degree of freedom in arranging logic unit cells and selecting a wiring channel region. To increase the efficiency of use of basic cells when creating logical unit cells, RAM cells, ROM cells, etc., and to reduce the channel width of transistors in the basic cell area to achieve high integration. Can be.

Note that a similar effect can be obtained even when the MOS forming section shown in FIG. 1 is configured to include the MOS forming section obtained by inverting the MOS forming section with respect to the axis in the X direction as a basic cell. it can.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention (a diagram showing a MOS forming portion constituting a basic cell included in a semiconductor integrated circuit of the present invention).

FIG. 2 is a diagram for explaining an effect of the present invention.

FIG. 3 is a diagram for explaining a conventional problem.

4A and 4B are logic circuits realized by the configurations of FIGS. 2A and 3A, and FIGS. 2B and 3B.
3 is a diagram showing a logic circuit realized by the configuration of FIG.

FIG. 5 is a plan view showing the entire first embodiment of the present invention.

FIG. 6 is a plan view showing an example of a semiconductor integrated circuit to be constituted by the first embodiment of the present invention.

FIG. 7 is a plan view showing a part of a basic cell region according to the first embodiment of the present invention.

FIG. 8 is a plan view showing one of the CMOS forming parts constituting the basic cell included in the first embodiment of the present invention.

9 is an equivalent circuit diagram of the CMOS forming section shown in FIG.

FIG. 10 is a sectional view taken along line AA of FIG. 4;

FIG. 11 is a sectional view taken along the line BB of FIG. 4;

FIG. 12 is a sectional view taken along the line CC of FIG. 4;

FIG. 13 is a sectional view taken along line DD of FIG. 4;

FIG. 14 is a diagram showing an example of usage of basic cells in the first embodiment of the present invention.

FIG. 15 is a circuit diagram illustrating an example of an inverter.

FIG. 16 is a plan view of an example in which the inverter shown in FIG. 12 is configured using the basic cells included in the first embodiment of the present invention.

FIG. 17 illustrates an example of a NAND circuit.

FIG. 18 is a plan view of an example in which the NAND circuit shown in FIG. 14 is configured using the basic cells included in the first embodiment of the present invention.

FIG. 19 is a circuit diagram illustrating an example of a NOR circuit.

FIG. 20 is a plan view showing an example in which the NOR circuit shown in FIG. 16 is configured using the basic cells included in the first embodiment of the present invention.

FIG. 21 is a circuit diagram showing an example of a 1-port RAM cell.

FIG. 22 is a plan view of an example in which the one-port RAM cell shown in FIG. 18 is configured using the basic cells included in the first embodiment of the present invention.

FIG. 23 is a circuit diagram showing an example of a two-port RAM cell.

FIG. 24 is a plan view of an example in which the two-port RAM cell shown in FIG. 20 is configured using the basic cells included in the first embodiment of the present invention.

FIG. 25 is a circuit diagram showing an example of a ROM.

FIG. 26 is a plan view of an example in which the ROM shown in FIG. 22 is configured using the basic cells included in the first embodiment of the present invention.

FIG. 27 is a diagram showing a modification of the first embodiment of the present invention.

FIG. 28 is a diagram showing a modification of the first embodiment of the present invention.

FIG. 29 is a diagram showing a modification of the first embodiment of the present invention.

FIG. 30 is a diagram showing a modification of the first embodiment of the present invention.

FIG. 31 is a plan view showing a part of a basic cell region according to a second embodiment of the present invention.

FIG. 32 is a plan view showing a part of a basic cell region according to a third embodiment of the present invention.

FIG. 33 is a plan view showing a part of a basic cell region according to a fourth embodiment of the present invention.

FIG. 34 is a plan view showing a part of a basic cell region according to a fifth embodiment of the present invention.

FIG. 35 is a plan view showing a part of a basic cell region according to a sixth embodiment of the present invention.

FIG. 36 is a view showing a modification of the sixth embodiment of the present invention.

FIG. 37 is a diagram showing a modification of the sixth embodiment of the present invention.

FIG. 38 is a diagram showing a modification of the sixth embodiment of the present invention.

FIG. 39 is a plan view showing a part of a basic cell region according to a seventh embodiment of the present invention.

FIG. 40 is a diagram showing an example of a composite LSI to which the present invention can be applied.

FIG. 41 is a plan view showing an example of a basic cell mounted on a conventional master slice type semiconductor integrated circuit.

FIG. 42 is a plan view showing another example of a basic cell mounted on a conventional master slice type semiconductor integrated circuit.

[Explanation of symbols]

 39 to 41 Wiring paths extending in the X direction 42, 43 Wiring paths extending in the Y direction 44 to 46 Impurity diffusion layers 47, 48 Gate electrode 55 to 60 Contact area

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-3279 (JP, A) JP-A-4-354370 (JP, A) JP-A-3-72678 (JP, A) 114717 (JP, A) JP-A-2-12964 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/118 H01L 27/04

Claims (9)

(57) [Claims] 1. A semiconductor device comprising: a first transistor and a second transistor arranged in a first direction, wherein the first transistor is directly connected to the first direction.
A first gate electrode (47) extending in a second direction
And the second transistor (62) extends in the second direction.
A second gate electrode (48), wherein the first gate electrode (47) has a first narrow portion (49).
A first wide portion (50) and a second wide portion (51)
And the width of the first wide portion (50) is
The second gate electrode (48) is wider than the width of the second wide portion (51), and the second gate electrode (48) has a second narrow portion (52).
A third wide portion (54) and a fourth wide portion having different widths across
(53) and the third wide portion (5
The width of 4) is wider than the width of the fourth wide portion (53), and the first wide portion (50) and the fourth wide portion (53).
Are formed between the second gate electrode (48) and the third wide electrode.
A semiconductor integrated circuit device, wherein the first and second portions are formed on the same side . Wherein <br/> gate contact formed on the first wide portion (50) (55, 56) is in a first wiring channel (42) under which extends in the first direction, the a second gate contact (59, 60) which is formed on the gate electrode (48) and the second wiring channel (43) under which extends the <br/> Ru said to spaced first wiring channels first direction 2. The semiconductor integrated circuit device according to claim 1, wherein: 3. A gate contact (55, 56) formed in said first wide portion (50 ) and said fourth wide portion.
Before the gate contact (57) formed in (53)
Serial arranged in one row first direction, said second wide portion (51)
Gate contact (57) formed on the substrate and the third width
Gate contacts (59, 6 ) formed in the wide portion (54)
0) The 請, characterized in that line up to the first direction
The semiconductor integrated circuit device according to claim 1. 4. Getokonta of part of <br/> gate contact formed on the first wide portion (50) (55, 56)
Transfected with Ri the wiring channel under near-extending in the second direction to the second gate contact formed on the wide portion (51) (57), a gate formed on said third wide portion (54) Contact
(59, 60) and the fourth contact
Contact (5) formed in the wide portion (54) of
8) a semiconductor integrated circuit device according to claim 1, wherein the wiring channel under near Rukoto extending in the direction of said second. 5. The first wide part (51) and the first wide part (51).
2. The semiconductor integrated circuit device according to claim 1 , further comprising a bent portion connecting the narrow portion (49) . 6. The fourth wide portion (54) and the second wide portion (54).
JP that has a bent portion that connects the narrow portion (52)
2. The semiconductor integrated circuit device according to claim 1, wherein: 7. The semiconductor device according to claim 1, wherein the first transistor is a first impurity.
And a diffusion layer and a second impurity diffusion layer, said second transistor is the second impurity diffusion layer and the third
Claim 1 乃, characterized in that it comprises an impurity diffusion layer
7. The semiconductor integrated circuit device according to the paragraph 6 . 8. and the first impurity diffusion layer and the second non
The semiconductor integrated circuit device according to claim 7 and pure things diffusion layer and the third impurity diffusion layer, characterized in that have a same width in the second direction. 9. The width must have three wiring channels.
When 9. The semiconductor integrated circuit device according to claim 8, wherein: