JP3210259B2 - Semiconductor storage device and storage system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable semiconductor memory device and a storage system, and more particularly to a multivalued semiconductor memory device and a storage system including the same.

[0002]

2. Description of the Related Art Demand for a nonvolatile semiconductor memory device has been greatly increased in recent years because it has an advantage that data is not erased even when power is turned off. A flash memory, which is a non-volatile semiconductor memory device that can be electrically erased in a batch, is different from a two-transistor type byte non-volatile semiconductor memory device in that the
A memory cell can be formed using a transistor. As a result, it is possible to reduce the size of the memory cell, and it is expected that a magnetic disk having a large capacity will be used as a substitute.

Among such flash memories, a NAND type EEPROM is known as being particularly advantageous for high integration. It has, for example, the following structure. That is, a plurality of memory cells having an n-channel FET MOS structure in which a floating gate serving as a charge storage layer and a control gate are stacked are arranged, for example, in a column direction, and the source and drain of adjacent cells among these cells are determined. Connect in series. By such a connection, a unit cell group (NAND cell) in which a plurality of memory cells are connected in series is formed, and the unit cell group is connected to the bit line as one unit.

FIGS. 74 (a) and 74 (b) show a NAND flash memory.
FIG. 1 shows a plan view and a circuit diagram of one NAND cell in a type EEPROM. FIG. 75 shows the NA shown in FIG.
FIG. 75 (a) is a longitudinal sectional view of the ND cell, and FIG.
FIG. 75A is a sectional view taken along line AA ′ in FIG.
(A) is a cross-sectional view taken along line BB ′.

1, an element region surrounded by an element isolation oxide film 12 is provided in a p-type well formed on a p-type substrate 11 or an n-type substrate.
A cell is formed. Here, eight memory cells M1 to M1
M8 are connected in series to form one NAND cell. In each memory cell having an n-channel FET MOS structure, a floating gate 14 (14-1, 14-2,..., 14) serving as a charge storage layer is provided on a p-type silicon semiconductor substrate 11 via a first gate insulating film 13. -8) is formed thereon, and the control gates 16 (16-1, 16-2,..., 16-8) are stacked thereon via the second gate insulating film 15. Further, the n-type diffusion layer 19 in the n-channel FET MOS structure is shared as a source on one of two adjacent memory cells and as a drain on the other, whereby each memory cell is connected in series.

On the drain side and source side of such a NAND cell, select gates 14-9, 16-9 and 14-10, 16 formed by the same process as the floating gate 14 and control gate 16 of the memory cell, respectively. -10 is provided. The selection gates 14-9, 16-9
And 14-10 and 16-10, the first layer and the second layer are electrically connected at desired portions (not shown). Further, the p-type silicon semiconductor substrate 1 on which the element has been formed in this manner.
1 is covered with an interlayer insulating film 17. A bit line 18 is provided on the interlayer insulating film 17,
The bit line 18 is in contact with the drain-side n-type diffusion layer 19 at one end of the NAND cell. That is, NAN
The drain side of the D cell is connected to select gates 14-9, 16-9.
Is connected to the bit line 18 via the. Further, on the source side of the NAND cell, an n-type diffusion layer 19 serving as a source line is formed via selection gates 14-10 and 16-10, and one source line is provided, for example, for every 64 bit lines in the row direction. The contact portion makes contact with the reference potential wiring.

On the other hand, the control gates 14 in the same row of a plurality of NAND cells arranged in the row direction are connected in common and arranged as control gate lines CG1, CG2,... CG8 running in the row direction. The lines are so-called word lines. That is, the control gate 14 of each memory cell
Are connected to word lines arranged in the row direction, respectively. Also, select gates 14-9, 16-9 and 14
−10 and 16-10 are also provided as select gate lines SG1 and SG2 running in the row direction, respectively.

FIG. 76 is a circuit diagram of a memory cell array of NAND cells. As shown in FIG. 76, control gate lines CG1, CG2,..., CG8 and select gate lines SG1, SG2 are continuously arranged in the row direction. Usually, one control gate line, that is, a memory cell group commonly connected to a word line forms a page (one page), and a set of drain-side select gate lines (select gates 14-9, 16-).
9) and the source side select gate line (select gate 14-1).
The set of pages sandwiched between (0, 16-10) is called a normal NAND block (1 NAND block) or a block (1 block). At this time, one page is composed of, for example, 256-byte (256 × 8) memory cells, and the memory cells for one page are written almost simultaneously. One block is composed of, for example, 2048 bytes (2048 × 8) memory cells, and the memory cells for one block are erased almost simultaneously.

A NAND type EEPR as described above will be described below.
The operation of the OM will be described. First, writing of data is generally performed in order from the memory cell farthest from the bit line. Specifically, the boosted write voltage Vpp (= 20 V) is applied to the control gate of the selected memory cell.
, While the control gate and the first select gate of the other unselected memory cells are each applied with an intermediate potential (= 1).
(Approximately 0 V). Further, 0 V ("0" write) or an intermediate potential ("1" write) is applied to the bit line according to the data. Thus, the potential of the bit line is transmitted to the selected memory cell. Therefore, the data is "0"
In this case, a high voltage is applied between the floating gate and the substrate in the selected memory cell, electrons are tunnel-injected from the substrate to the floating gate, and the threshold voltage of the memory cell transistor shifts in the positive direction. Conversely, when the data is "1", the threshold voltage does not change.

On the other hand, data is erased almost simultaneously in block units. That is, all the control gates and select gates in the block to be erased are set to 0 V, and the boosted potential VppE (= about 20 V) is applied to the p-type substrate or the n-type substrate and the p-type well formed on the n-type substrate. ). Further, the above-mentioned boosted potential VppE is applied to the control gate and the selection gate in the block which is not erased. As a result, electrons accumulated in the floating gate in the memory cells of the block to be erased are p
It is released to the p-type well of the type substrate or the n-type substrate, and the threshold voltage of the transistor shifts in the negative direction.

Regarding the data read operation,
After the bit line is precharged, the bit line is floated, the control gate of the selected memory cell is set to 0 V, the control gates and select gates of the other memory cells are set to the power supply voltage Vcc (for example, 3 V), and the source line is set to 0 V. Then, whether or not a current flows in the selected memory cell is detected by detecting the bit line. That is, if the data written in the selected memory cell is "0" (threshold voltage Vth> 0 of the transistor of the memory cell), the transistor is turned off and the bit line maintains the precharge potential. If 1 "(threshold voltage Vth <0 of the transistor of the memory cell), the memory cell is turned" ON "and the potential of the bit line drops from the precharge potential by ΔV. Therefore, data of the memory cell can be read by detecting such a bit line potential with a sense amplifier.

[0012]

Incidentally, even in the above-mentioned NAND type EEPROM, the cost performance is still far from the magnetic disk, and it is necessary to further increase the capacity and reduce the unit cost per bit. There is a strong demand. Therefore, recently, N
For an electrically rewritable nonvolatile semiconductor memory device such as an AND type EEPROM, a multi-value storage technology for storing three or more values of information in one memory cell has been proposed (for example, JP-A-7-93979). .

Here, the basic operation of a quaternary cell in which quaternary information is stored in one memory cell will be described as an example. First, FIG. 77 is a characteristic diagram showing the relationship between the threshold voltage of the transistor of the memory cell and the quaternary data for the quaternary cell. As shown, the state of data "1" in the quaternary cell is the same as the state after erasing and has, for example, a negative threshold value. On the other hand, the state of data "2" is, for example, 0.5 to 0.8 V, the state of data "3" is, for example, 1.5 to 1.8 V, and the state of data "4" is, for example, 2.5 to 2.5 V.
It has a threshold of ~ 2.8V.

Therefore, FIG. 77 is applied to the control gate of the memory cell.
When the read voltage VCG3R as shown in is applied, the transistor of the memory cell turns ON or OFF.
Can be detected as "1" or "2" or "3" or "4" as the data of the memory cell. Then, by applying the read voltages VCG4R and VCG2R, Thus, the data of the memory cell can be completely detected. At this time, the read voltages VCG2R, VCG3R, and VCG4R may be set to, for example, 0 V, 1 V, and 2 V, respectively.

Also, VCG2V, VCG3V, VCG4V in FIG.
Denotes a verify voltage. At the time of data writing, these verify voltages are applied to the control gate to detect the state of the memory cell and check whether or not the writing has been performed sufficiently. The verify voltages VCG2V, VCG3V,
VCG4V is, for example, 0.5V, 1.5V, 2.5V, respectively.
V.

FIG. 78 is a characteristic diagram showing an example of a write operation to a quaternary cell. FIG. 79 shows write data and a write destination memory cell when such a write is performed to a page of memory cells. FIG. 3 is a conceptual diagram showing the correspondence with the above. That is, the general 4
In the write operation to the value cell, as shown in FIG. 79, externally input write data is transferred from the start address to A0 and A1 in the memory cell MC1 and to the next A2 and A1.
3 is sequentially allocated to the memory cell MC2, and the next A4 and A5 are sequentially allocated to the memory cell MC3, and so on.
Data is written to each memory cell based on the 2-bit address assigned in this manner.

More specifically, for the memory cell MC1, for example, the data of A0 and A1 is temporarily stored in a data circuit corresponding to the memory cell MC1, and then, based on these write data, a write operation as shown in FIG. Is performed. Similarly, for the other memory cells MC2 to 128, "2" is written according to the data of A2 to A255,
Either “3” write or “4” write is performed, or the erase state (non-write state) “1” is held.

However, in such a write operation,
The time required for writing "3" is longer than that for "2" writing, which is equivalent to "0" writing for a binary cell, and much longer time is required for "4" writing. Also, in order to check whether or not these data have been sufficiently written, it is necessary to individually check each of "2" write, "3" write and "4" write. It is inevitable that the operation of the verify read performed for a long time is prolonged. Therefore, as described above, the time required for sufficiently writing data in all the memory cells for one page in which writing is performed almost simultaneously increases, in other words, the writing time generally defined by the time required for such page writing is increased. There is a problem that it becomes long.

Further, in an electrically rewritable nonvolatile semiconductor memory device such as a NAND type EEPROM, data destruction due to leakage of electrons stored in a floating gate as a charge storage layer may be a problem. However, the semiconductor memory device of multi-value storage is liable to cause such data destruction, and further improvement in reliability is required for practical use. That is, when data having a particularly high threshold level is written into a memory cell in a multi-valued semiconductor memory device, the electric charge between the substrate and the floating gate is strong, so that the charge stored in the floating gate leaks to the substrate. Tends to increase. Moreover, in a multi-valued semiconductor memory device, the state difference between data written in memory cells is often set to be small, and even a small change in the threshold level due to leakage of accumulated charges can cause data destruction. Would.

As described above, the conventional multi-level storage semiconductor memory device has not yet been put to practical use because the write time is longer than the binary one and the reliability is not sufficient. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor memory device of a multi-value memory capable of shortening a writing time and further improving reliability. An object of the present invention is to provide a storage system including a semiconductor storage device.

[0021]

In order to solve the above problems, the present invention employs the following configuration. (1) the "1" state has a first threshold level;
The “2” state has a second threshold level, the “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n, and n is greater than or equal to 3). , "M-1" in a semiconductor memory device having a memory cell storing an n value having an i-th threshold level. State, “m” state (m
Is a natural number of 2 or more), the memory cell is set to “1” based on write data input from outside the memory cell and data held by the memory cell.
, "K-1" state, or "k" state (k is a natural number greater than m).

(2) the "1" state has a first threshold level, the "2" state has a second threshold level,
The "3" state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) is n such that it has an i-th threshold level. A memory cell for storing a value, writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels, and each time a bias is supplied to the memory cell for a predetermined time. Verifying whether the threshold value of the memory cell has shifted between desired threshold levels and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts Means for providing a bias to the memory cell by the writing means, wherein the bias value increases stepwise according to the number of repetitions.
When the memory cell is at the threshold level of the “1” state, the memory cell is set to the “1” state, the “2” state, or the like based on write data input from outside the memory cell.
.., A first write mode for setting the threshold level to one of the “m−1” state and the “m” state (m is a natural number of 2 or more), and the “1” state and the “2” state of the memory cell ,…,
When the memory cell is at one of the threshold levels of the “m−1” state and the “m” state, the memory cell is set to “based on the write data input from outside the memory cell and the threshold level of the memory cell. 1 "state," 2 "state, ...," k-
A second write mode in which the threshold level is set to one of a 1 "state and a" k "state (k is a natural number larger than m), and the increase width of the bias value in the first write mode is ΔVpp1, where ΔVpp2 is the increase width of the bias value in the second write mode,
It is characterized by satisfying the relationship of ΔVpp1 <ΔVpp2.

(3) In (1) and (2), the “1” state is the erased state, and the “2” state, “3” state,.
The threshold distribution width of the “m−1” state and the “m” state is “m +”
1 "state," m + 2 "state, ...," k-1 "state,
It is characterized by being narrower than the threshold distribution width in the “k” state.

(4) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. In a semiconductor memory device having a memory cell for storing a value, the memory cell is in a “1” state, a “2” state,..., A “2 ^m−1 −1” state,
When one of the “2 ^m−1 ” states (m is a natural number satisfying n = 2 ^m ) is held, the memory cell is determined based on write data input from outside the memory cell and data held by the memory cell. In the “1” state, “2” state,.
The state is set to one of the “2 ^m −1” state and the “2 ^m ” state.

(5) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. A memory cell for storing a value, writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels, and a memory for supplying a bias to the memory cell for a predetermined time. Verifying whether the threshold value of the memory cell has shifted between desired threshold levels and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts Means, wherein when the supply of bias to the memory cell by the writing means is repeated, a bias value increases stepwise according to the number of repetitions.
When the memory cell is at the threshold level of the “1” state, the memory cell is set to a threshold of either the “1” state or the “2” state based on write data input from outside the memory cell. , "1" state, "2" state,..., "2"
^m-1 -1 "state," 2 ^m-1 "state (m is a natural number satisfying n = 2 ^m) in the case of any of the threshold levels,
Based on the write data input from outside the memory cell and the threshold level of the memory cell, the memory cell is set to a “1” state, a “2” state,..., A “2 ^m −1” state, a “2 ^m −1” state.
^m "state, wherein the threshold value is any one of the threshold levels in the" ^m "state, the increase in the bias value in the first write mode is ΔVpp1, and the bias value in the m-th write mode is ΔVppm increase
, The relationship of ΔVpp1 <ΔVppm is satisfied.

(6) In (5), the threshold distribution width of the "2" state is "2 ^m-1 +1" state, "2 ^m-1 +2" state,..., "2 ^m -1" state, It is characterized by being narrower than the threshold distribution width in the “2 ^m ” state. (7) In (4) and (5), the “1” state is the erase state, and the “2” state, “3” state,..., “2 ^m−1 −1”
State, the threshold distribution width in the "2 ^m-1 " state is "2 ^m-1 +
It is characterized in that it is narrower than the threshold distribution width of the "1" state, "2 ^m-1 +2" state,..., "2 ^m -1" state, and "2 ^m " state.

(8) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. In a semiconductor memory device having a memory cell for storing a value, when the memory cell holds the “1” state or the “2” state, it is determined based on write data input from outside the memory cell and data held by the memory cell. The memory cell is set to a "1" state, a "2" state, a "3" state or a "4" state.

(9) The "1" state has a first threshold level, the "2" state has a second threshold level,
The "3" state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) is n such that it has an i-th threshold level. A memory cell for storing a value, writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels, and each time a bias is supplied to the memory cell for a predetermined time. Verifying whether the threshold value of the memory cell has shifted between desired threshold levels and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts Means for providing a bias to the memory cell by the writing means, wherein the bias value increases stepwise according to the number of repetitions.
When the memory cell is at the threshold level of the “1” state, the memory cell is set to a threshold of either the “1” state or the “2” state based on write data input from outside the memory cell. A first write mode for setting the level of the memory cell to a threshold level of the "1" state or the "2"state; Based on the above, the memory cells are set in the “1” state, the “2” state, the “3” state.
A second write mode for setting the threshold level to one of the state and the "4" state, wherein the increase width of the bias value in the first write mode is ΔVpp1 and the second write mode is When the increment of the bias value is ΔVpp2, the relationship of ΔVpp1 <ΔVpp2 is satisfied.

(10) In (8) and (9), the “1” state is the erased state, and the threshold distribution width of the “2” state is the threshold distribution of the “3” state and the “4” state. It is characterized by being narrower than the width.

(11) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. In a semiconductor memory device having a memory cell for storing a value, the memory cell may be in a “1” state, a “2” state,.
When any of the “r” states (r is a natural number of 2 or more) is held, the memory cell is set to the “1” state based on write data input from outside the memory cell and data held by the memory cell. , "S-1" state or "s" state (s is a natural number larger than r), and the memory cells are in "1" state, "2" state,.
When holding either the “-1” state or the “s” state,
Based on the write data input from outside the memory cell and the data held by the memory cell, the memory cell is set to a “1” state, a “2” state,..., A “t−1” state, a “t” state.
One of the states (t is a natural number greater than s).

(12) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. A memory cell for storing a value, writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels, and a memory for supplying a bias to the memory cell for a predetermined time. Verifying whether the threshold value of the memory cell has shifted between desired threshold levels and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts Means, wherein when the supply of bias to the memory cell by the writing means is repeated, a bias value increases stepwise according to the number of repetitions.
The memory cells are in the “1” state, the “2” state,..., “R−1”
The threshold value of the memory cell based on the write data input from outside the memory cell and the threshold level of the memory cell when the threshold level is any of the state and the “r” state (r is a natural number of 2 or more). When the cell is in the “1” state, the “2” state,
, A j-th (j is 2) state which is a threshold level of one of the "s-1" state and the "s" state (s is a natural number larger than r)
, "S" state, "s-1" state, "1" state, "2" state,.
If the threshold level is any of the states, the memory cell is set to a "1" state, a "2" state,... Based on the write data input from outside the memory cell and the threshold level of the memory cell. , “T−1” state, “t” state (t
A natural number greater than s), and a (j + 1) th write mode in which the threshold level is increased by ΔVpp in the jth write mode.
j, ΔVpp (j + 1) where ΔVpp (j + 1) is the increase width of the bias value in the (j + 1) th write mode.
Vpp (j + 1) is satisfied.

(13) In (11) and (12), "r +
1 "state," r + 2 "state, ...," s-1 "state,
The threshold distribution width of the “s” state is “s + 1” state, “s +
It is characterized in that it is narrower than the threshold distribution width of the “2” state,..., “T−1” state, and “t” state (14) In (11) to (13), the “1” state is erased. , “R−1” state, “r” state, the threshold distribution width is “r + 1” state,
It is characterized in that it is narrower than the threshold distribution width in the “r + 2” state,..., “S−1” state, and “s” state.

(15) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. In a semiconductor memory device having a memory cell for storing a value, the memory cell is in a "1" state, a "2" state,..., A "2 ^k-1 -1" state,
When any of the “2 ^k−1 ” states (k is a natural number of 2 or more) is held, the memory cell is set to “1” based on write data input from outside the memory cell and data held by the memory cell. State, “2” state, ..., “2 ^k −
1 ”state or“ 2 ^k ”state, and the memory cell is in“ 1 ”state,“ 2 ”state,...,“ 2 ^k −1 ”state,“ 2 ^k
k ”state, the memory cell is set to a“ 1 ”state based on write data input from outside the memory cell and data held by the memory cell.
.., “2 ^{k + 1} −1” state, or “2 ^{k + 1} ” state.

(16) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. A memory cell for storing a value, writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels, and a memory for supplying a bias to the memory cell for a predetermined time. Verifying whether the threshold value of the memory cell has shifted between desired threshold levels and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts Means, wherein when the supply of bias to the memory cell by the writing means is repeated, a bias value increases stepwise according to the number of repetitions.
The state of the memory cell is “1” state, “2” state,..., “2 ^k−1 −
When the threshold level is any of the 1 ”state and the“ 2 ^k−1 ”state (k is a natural number of 2 or more), the write data input from outside the memory cell and the threshold level of the memory cell The memory cell is set to a “1” state based on
The k-th write mode for setting any one of the threshold levels of the “2” state,..., “2 ^k −1” state and “2 ^k ” state, and the memory cell in the “1” state, “2” state, …, “2 ^k
-1 "state,""when any of these threshold level states, based on a threshold level of the write data and the memory cell input from the outside of the memory cell, the memory cell" 2 ^k 1 "State," 2 "state, ...," 2 ^{k + 1-}
1) state and a (k + 1) -th write mode for setting the threshold level to ^{one of} the “2 ^{k + 1} ” state, and the increase in the bias value in the k-th write mode is ΔV
ppk, where ΔVpp (k + 1) is the increment of the bias value in the (k + 1) th write mode,
It is characterized by satisfying the relationship of ΔVpp (k + 1).

(17) In (15) and (16), "2 ^k-1 +
1 ”state,“ 2 ^k−1 +2 ”state,...,“ 2 ^k −1 ”state,“ 2 ^k ”state threshold distribution width is“ 2 ^k +1 ”state,“ 2 ^k +2 ”state,. , “2 ^{k + 1} −1” state, “2 ^{k + 1} −1”
It is characterized by being narrower than the threshold distribution width of the ( ^{k + 1} ) state. (18) In (15) to (17), the “1” state is the erased state, the “2” state, and “3”. State, ..., "2 ^k-1 -1"
State, the threshold distribution width of the "2 ^k-1 " state is "2 ^k-1 +
It is characterized in that it is narrower than the threshold distribution width of the “1” state, “2 ^k−1 +2” state,..., “2 ^k −1” state, and “2 ^k ” state.

(19) In (15) to (18), the “1” state is the erased state, and the threshold distribution width of the “2” state is “3” state, “4” state,. ^k-1 -1 "state,
It is characterized by being narrower than the threshold distribution width in the “2 ^k−1 ” state.

(20) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) is n In a semiconductor memory device provided with a memory cell for storing a value, the memory cell becomes "1" when a first logic level is input and "2" when a second logic level is input in a first write operation. State, and the k-1 (k is a natural number of 2 or more)
In the k-th write operation, the memory cell in the “A” state as a result of the write operation enters the “A” state when the 2k−1 logical level is input, and “A + 2 ^k− ” when the 2k logical level is input. ¹ "state.

(21) The "1" state has a first threshold level, the "2" state has a second threshold level,
The "3" state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) is n such that it has an i-th threshold level. A memory cell for storing a value, writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels, and each time a bias is supplied to the memory cell for a predetermined time. Verifying whether the threshold value of the memory cell has shifted between desired threshold levels and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts Means for providing a bias to the memory cell by the writing means, wherein the bias value increases stepwise according to the number of repetitions.
At the time of the first write operation, the memory cell goes into the “1” state when the first logic level is input, goes into the “2” state when the second logic level is input, and becomes k−1 (k is 2 or more). In the k-th write operation, the memory cell in the “A” state as a result of the (natural number) write operation enters the “A” state when the 2k−1 logical level is input, and “A + 2” when the 2k logical level is input. ^k-1 "state and the first
When the increase width of the bias value in the first write mode in which the write operation is performed is ΔVpp1, and the increase width of the bias value in the k-th write mode in which the k-th write operation is performed is ΔVppk, ΔVpp1 <ΔV
It is characterized by satisfying the relationship of ppk.

(22) In (20) and (21), the "1" state is the erased state, and the threshold distribution width of the "2" state is larger than the threshold distribution width of the "A + 2 ^k-1 " state. Is also characterized by being narrow. (23) In the constitutions (20) and (21), the threshold distribution width in the “A” state is narrower than the threshold distribution width in the “A + 2 ^k−1 ” state.

(24) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. In a semiconductor memory device provided with a memory cell for storing a value, the memory cell becomes "1" when a first logic level is input and "2" when a second logic level is input in a first write operation. State and the result of the first write operation is “1”
In the second write operation, the memory cell that is in the state becomes “1” when a third logical level is inputted, and becomes “3” when a fourth logical level is inputted. As a result of the first write operation, In the second write operation, the memory cell in the “2” state enters the “2” state when the third logical level is input, and enters the “4” state when the fourth logical level is input. .

(25) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. A memory cell for storing a value, writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels, and a memory for supplying a bias to the memory cell for a predetermined time. Verifying whether the threshold value of the memory cell has shifted between desired threshold levels and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts Means, wherein when the supply of bias to the memory cell by the writing means is repeated, a bias value increases stepwise according to the number of repetitions.
At the time of the first write operation, the memory cell goes into the “1” state when the first logical level is input, goes into the “2” state when the second logical level is input, and as a result of the first write operation, “1”. In the second write operation, the memory cell that is in the state becomes the “1” state when the third logic level is inputted, and becomes the “3” state when the fourth logic level is inputted,
In the second write operation, the memory cell which is in the “2” state as a result of the first write operation becomes the “2” state when the third logical level is input, and becomes the “4” state when the fourth logical level is input. In the first write mode in which the first write operation is performed, the increase width of the bias value is ΔVpp1, and in the second write mode in which the second write operation is performed, the increase width of the bias value is ΔVpp1.
When 2, the relationship of ΔVpp1 <ΔVpp2 is satisfied.

(26) In (24) and (25), the "1" state is the erased state, and the threshold distribution widths of the "2" state are the "3" state and the "4" state. It is characterized by being narrower than the width. (27) In the constitutions (24) to (26), the third threshold level is larger than the second threshold level. (28) In (27), the voltage difference between the threshold distribution in the “3” state and the threshold distribution in the “4” state is different from the threshold distribution in the “2” state and the threshold distribution in the “3” state. It is characterized by being equal to the voltage difference between the threshold distributions. (29) In (27), the voltage difference between the threshold distribution in the “3” state and the threshold distribution in the “4” state is different from the threshold distribution in the “2” state and the threshold distribution in the “3” state. It is characterized by being larger than the voltage difference between the threshold distributions. (30) In any one of (24) to (26), the third threshold level is smaller than the second threshold level.

(31) In (30), the voltage difference between the threshold distribution in the “2” state and the threshold distribution in the “4” state is
It is characterized by being equal to the voltage difference between the threshold distribution in the "3" state and the threshold distribution in the "2" state. (32) In (30), the voltage difference between the threshold distribution in the “2” state and the threshold distribution in the “4” state is different from the threshold distribution in the “3” state and the threshold distribution in the “2” state. It is characterized by being larger than the voltage difference between the threshold distributions. (33) the "1" state has a first threshold level;
The “2” state has a second threshold level, the “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n, and n is greater than or equal to 4). Is a natural number of a semiconductor memory device having a memory cell storing an n value having an i-th threshold level. In the first write operation, when the first logic level is input to the memory cell, "1" State when the second logic level is input, the state changes to the "2" state, and the memory cell which is in the "1" state as a result of the first write operation has the third logic level at the time of the second write operation. When input, the state becomes "1" based on the "1" data held in the memory cell and the third logic level, and when the fourth logic level is input, the "1" data held in the memory cell and the fourth logic level are input. The state becomes “3” based on the logic level, and the first write When the third logic level is input during the second write operation, the memory cell in the “2” state as a result of the only operation receives “2” data held in the memory cell and “2” based on the third logic level. State, and when the fourth logic level is input, the state changes to the "4" state based on the "2" data held in the memory cell and the fourth logic level.

(34) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. A semiconductor memory device comprising: a memory cell for storing a value; and a data circuit for holding write data of the memory cell.
When the write data is at the first logical level, the memory cell is set to the "1" state in response to the first write data held in the data circuit, and the write data is changed to the second logical level. In this case, the state changes to the “2” state, and after the data circuit holds the second write data input from outside the memory cell and the data read from the memory cell, the memory cell changes to “1”. When the data circuit holds that the memory cell is in the state and the second write data is at the third logic level, the memory cell is in the “1” state, the memory cell is in the “1” state and the second When the data circuit holds that the write data is at the fourth logic level, the memory cell is in the "3" state, the memory cell is in the "2" state, and the second write data is in the "3" state. If the data circuit holds that the data cell is at the third logic level, the memory cell is in the "2" state, the memory cell is in the "2" state and the second write data is at the fourth logic level. , When the data circuit holds the data, the memory cell is in the “4” state.

(35) In the constitutions (24) to (34), the first logical level is equal to the third logical level, and the second logical level is equal to the fourth logical level. (36) The "1" state has a first threshold level,
The “2” state has a second threshold level, the “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n, and n is greater than or equal to 3). Is a natural number of a semiconductor memory device having a memory cell storing an n value having an i-th threshold level, and a data circuit holding write data of the memory cell, wherein the memory cell is “1”. State, "2" state, ..., "m-1" state, "m" state
When a state (m is a natural number of 2 or more) is held, the data circuit holds write data input from outside the memory cell and data held in the data circuit after holding data read from the memory cell. , The "1" state, the "2" state,..., The "k-1" state, and the "k" state (k is a natural number larger than m).

(37) The "1" state has a first threshold level, the "2" state has a second threshold level,
The "3" state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) is n such that it has an i-th threshold level. A memory cell for storing a value, a data circuit for holding write data of the memory cell, and writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels. Each time a bias is supplied to the memory cell for a predetermined time, detecting whether or not the threshold value of the memory cell has shifted between desired threshold levels; Verifying means for repeating supply of a bias to the memory cell by the writing means, and when the supply of bias to the memory cell by the writing means is repeated, a bias value is varied according to the number of repetitions. In a semiconductor memory device that increases in number, when a memory cell is at a threshold level of a "1" state, after a data circuit holds write data input from outside the memory cell, the data held in the data circuit Based on the threshold value of any one of the “1” state, “2” state,..., “M−1” state, and “m” state (m is a natural number of 2 or more). 1 write mode, and the memory cell is in a “1” state, a “2” state,
.., When the threshold level is one of the “m−1” state and the “m” state, the data circuit reads write data input from outside the memory cell and data read from the memory cell. After holding, the memory cell is set to a “1” state based on the data held in the data circuit.
"2" state, ..., "k-1" state, "k" state (k is m
A larger natural number) and a second write mode in which the threshold value is increased by ΔVpp1 in the first write mode, and the bias value in the second write mode. Where ΔVpp1 <ΔVpp2 is satisfied, where ΔVpp2 is the increase width.

(38) In (36) and (37), the “1” state is the erase state, and the “2” state, “3” state,.
The threshold distribution width of the “m−1” state and the “m” state is “m +”
1 "state," m + 2 "state, ...," k-1 "state,
It is characterized by being narrower than the threshold distribution width in the “k” state.

(39) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. In a semiconductor memory device including a memory cell for storing a value and a data circuit for holding write data of the memory cell, when the memory cell holds a “1” state or a “2” state,
After the data circuit holds the write data input from outside the memory cell and the data read from the memory cell, based on the data held in the data circuit,
The memory cell is set to a "1" state, a "2" state, a "3" state or a "4" state.

(40) The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is an n-th state having an i-th threshold level. A memory cell for storing a value, a data circuit for holding write data of the memory cell, and writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels. Each time a bias is supplied to the memory cell for a predetermined time, detecting whether or not the threshold value of the memory cell has shifted between desired threshold levels; Verifying means for repeating supply of a bias to the memory cell by the writing means, and when the supply of bias to the memory cell by the writing means is repeated, a bias value is varied according to the number of repetitions. In a semiconductor memory device that increases in number, when a memory cell is at a threshold level of a "1" state, after a data circuit holds write data input from outside the memory cell, the data held in the data circuit Is set to the “1” state or “2” based on
A first write mode in which one of the states is set to the threshold level; and a case in which the data circuit is connected to the outside of the memory cell when the memory cell is in one of the "1" state and the "2" state. After holding the write data input from the memory cell and the data read from the memory cell, the memory cell is set to the “1” state, the “2” state, and the “3” state based on the data held in the data circuit. Or a second write mode for setting any one of the threshold levels in the “4” state, wherein the increase width of the bias value in the first write mode is ΔVpp1, and the bias in the second write mode is When the increment of the value is ΔVpp2, the relationship of ΔVpp1 <ΔVpp2 is satisfied.

(41) In (39) and (40), the “1” state is the erased state, and the threshold distribution width of the “2” state is the threshold distribution of the “3” state and the “4” state. It is characterized by being narrower than the width. (42) In any one of the constitutions (1) to (41), the memory cells share a word line to form a memory cell array.

(43) In a semiconductor memory device provided with a memory cell capable of storing data of a plurality of bits and a data circuit for holding write data of the memory cell, a memory cell of When data to be written to the memory cell is upper bit data and data to be written to the memory cell later is lower bit data, the first write data is input to the data circuit from outside the memory cell and temporarily stored. The write operation of the upper bit data is performed, and after the write operation of the upper bit data is completed, the second write data is input to the data circuit from outside the memory cell and temporarily stored, A lower bit data write operation is performed.

(44) In (43), the write operation of the lower-order bit data includes the second write data input from outside the memory cell and the upper-order data read from the memory cell by the data circuit. It is performed after holding bit data.

(45) A memory cell capable of storing a plurality of bits of data, and a data circuit for holding write data of the memory cell, wherein a memory cell group consisting of a predetermined plurality of memory cells is used as a write unit. In the semiconductor memory device for forming a page, the data of the plurality of bits that is first written to the memory cell is the upper bit data, and the data that is later written to the memory cell is the lower bit data, and the page is formed. In writing the plurality of bits of data into each of the memory cell groups, the operation of writing the upper bit data is referred to as an upper page write operation, and the operation of writing the lower bit data is referred to as a lower page write operation. When the above, for each of the memory cell groups forming the page, Page write operation, characterized in that the write operation of the lower page is started after completion.

(46) In (45), after the first write data is inputted to the data circuit from outside the memory cell and temporarily stored, the write operation of the upper page is performed, and then the data circuit After the second write data is inputted from outside the memory cell and temporarily stored, the write operation of the lower page is performed. (47) In (45) and (46), a plurality of data circuits are provided corresponding to a memory cell group including a plurality of memory cells.

(48) A memory cell capable of storing a plurality of bits of data, a data circuit holding write data of the memory cell, and writing to the memory cell in accordance with the write data held in the data circuit Writing means for performing an operation; detecting whether or not write data held in the data circuit has been written to the memory cell; and determining whether or not desired writing has been performed; A verifying means for repeating a write operation to the cell, wherein the data of the plurality of bits, which is first written to the memory cell, is data of upper bits,
When what is to be written to the memory cell later is the lower bit data, the higher bit data is written to the memory cell by the writing means, and the verifying means detects that the desired writing has been performed. Thereafter, a writing operation to the memory cell by the writing means is performed on the lower bit data.

(49) In (48), in the writing operation of the lower bit data, after the upper bit data is written, the data circuit may write the write data inputted from outside the memory cell and the memory circuit. This is performed after holding the upper bit data read from the cell. (50) A memory cell capable of storing a plurality of bits of data, a data circuit holding write data of the memory cell, and performing a write operation to the memory cell according to the write data held in the data circuit Writing means for detecting whether or not write data held in the data circuit has been written to the memory cells, and writing data to the memory cells by the writing means until it is detected that desired writing has been performed; Verifying means for repeating a write operation, wherein a memory cell group consisting of a predetermined plurality of memory cells forms a page as a write unit; Data to be written to the memory cells, In writing the plurality of bits of data into each of the memory cells forming the page, the operation of writing the data of the upper bit is an operation of writing the data of the upper page, and the writing of the data of the lower bit. When the operation to be performed is the write operation of the lower page, the write operation of the upper page is performed by the write unit for each of the memory cell groups forming the page, and the desired write is performed in all the memory cells of the memory cell group. After the verifying means detects that the writing has been performed, a writing operation of the lower page is performed by the writing means.

(51) In (50), the lower page write operation is performed after the upper page write operation.
It is performed after the data circuit holds write data inputted from outside the memory cell and data read from the memory cell. (52) In the items (50) and (51), a plurality of the data circuits are provided corresponding to a memory cell group including a plurality of memory cells.

(53) In a semiconductor memory device in which a memory cell group consisting of a predetermined plurality of memory cells forms a page serving as a writing unit, the memory cell has an n value (n is an integer) capable of storing a plurality of bits of data. 3 or more natural number) storage memory cell, and when a plurality of bits of data are written to the memory cell by a p-th (p is a natural number of 1 or more) write operation and a (p + 1) -th write operation, the first page The plurality of bits of the first memory cell
The first bit is set to p-th based on the first write data.
After performing a p-th write operation on the first bit of the plurality of bits of the second memory cell belonging to the second page based on second write data, and then performing the first write operation on the first memory cell. Of the plurality of bits of the memory cell
Of the p + th bit based on the third write data in the second bit of
1 is performed.

(54) A memory cell capable of storing a plurality of bits of data, a data circuit holding write data of the memory cell, and writing to the memory cell in accordance with the write data held in the data circuit Writing means for performing an operation; and detecting whether or not write data held in the data circuit has been written to the memory cell, and determining whether the desired writing has been performed. A verifying means for repeating a write operation to a cell, wherein a memory cell group including a plurality of predetermined memory cells forms a page as a write unit;
P-th (p is a natural number of 1 or more) write operation and p +
When by one write operation of the plurality of bits of data writing into the memory cell, the first based on the first write data to the first bit of said plurality of bits of the first memory cells belonging to the first page p write operation, and the plurality of second memory cells belonging to the second page
After performing the p-th write operation on the first bit of the bits based on the second write data, the third bit is set on the second bit of the plurality of bits of the first memory cell.
Is performed based on the write data.

(55) In (53) and (54), the second bit of the plurality of bits of the first memory cell is selected.
Performing a ( p + 1) -th write operation on a second bit of the plurality of bits of the second memory cell based on a fourth write data subsequent to a (p + 1) -th write operation on the second memory cell It is characterized by. In (56) (54), the said first memory cell
The p result of write operation into one bit, after that the desired writing is performed to the first bit of the first memory cell is detected by the verifying means, said second memory by said writing means P -th to first bit of cell
Is performed. In (57) (54), first of the second memory cell
The p result of write operation into one bit, after that the desired writing is performed to the first bit of the second memory cell is detected by the verifying means, said first memory by said writing means P -th to second bit of cell
A +1 write operation is performed.

(58) In (53) to (57), the p-th
Is the first write operation, and the p-th
The writing operation of +1 is a second writing operation. (59) In (58), in the memory cell, the “1” state has a first threshold level, the “2” state has a second threshold level, and the “3” state is A third threshold level, the "i" state (where i is a natural number less than or equal to n and n
Is a natural number of 3 or more) stores an n value having the i-th threshold level. When the memory cell is at the threshold level of the “1” state, an input from the outside of the memory cell is performed. The first write is performed based on the write data to be written, and the memory cells are set to a “1” state, a “2” state,. A first write mode for setting any one of the threshold levels,
.., The "m-1" state, or the "m" state, the second write is performed, and the write data input from outside the memory cell and the threshold value of the memory cell On the basis of the level, the memory cell is set in a “1” state, a “2” state,..., A “k−1” state, a “k” state.
A second write mode for setting one of the threshold levels in a state (k is a natural number greater than m).

(60) In any one of (53) to (57), the memory cell has a first threshold level when the state is "1".
The “2” state has a second threshold level, the “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n, and n is greater than or equal to 4). Is a natural number that stores an n value having an i-th threshold level,
The memory cells are in the “1” state, the “2” state,..., “R−1”
The p-th write is performed when the threshold level is any one of the state and the “r” state (r is a natural number of 2 or more), and the write data input from outside the memory cell and the threshold of the memory cell are written. .., “S−1” state,..., “2” state,.
The j-th (j is a natural number of 2 or more) write mode in which one of the threshold levels is in the “s” state (s is a natural number greater than r), and the memory cell is in the “1” state, the “2” state,
.., The "s + 1" state or the "s" state, the (p + 1) th write is performed, and the write data input from outside the memory cell and the threshold value of the memory cell Based on the level, the memory cells are set to a “1” state, a “2” state,.
And a (j + 1) th write mode for setting any threshold level in a “t” state (t is a natural number greater than s).

(61) In a semiconductor memory device in which a memory cell group consisting of a predetermined plurality of memory cells forms a page serving as a writing unit, the memory cell has an n value (n is an integer) capable of storing a plurality of bits of data. 3 or more natural number) storage memory cell, and when a plurality of bits of data are written to the memory cell by a p-th (p is a natural number of 1 or more) write operation and a (p + 1) -th write operation, the first page Of the plurality of bits of the memory cell group to which the
The p-th write operation is performed on the first bit based on the first write data, and the p-th write operation is performed on the first bit of the plurality of bits of the memory cell group belonging to the second page based on the second write data. After performing the write operation of
The plurality of bits of the memory cell group belonging to the first page
And performing a (p + 1) -th write operation on the second bit of the data based on the third write data.

(62) A memory cell capable of storing a plurality of bits of data, a data circuit holding write data of the memory cell, and writing to the memory cell in accordance with the write data held in the data circuit Writing means for performing an operation; detecting whether or not write data held in the data circuit has been written to the memory cell; and determining whether or not desired writing has been performed; A verifying means for repeating a write operation to a cell, wherein a memory cell group including a plurality of predetermined memory cells forms a page as a write unit;
P-th (p is a natural number of 1 or more) write operation and p +
1, when writing a plurality of bits of data into the memory cell by the write operation 1, a first bit group of the plurality of bits of the plurality of bits of the memory cell belonging to the first page is set based on the first write data. Perform a write operation,
Of the plurality of bits of the memory cell group belonging to the second page.
After the first bit of the out was performed first p write operation based on the second write data, a second bit of said plurality of bits of memory cells belonging to the first page
And performing a (p + 1) -th write operation based on the third write data.

(63) In (61) and (62), the plurality of bits of the memory cell group belonging to the first page may be used.
Following the p + 1 of the write operation to the second bit of the previous memory cell group belonging to the second page
The p + 1-th write operation is performed on the second bit of the plurality of bits based on the fourth write data. (64) In (62), as a result of the p-th write operation to the first bit of the memory cell group belonging to the first page, all of the memory cells in the memory cell group forming the first page may be written . After the verifying means detects that the desired writing has been performed with one bit , the write means selects the memory cell group belonging to the second page belonging to the second page .
A p-th write operation to one bit is performed.

(65) In (62), as a result of the p-th write operation to the memory cell group belonging to the second page,
After the verifying unit detects that the desired writing has been performed in all the memory cells in the memory cell group forming the second page, the writing unit writes the desired data to the memory cell group belonging to the first page. A writing operation of p + 1 is performed. (66) In (61) to (65), the p-th write operation is a first write operation, and the (p + 1) -th write operation is a second write operation.

(67) In (66), in the memory cell, the "1" state has the first threshold level, and the "2" state
The state has a second threshold level and the "3" state is the third threshold level.
The "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) stores an n value having an i-th threshold level. When the memory cell is at the threshold level of "1" state, the first write is performed based on write data input from outside the memory cell, and the memory cell is set to "1".
, "M-1" state, "m" state (m is a natural number of 2 or more), and a first write mode in which the memory cell is set to "1" The second write is performed when the threshold level is any of the "state", "2" state,..., "M-1" state, and "m" state. Based on the data and the threshold level of the memory cell, the memory cell is set to "1" state, "2" state,.
And a second write mode for setting the threshold level to one of a state and a “k” state (k is a natural number greater than m).

(68) In any one of the constitutions (61) to (65), the memory cell has a first threshold level in the "1" state.
The “2” state has a second threshold level, the “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n, and n is greater than or equal to 4). Is a natural number that stores an n value having an i-th threshold level,
The memory cells are in the “1” state, the “2” state,..., “R−1”
The p-th write is performed when the threshold level is any one of the state and the “r” state (r is a natural number of 2 or more), and the write data input from outside the memory cell and the threshold of the memory cell are written. .., “S−1” state,..., “2” state,.
The j-th (j is a natural number of 2 or more) write mode in which one of the threshold levels is in the “s” state (s is a natural number greater than r), and the memory cell is in the “1” state, the “2” state,
.., The "s + 1" state or the "s" state, the (p + 1) th write is performed, and the write data input from outside the memory cell and the threshold value of the memory cell Based on the level, the memory cells are set to a “1” state, a “2” state,.
And a (j + 1) th write mode for setting any threshold level in a “t” state (t is a natural number greater than s).

(69) In (61) to (68), each of the p-th memory cells belonging to all pages in the device may be referred to as the p-th memory cell group.
Is performed, the (p + 1) -th write operation to the memory cell group belonging to the first page is performed. (70) In (53) to (69), the number of times the (p + 1) th write operation is performed is stored for each page, and the write order is determined based on the number of times. (71) In the memory cell group of (43) to (70), a predetermined plurality of memory cells share one word line, and a memory cell group including a plurality of predetermined memory cells sharing the word line. Form a page serving as a writing unit.

(72) In a storage system including a plurality of semiconductor memory devices each having a memory cell capable of storing a plurality of bits of data as a storage unit, the plurality of memory cells are provided for each semiconductor memory device. A memory cell group including a plurality of memory cells forms a page serving as a write unit, and a plurality of bits of data are written to the memory cell by a p-th (p is a natural number of 1 or more) write operation and a p + 1-th write operation At this time, the plurality of bits of the memory cell group belonging to the page in the first semiconductor memory device are
A p-th write operation is performed on the first bit of the memory cell based on the first write data, and the plurality of bits of the memory cell group belonging to the page in the second semiconductor memory device are written.
The first bit based on the second write data
After performing the write operation of the plurality of bits of the memory cells belonging to the page in the first semiconductor memory device.
It is characterized in that a (p + 1) -th write operation is performed based on the third write data in the second bit . (73) In (72), the plurality of bits of a memory cell group belonging to a page in the first semiconductor memory device are stored.
Chino subsequent to the p + 1 of the write operation to the second bit, based on the fourth write data to the second bit of said plurality of bits of memory cells belonging to a page within the second semiconductor memory device It is characterized in that a (p + 1) -th write operation is performed.

(74) In (73), after performing the (p + 1) -th write operation only on the memory cell group belonging to a part of the page in the first semiconductor memory device, Memory cells belonging to page p
A +1 write operation is performed. (75) In any of (72) to (74), the p-th write operation is a first write operation, and the (p + 1) -th write operation is a second write operation.

(76) In (75), in the memory cell, the "1" state has the first threshold level, and the "2" state
The state has a second threshold level and the "3" state is the third threshold level.
The "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) stores an n value having an i-th threshold level. When the memory cell is at the threshold level of "1" state, the first write is performed based on write data input from outside the memory cell, and the memory cell is set to "1".
, "M-1" state, "m" state (m is a natural number of 2 or more), and a first write mode in which the memory cell is set to "1" The second write is performed when the threshold level is any of the "state", "2" state,..., "M-1" state, and "m" state. Based on the data and the threshold level of the memory cell, the memory cell is set to "1" state, "2" state,.
And a second write mode for setting the threshold level to one of a state and a “k” state (k is a natural number greater than m).

(77) In each of (72) to (74), the memory cell has a first threshold level when the state is "1".
The “2” state has a second threshold level, the “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n, and n is greater than or equal to 4). Is a natural number that stores an n value having an i-th threshold level,
The memory cells are in the “1” state, the “2” state,..., “R−1”
The p-th write is performed when the threshold level is any one of the state and the “r” state (r is a natural number of 2 or more), and the write data input from outside the memory cell and the threshold of the memory cell are written. .., “S−1” state,..., “2” state,.
The j-th (j is a natural number of 2 or more) write mode in which one of the threshold levels is in the “s” state (s is a natural number greater than r), and the memory cell is in the “1” state, the “2” state,
.., The "s + 1" state or the "s" state, the (p + 1) th write is performed, and the write data input from outside the memory cell and the threshold value of the memory cell Based on the level, the memory cells are set to a “1” state, a “2” state,.
And a (j + 1) th write mode for setting any threshold level in a “t” state (t is a natural number greater than s).

(78) In (72) to (77), after the p-th write operation is performed on the memory cell groups belonging to all pages in all the semiconductor memory devices forming the storage section, The (p + 1) -th write operation is performed on a memory cell group belonging to a page in one semiconductor memory device. (79) In any one of the constitutions (72) to (78), further comprising means for controlling an operation of the semiconductor memory device. (80) In the constitution (79), the means for controlling the operation of the semiconductor memory device controls a writing order to each memory cell group forming the page. (81) In the constitution (80), the writing order is determined in page units. (82) In (81), the writing order is determined for each device.

According to the present invention configured as described above,
For example, in the case of a quaternary cell, the first write operation writes the memory cell to the “1” state or the “2” state, and the second write operation keeps the “1” state as it is or sets the memory cell to the “3” state. By writing, and further holding the “2” state as it is or writing to the “4” state, quaternary writing can be performed. That is, quaternary writing can be performed by two writing operations.

Therefore, the first write operation is a binary cell,
The second write operation can be performed almost in the same manner as the ternary cell. As a result, the writing circuit is simplified and the writing speed is increased. Similarly, for multi-level cells other than the four-level cells, it is possible to speed up the writing by dividing the data in the memory cells into a plurality of bits and performing the respective writing operations.

[0077]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. [First Embodiment] FIG. 1 is a diagram for explaining an EEPROM according to a first embodiment of the present invention, and is a diagram showing memory cells connected to one word line. Unlike the conventional four-valued memory cell, in FIG. 1, of the write data input from the outside, A0 is assigned to the memory cell MC1, the next A1 is assigned to the memory cell MC2, and the next A2 is assigned to the memory cell MC3 from the start address. Address A0
The data of A127 is written.

<Write to upper page> The above-mentioned addresses A0 to A127 constitute the first page (upper page). FIGS. 2 and 3 show how the writing is performed. If A0 is low, the memory cell keeps the erased state ("1"), and if A0 is high, the memory cell is written with "2". As described above, writing to the upper page (addresses A0 to A127) is performed at a high speed as in the case of the binary memory cell.

<Writing to lower page> The data of addresses A128 to A255 to be input next form the second page (lower page). Address A128 is stored in memory cell M
C1 and the next A129 in the memory cell MC2, and the next A129
130 to the memory cell MC3, and so on.
Write the data from 8 to A255. 3 and 4 show the state of writing. Before writing the lower page, the data of the upper page has already been written to the memory cells. Therefore, before writing the lower page, the state of the memory cell is "1" state or "2" state as shown in FIG. Thereafter, if A128 is Low, for example, the memory cell is not written, and maintains the "1" state or the "2" state.

On the other hand, if A128 is High, the memory cell is written as shown in FIGS. That is, the memory cell in the “1” state before writing is written to the “3” state, and the memory cell in the “2” state is written to the “4” state. As can be seen from FIG. 4, writing from the “1” state to the “3” state or changing from the “2” state to the “4” state
Since writing to the state has a smaller threshold change amount than the conventional writing method (FIG. 78), high-speed writing is performed.

Next, reading will be described with reference to FIG. <Read of upper page> First page (upper page)
Is read, it is determined whether the memory cell is in the “1” state or the “3” state, or in the “2” state or the “4” state. In this case, the voltage between the "3" state and the "2" state (V in FIG. 5) is applied to the control gate of the memory cell.
1) is applied. When the memory cell transistor is turned on, it is known that the memory cell is in the "1" state or the "3" state, and as a result, for example, Low data is output to the outside. On the other hand, if the memory cell transistor keeps the non-conductive state, it is known whether the memory cell is in the “2” state or the “4” state. As a result, for example, High data is output to the outside.

<Read of lower page> When reading the second page (lower page), the memory cell is in the "1" state or the "2" state, or in the "3" state or the "4" state. It is determined whether there is. In this case, a voltage (V1 in FIG. 5) between the “3” state and the “2” state is applied to the control gate of the memory cell. When the memory cell transistor is turned on, it is known that the memory cell is in the "1" state or the "3" state. Next, by applying a voltage (V2 in FIG. 5) between the “1” state and the “3” state to the control gate of the memory cell, it is possible to determine whether the memory cell is in the “1” state. .

Next, a voltage (V3 in FIG. 5) between the "2" state and the "4" state is first applied to the control gate of the memory cell to determine whether the memory cell is in the "4" state. I understand. Thereby, it is determined whether the memory cell is in the “1” state or the “2” state, or is in the “3” state or the “4” state. In the “1” state or the “2” state, for example, Low data is output to the outside. On the other hand, when the memory cell transistor is in the “3” state or the “4” state, for example, High data is output to the outside.

In the above embodiment, as shown in FIG. 3, the threshold level in the “3” state written in the second write operation is changed to the threshold level in the “2” state written in the first write operation. It is set smaller. This is 3
For the second write operation in which the same write operation as the value cell is performed, it is better to reduce the threshold change amount in comparison with the first write operation in which the same write operation as the binary cell is performed. This is because it is advantageous in terms of speeding up. However, the method of setting the threshold level of the write data is not limited to this, and has a great deal of arbitrariness. For example, it may be set as shown in FIG.

In the embodiment shown in FIG. 6, "1" state, "2"
The threshold levels of the state, “3” state and “4” state have the same magnitude relationship as in the conventional example shown in FIG.
The threshold level of the “3” state written in the second write operation is “2” written in the first write operation.
It is set higher than the state threshold level. However, the upper page is “1” or “2” as in FIG. 3, and the write data input from the outside is
Is written to the memory cell in the same manner as described above. That is, when the address A0 is Low, the memory cell MC1 keeps the "1" state, and when the address A0 is High, the memory cell MC1
1 is written to the "2" state. On the other hand, before the lower page is written, the memory cell MC1 is in the "1" state or the "2" state.
C1 maintains the "1" state or the "2" state. On the other hand, A128
Is High, the memory cells MC1 in the “1” state or the “2” state are written to the “3” state and the “4” state, respectively.

As described above, high-speed writing can be performed by dividing the multi-value data stored in one memory cell into a plurality of pages. For example, when quaternary data is stored in one memory cell, the first page and the second page may be used. When storing eight-value data in one memory cell, the first page, the second page, and the third page may be used. Further, for example, when storing 16-value data in one memory cell, the first page, the second page, the third page, the fourth page,
Page. That is, one memory cell has 2
^When storing data of ⁿ (n is a natural number) value,
The second,..., N-th pages may be used.

As described above, according to the present embodiment, in a multilevel semiconductor memory device that stores three or more values in one memory cell, data in one memory cell is divided into a plurality of pages and written. The writing speed is increased. In the above embodiment, the EEPROM has been described, but the present invention is also effective for an SRAM, a DRAM, a mask ROM, etc. which perform multi-value storage.

Hereinafter, the present embodiment will be described in more detail with reference to a block diagram. FIG. 7 is a block diagram of a multilevel semiconductor memory device. A control gate / select gate drive circuit 2 for selecting a memory cell and applying a write voltage and a read voltage to a control gate is provided for a memory cell array 1 in which memory cells are arranged in a matrix. The control gate / selection gate drive circuit 2 is connected to the address buffer 5 and receives an address signal. The data circuit 3 is a circuit for holding write data and reading data from a memory cell. Data circuit 3 is connected to data input / output buffer 4 and receives an address signal from address buffer 5. The data input / output buffer 4 controls data input / output with the outside of the chip.

FIGS. 8 and 9 show the writing and reading of the memory cell. A memory cell unit including at least one memory cell is connected to a data circuit via a bit line. In the figure, memory cells sharing a word line WL1 as a gate electrode are MC1, MC2, MC3,.
C127 and MC128.

<Writing> FIG. 8 is a diagram for explaining writing.
It is. First, the writing of the first page corresponding to address A ₀ to A ₁₂₇ (upper page). A ₀
Data is latched in the first data circuit, data A ₁ is latched in the second data circuit. Similarly, A ₁₂₆
Data of the data circuits 127, data A ₁₂₇ is latched in the data circuit of the 128. Share the word line WL1 according to the data latched in the data circuit,
MC1, MC2, MC3, ..., MC127, MC128
Is written to the upper page.

Next, writing of the second page (lower page) corresponding to addresses B ₀ to B ₁₂₇ will be described.
Data B ₀ is latched in the first data circuit, data B ₁ is latched in the second data circuit. Similarly, B
_{The 126} data is latched in the 127th data circuit, and the _B127 data is latched in the 128th data circuit. Address B
₀ write data of the lower page of B ₁₂₇ while the first data circuit is latched in the data circuit of the 128, A ₁₂₇ from the address A ₀ written in the memory cell
From the first data circuit to the 128th
And holds it in the data circuit. From the data, and B ₀ of the upper page of the A ₁₂₇ from A ₀ obtained by latching in accordance with the write data of the lower page of B ₁₂₇ to the data circuit, sharing the word lines WL1, MC1, MC2, MC3, ...,
Lower page writing is performed on MC127 and MC128.

<Reading> FIG. 9 is a diagram for explaining reading.
It is. First, the reading of the first page corresponding to address A ₀ to A ₁₂₇ (upper page). Data A ₀ from the memory cell MC1 is read out to the first data circuit from the memory cell MC2 of A ₁ data is read out to the second data circuit. Similarly, the memory cell MC1
Data A ₁₂₆ from the 27 to the data circuits 127, the data from the memory cell MC128 A ₁₂₇ is latched in the data circuit of the 128. As described above, the word line WL
1, MC1, MC2, MC3,..., MC12
7, the data of the upper page of MC128 is read out to the data circuit.

Next, reading of the second page (lower page) corresponding to addresses B ₀ to B ₁₂₇ will be described. Data B ₀ from the memory cell MC1 is read out to the first data circuit from the memory cell MC2 of B ₁ data second
Is read out to the data circuit. Similarly, the memory cell MC
The data from 127 to B ₁₂₆ is transferred to the 127th data circuit,
Data from the memory cell MC128 B ₁₂₇ is read out to the data circuit of the 128. As described above, the word line W
MC1, MC2, MC3,..., MC1 sharing L1
27, data of the lower page of the MC 128 are read out to the data circuit.

The memory cell unit includes one or a plurality of memory cells and zero, one, or a plurality of selection MOS transistors. Some examples of the memory cell unit are shown in FIG. FIG. 10A shows a so-called N
FIG. 10B shows an AND type EEPROM or a NAND type mask ROM in which the threshold values of the selection MOS transistors shown in FIG. 10A are different (E-type, I-type).
FIG. 10C shows an example of a NAND nonvolatile memory provided with three selection MOS transistors, and FIG. 10D shows an example of a NAND nonvolatile memory provided with four selection MOS transistors. E-type selection MOS in the figure
The threshold value of the transistor is positive, and the threshold value of the D-type selection MOS transistor is negative. ). The configuration of the NAND cell is the same as in FIGS. 74 and 75, and the configuration of the memory cell array is the same as in FIG.

FIG. 11A shows a NOR type EEPROM.
It is an OM or NOR type mask ROM. FIG. 11B
(C) is an example in which one or two selection MOS transistors are provided in a NOR type nonvolatile memory. FIG.
(A) shows a configuration in which the source and the drain are shared by a plurality of memory cells, and the memory cells are connected in parallel. FIG.
2 (b) shows a plurality of memory cells connected in parallel,
A device in which one selection MOS transistor is connected (known example O
noda, H., et al., IEDM Tech. Dig, 1992, p.599).
FIG. 12 (c) shows a configuration in which a plurality of memory cells are connected in parallel and two selection MOS transistors are connected (known examples: Kume, H., et al, IEDM Tech. Dig, 1992, p991, Hisamu
ne, Y., et al., IEDM Tech. Dig, 1992, p19). FIG.
Reference numeral 3 denotes another example in which a plurality of memory cells are connected in parallel (known examples: Bergemont, A., et al, .IEDMTech.Dig, 1993, p15).
).

[Second Embodiment] The present embodiment will be described with reference to the drawings, taking a 4-level NAND flash memory as an example. FIG. 7 shows a configuration of a multi-value storage type EEPROM. A control gate / select gate drive circuit 2 for selecting a memory cell and applying a write voltage and a read voltage to a control gate is provided for a memory cell array 1 in which memory cells are arranged in a matrix.
The control gate / selection gate drive circuit 2 is connected to the address buffer 5 and receives an address signal. The data circuit 3
This is a circuit for holding write data or reading data from a memory cell. Data circuit 3 is connected to data input / output buffer 4 and receives an address signal from address buffer 5. The data input / output buffer 4
Data input / output control with the outside of the EEPROM is performed.

FIG. 14 shows the memory cell array 1 and the data circuit 3 shown in FIG. Memory cells M1 to M
4 are connected in series to form a NAND cell. Both ends are connected to a bit line BL and a source line Vs via select transistors S1 and S2, respectively. Also,
A block is formed by a memory cell group connected to the four control gates CG1 to CG4. “Page” and “block” are selected by the control gate / selection gate drive circuit 2.
Each of the bit lines BL0A to BLmA has a data circuit 3-0 to 3-m
Are connected to temporarily store write data to a corresponding memory cell. In this embodiment, since the open bit lines are arranged, the data circuits 3-0 to 3-m have bit lines B
L0B to BLmB are also connected.

FIG. 15 shows the threshold voltage of the memory cell M and the four write states (four-level data "1", "2") when four values are stored by providing four write states in the memory cell M. , “3”, “4”). The state of data "1" is the same as the state after erasure,
For example, it has a negative threshold. The “2” state is, for example, 0.
It has a threshold between 5V and 0.8V. The "3" state has a threshold value between 1.5V and 1.8V, for example. The "4" state has a threshold value between, for example, 2.5V and 2.8V.

The read voltage VCG3R is applied to the control gate CG of the memory cell M, and the memory cell is turned on or off.
The data of the memory cell can be detected as “1” or “2” or “3” or “4” by FF ”. Subsequently, by applying the read voltages VCG4R and VCG2R, the data of the memory cell is completely detected. Read voltage VC
G2R, VCG3R, VCG4R are, for example, 0V, 1V, 2
V. The voltages VCG2V, VCG3V, and VCG4V are called verify voltages, and when data is written, these verify voltages are applied to the control gate to detect the state of the memory cell M and check whether or not the write has been performed sufficiently.
For example, they are 0.5 V, 1.5 V, and 2.5 V, respectively.

FIG. 16 shows a data circuit. The data circuit includes two latch circuits (a first latch circuit and a second latch circuit). At the time of writing, 2-bit write data is stored in these two latch circuits. At the time of reading, the read quaternary data is stored in these two latch circuits, and then output to the outside of the chip via IO1. In this embodiment, one page is composed of 256 memory cells. That is, the number of memory cells simultaneously selected by the same control gate and select gate is 256. Here, a case where data of two pages of 512 bits are written and read will be described as an example. 5
The 12-bit data includes upper page data and lower page data. The upper page data corresponds to the column addresses A ₀ , A ₁ , A ₂ ,..., A ₂₅₄ , A ₂₅₅ , and the lower page data corresponds to the column addresses B ₀ , B ₁ , B ₂ ,.
.., B ₂₅₄ and B ₂₅₅ .

<Upper page (A ₀ , A ₁ , A ₂ ,..., A
₂₅₄ , A ₂₅₅ )> First, the write data of the head address A ₀ is input to the first latch circuits RT1-0,
And it is held. Subsequently, addresses A ₁ , A ₂ ,.
The write data of A ₂₅₄ and A ₂₅₅ is stored in the first latch circuit R
.., RT1-254, RT1-255 are input and held. After that, writing is performed on the memory cell according to the 1-bit write data held in the first latch circuit in the data circuit, and the “1” state or “2” is written.
State. If the data is less than 256 bits, some of the first latch circuits in the data circuit do not receive write data. In this case, the write state of the memory cell is "1" having a low threshold level.
What is necessary is just to set the write data in the first latch circuit so as to be in the state.

<Lower page (B ₀ , B ₁ , B ₂ ,..., B
_254, B ₂₅₅₎ writes> First, the write data start address B ₀ is input to the first latch circuit RT1-0,
And it is held. Subsequently, addresses B ₁ , B ₂ ,.
₂₅₄ and B ₂₅₅ are written to the first latch circuit RT.
1-1, RT1-2,..., RT1-254, RT1-255 are input and held. Addresses A ₀ , A ₁ , A ₂ ,..., A already written in the memory cells while the externally input write data is being loaded into the first latch circuit.
₂₅₄ reads write data A _255, a second latch circuit RT2-0, RT2-1, ..., RT2-254, RT2-25
Enter 5 Thereafter, writing is performed on the memory cells in accordance with the 2-bit write data held in the two latch circuits in the data circuit.

That is, "1" or "2" is kept, or "1" to "3" or "2" to "4" is written. If the data is less than 512 bits, some of the latch circuits in the data circuit do not receive the data. In this case, if the data of the latch circuit to which no data is input is set so that the write state of the memory cell becomes the “1” state, “2” state, or “3” state where the threshold level is as low as possible. Good.

<Read> The read procedure is shown in FIG. First, a voltage V _p1 between the “2” state and the “3” state is applied to the word line of the memory cell to be read. When the memory cell is turned on, the memory cell is in the "1" or "2" state, and when the memory cell is turned off, the memory cell is in the "3" or "4" state. Thus, the lower page read data corresponding to the column addresses B ₀ , B ₁ , B ₂ ,..., B ₂₅₄ , B ₂₅₅ is held in the second latch circuit. Lower page (column addresses B ₀ , B ₁ ,
B ₂ ,..., B ₂₅₄ , B ₂₅₅ ), the data is output to the outside of the chip via the IO 1 here. When reading the upper page, the reading is further continued.
When V _p2 is applied to the selected word line, the memory cell becomes “4”
State, or "1" or "2" or "3" state. The read data is held in the first latch circuit.

Finally, when V _p3 is applied to the selected word line, it is determined whether the memory cell is in the “1” state, or in the “2”, “3” or “4” state. This allows
Column addresses A ₀ , A ₁ , A stored in memory cells
Read data corresponding to ₂ ,..., A ₂₅₄ , A ₂₅₅ is held in the first latch circuit. Thereafter, the column addresses A ₀ , A ₁ , A ₂ ,..., A held in the first latch circuit
Data corresponding to ₂₅₄ and _A255 is output to the outside of the chip.

The operation will be described in more detail below. The configuration of the multi-value storage type EEPROM is the same as that of FIG. N
The configuration of the AND cell is the same as that shown in FIGS. 74 and 75, and the configuration of the memory cell array is the same as that shown in FIG. 76. The relationship between the write state of the memory cell and the threshold value is the same as in FIG. FIG. 18 shows a specific example of the data circuit 3.

The present embodiment is configured using four-value storage as an example. n channel MOS transistors Qn21, Qn22, Q
n23 and p-channel MOS transistors Qp9, Qp10, Q
The write / read data is latched in a flip-flop FF1 composed of p11 and an FF2 composed of n-channel MOS transistors Qn29, Qn30, Qn31 and p-channel MOS transistors Qp16, Qp17, Qp18. These also operate as sense amplifiers.

The flip flops FF1 and FF2 are
"Whether to write" 1 "or" 2 "
“3” write or “4” write ”is latched as write data information, and whether the memory cell holds“ 1 ”information or“ 2 ”information Whether the information “3” is held or the information “4” is held ”is sensed as read data information and latched.

Data input / output lines IOA and IOB and flip-flop FF1 are connected to n-channel MOS transistor Q
They are connected via n28 and Qn27. Data input / output line IO
A, IOB and flip-flop FF2 are connected via n-channel MOS transistors Qn35 and Qn36. The data input / output lines IOA and IOB are also connected to the data input / output buffer 4 in FIG. The read data held in the flip-flop FF1 is output to IOA and IOB by activating CENB1.
The read data held in the flip-flop FF2 is supplied to IOA and I
Output to OB.

N channel MOS transistors Qn26, Qn
n34 equalizes the flip-flops FF1 and FF2 when the signals ECH1 and ECH2 become "H". The n-channel MOS transistors Qn24 and Qn32 are
The connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd1 is controlled. The n-channel MOS transistors Qn25 and Qn33 are connected to flip-flops FF1 and FF2.
And the connection of the MOS capacitor Qd2.

P channel MOS transistors Qp12C, Q
The circuit constituted by p13C responds to the data of the flip-flop FF1 by the activation signal VRFYBAC,
The gate voltage of the MOS capacitor Qd1 is changed. A circuit composed of p-channel MOS transistors Qp14C and Qp15C is flip-flopped by an activation signal VRFYBBC.
According to the data of the flop FF1, the MOS capacitor Q
Change the gate voltage of d2. A circuit composed of n-channel MOS transistors Qn1C and Qn2C activates an activation signal V
RFYBA1C changes the gate voltage of MOS capacitor Qd1 according to the data of flip-flop FF2. n-channel MOS transistors Qn3C, Qn4
The circuit constituted by C is activated by the activation signal VRFYBB1C according to the data of the flip-flop FF2.
The gate voltage of the MOS capacitor Qd2 is changed.

MOS capacitors Qd1 and Qd2 are composed of depletion type n-channel MOS transistors.
This is made sufficiently smaller than the bit line capacity. n-channel MOS
The transistor Qn37 charges the MOS capacitor Qd1 to the voltage VA by the signal PREA. n-channel MOS
Transistor Qn38 charges MOS capacitor Qd2 to voltage VB in response to signal PREB. n-channel MOS
The transistors Qn39 and Qn40 output signals BLCA and BLC
B controls the connection between the data circuit 3 and the bit lines BLa and BLb, respectively. The circuit composed of the n-channel MOS transistors Qn37 and Qn38 also functions as a bit line voltage control circuit.

Next, the EEPROM constructed as described above will be described.
Will be described with reference to a timing chart. Hereinafter, a case where the control gate CG2A is selected will be described. <Writing of upper page> (1) Program of upper page The input data is input to the data circuit 3 via the data input / output buffer 4 before the write operation. The size of one page is 256 bits, and the data circuit is 256 bits.
If there are the write data, the input 256-bit write data of the upper page is input to the flip-flop FF1 via IOA and IOB when the column activation signal CENB1 is "H". Write data and node N of FF1
FIG. 19 shows the relationship between 3C and N4C. Input data is Hi
gh, the state is kept “1” and the input data is Low.
In the case of, it is written to the "2" state.

The write operation is shown in FIG. At time t1s, VRFYBAC becomes 0 V, and the bit line write control voltage Vcc is output to the bit line from the data circuit holding data "1". Then, at time t2s
When RV1A becomes Vcc, 0V is output to the bit line from the data circuit holding data "2".
As a result, the bit line for writing “1” is Vcc, “2”
The bit line to be written becomes 0V.

At time t1s, the control gate / selection gate drive circuit 2 selects the selection gate SG1 of the selected block.
A, the control gates CG1A to CG4A become Vcc. The selection gate SG2A is at 0V. Next, at time t3s, the selected control gate CG2A is driven to the high voltage Vpp (for example, 20
V), non-selection control gates CG1A, CG3A, CG4A
Becomes VM (for example, 10 V). In the memory cell corresponding to the data circuit holding the data “2”, electrons are injected into the floating gate due to the difference between the channel potential of 0 V and the potential of Vpp of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding the data “1”, the channel of the memory cell becomes floating because the selection gate SG1A is turned “OFF”. As a result, the channel of the memory cell becomes about 8 V due to capacitive coupling with the control gate. In the memory cell into which data "1" is to be written, the channel is 8 V and the control gate is 20 V, so that electrons are not injected into the memory cell and the erase state ("1") is maintained. During the write operation, the signals SAN1, S
AN2, PREB, BLCB are "H", and signals SAP1,
SAP2, VRFYBA1C, RV1B, RV2B, E
CH1 and ECH2 are "L", and voltage VB is 0V.

(2) Verify Read of Upper Page After the write operation, it is detected whether or not the write has been sufficiently performed (write verify). If the desired threshold value has been reached, the data of the data circuit is changed to "1". If the threshold value has not been reached, the data of the data circuit is held and the write operation is performed again. The write operation and the write verify are repeated until all the memory cells to which "2" is written reach a desired threshold. The write verify operation will be described with reference to FIGS. First, at time t1yc, the voltage V
A and VB become 1.8V and 1.5V, respectively, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. The signals BLCA and BLCB become "L", the bit line BLa and the MOS capacitor Qd1, and the bit lines BLb and M
The OS capacitor Qd2 is cut off and the bit lines BLa, B
Lb is floating. Signals PREA, PREB
Becomes "L", and the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, enter a floating state.

Subsequently, at time t2yc, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is 0.5 V, the non-selected control gates CG1A, CG3A, CG4A and the selection gate SG1A,
SG2A is set to Vcc. If the threshold value of the selected memory cell is 0.5V or less, the bit line voltage will be lower than 1.5V. The threshold value of the selected memory cell is 0.5 V
In this case, the bit line voltage remains at 1.8 V. At time t3yc, the signals BLCA and BLCB are set to "H", and the bit line potential is transferred to N1 and N2. After that, the signals BLCA and BLCB become “L” and the bit line BLa
And the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected.

Thereafter, when VRFYBAC becomes "L" at time t4yc, in the data circuit holding "1" write data, the p-channel MOS transistor Qp1
2C is "ON", and the node N1 becomes Vcc. As a result, the node N1 becomes Vcc when "1" is written. In the case of writing "2", the p-channel MOS transistor Qp12C is turned "OFF". That is, when "2" write is sufficiently performed, N1 becomes Vcc,
If "2" write is insufficient, N1 becomes 0V. Thereafter, the signals SAN1 and SAP1 become "L" and "H" respectively, the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized.

Thereafter, the signals RV1A and RV1B are set to "H".
Becomes Again, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the node N1 at time t5yc.
Are sensed and latched. As a result, only the data circuit holding the “2” write data detects whether the data of the corresponding memory cell is sufficiently in the “2” write state. If the data of the memory cell is "2", the write data is changed to "1" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data of the memory cell is not “2”, the write data is held at “2” by sensing and latching the voltage of the node N1 with the flip-flop FF1.
The write data of the data circuit holding the “1” write data is not changed.

If all the selected memory cells have reached the desired threshold, the node N4C of the data circuit goes to "L". By detecting this, it is known whether or not all the selected memory cells have reached the desired threshold. For example, the write end detection transistor Qn5C may be used to detect the write end as shown in FIG.
After the verify read, VRTC is first precharged to, for example, Vcc. If there is at least one insufficiently written memory cell, the n-channel MOS transistor Qn5C turns "ON" because the node N4C of the data circuit is "H",
VRTC falls from the precharge potential. When all the memory cells are sufficiently written, the data circuits 3-0, 3-
All the nodes N4C of 1,..., 3-m-1, 3-m become “L”. As a result, n-channel MOS in all data circuits
Since the transistor Qn5C is turned "OFF", VRTC maintains the precharge potential, and the end of writing is detected.

<Writing of lower page> (1) Reading of upper data, data inversion, and data loading Prior to writing of the lower page, data of the upper page is written in the memory cell, as shown in FIG. ,
It is in the “1” state or the “2” state. The lower page data is externally input to the flip-flop FF1 via IOA and IOB, and at the same time, the upper page data stored in the memory cell is read and held in the flip-flop FF2. Reading of the data of the upper page written in the memory cell will be described with reference to FIGS.

First, at time t1yd, voltages VA and VB become 1.8 V and 1.5 V, respectively, and bit lines BLa and B
Lb becomes 1.8V and 1.5V, respectively. Signal BLC
A and BLCB become “L”, and the bit lines BLa and MO
The S capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are cut off, and the bit lines BLa and BLb float. The signals PREA and PREB become "L", and the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, enter a floating state.

Subsequently, at time t2yd, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is set to 0V, and the unselected control gate CG1 is set.
A, CG3A, CG4A and select gates SG1A, SG2
A is set to Vcc. If the threshold value of the selected memory cell is 0V or less, the bit line voltage will be lower than 1.5V.
If the threshold value of the selected memory cell is 0 V or more, the bit line voltage remains at 1.8 V. At time t3yd, the signals BLCA and BLCB are set to "H", and the bit line potential is transferred to N1 and N2. After that, the signals BLCA, BL
CB becomes "L", and the bit line BLa is separated from the MOS capacitor Qd1, and the bit line BLb is separated from the MOS capacitor Qd2. Thereafter, the signals SAN2 and SAP2 become "L" and "H", respectively, so that the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized. Thereafter, the signals RV2A and RV2B become "H". Again, when the signals SAN2 and SAP2 become "H" and "L", respectively, the node N1 at time t4yd
Are sensed and latched. The flip at this time
The nodes N5C and N6C of the flop FF2 are shown in FIG.
become.

Thereafter, the data read out is inverted. For example, when “1” is read, as shown in FIG.
5C is “L”, but “H” due to the data inversion operation.
To At time t5yd, the signals PREA and PREB change to "H", and the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, are precharged to 1.8 V and 1.5 V, and thereafter enter a floating state.
Subsequently, when VRFYBA1C becomes “H” at time t6yd, in the data circuit holding the “2” write data, the n-channel MOS transistor Qn2C is turned “ON”.
And the node N1 becomes 0V. In the case of "1" writing, the n-channel MOS transistor Qn2C
F ", and the node N1 keeps 1.8V.

Thereafter, the signals SAN2 and SAP2 become "L" and "H" respectively, the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and equalized. Thereafter, the signals RV2A and RV2B become "H". Again, the signals SAN2 and SAP2 become "H" and "L", respectively, so that the node N1 at time t7yd.
Are sensed and latched. As a result of the above data inversion operation, the node of the flip-flop FF2 is
(C).

FIG. 24 shows the write data of the lower page inputted to the flip-flop FF1 from the outside. If the input data of the lower page is "H", writing is not performed, and the memory cell maintains the "1" or "2" state. On the other hand, if the input data of the lower page is "L", writing is performed, and the memory cell in the "1" state is written in the "3" state, and the memory cell in the "2" state is written in the "4" state. In summary, the flip-flop nodes N3C, N4C, N5C, N6C at the time of writing the lower page
Are as shown in FIG.

(2) Lower page program write operation is shown in FIG. At time t1p, the voltage VA becomes the bit line write control voltage 1V, and the bit line BLa becomes 1V. When the voltage drop of the threshold value of the n-channel MOS transistor Qn39 becomes a problem,
The signal BLCA may be boosted. Subsequently, the signal PREA
Becomes "L", and the bit line is floated.
Next, the signal RV2A is set to 1.5 V at the time t2p. As a result, the bit line control voltage 0V is applied to the bit line from the data circuit holding the data “2” or “4”.

Assuming that the threshold value of the n-channel MOS transistor Qn32 is 1 V, the n-channel MOS transistor Qn32 is "OFF" when "1" or "3" is written.
It becomes "ON" when "2" or "4" is written. Thereafter, at time t3p, VRFYBAC becomes 0 V, and the bit line write control voltage Vcc is output to the bit line from the data circuit holding data "1" or data "2". As a result, the bit line for writing “1” or “2” is Vcc, and the bit line for writing “3” is 1
The bit line for writing V, "4" becomes 0V.

At time t1p, the control gate / selection gate drive circuit 2 selects the selection gate SG1 of the selected block.
A, the control gates CG1A to CG4A become Vcc. The selection gate SG2A is at 0V. At time t4p, the selected control gate CG2A becomes high voltage Vpp (for example, 20V), and the non-selected control gates CG1A, CG3A, CG4A become VM (for example, 10V). In the memory cell corresponding to the data circuit holding data "4", electrons are injected into the floating gate due to the difference between the channel potential of 0 V and the potential of Vpp of the control gate, and the threshold value increases. In a memory cell corresponding to a data circuit holding data “3”, 1
Due to the difference between the channel potential of V and the potential of Vpp of the control gate, electrons are injected into the floating gate to raise the threshold.

The channel potential in the case of “3” write is set to 1
The reason for setting V is to make the injection amount of electrons smaller than in the case of writing “4” data. Data "1"
Alternatively, in a memory cell corresponding to a data circuit in which "2" is held, electrons are not effectively injected into the floating gate because the potential difference between the channel potential and Vpp of the control gate is small. Therefore, the threshold value of the memory cell does not change. During a write operation, signals SAN1, SAN2, PREB, B
LCB is “H”, signals SAP1, SAP2, VRFYB
A1C, RV1A, RV1B, RV2B, ECH1, E
CH2 is “L” and voltage VB is 0V. The writing method is optional. For example, as shown in FIG. 27, the node to which the n-channel transistors Qn2C and Qn4C are connected may be set to a fixed potential Vref instead of the ground potential as shown in FIG. In FIG. 28, the bit line is grounded to 0 V, then floated, and then VRFYBA1C is set to Vcc, so that the bit line for writing "1" or "3" is 1 V. After that, VR
By setting FYBAC to 0 V, "1" or "2"
The write bit line is set to Vcc. As a result, the bit line for “4” write becomes 0 V, the bit line for “3” write becomes 1 V, and the bit line for “1” or “2” write becomes Vcc.

(3) Verify read of lower page After the write operation, it is detected whether or not the write has been sufficiently performed (write verify). If the desired threshold value has been reached, the node N3 of the flip-flop FF1
Change C to "H". If the threshold has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and the write verify operation are repeated until all the memory cells to which "3" is to be written and the memory cells to which "4" are to be written have reached desired threshold values.

The write verify operation will be described with reference to FIGS. First, it is detected whether the memory cell to which "3" is to be written has reached a predetermined threshold value. First, at time t1yx, the voltages VA and VB are set to 1.
8V and 1.5V, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. Signals BLCA, BL
When CB becomes "L", the bit line BLa is disconnected from the MOS capacitor Qd1, the bit line BLb is disconnected from the MOS capacitor Qd2, and the bit lines BLa and BLb are floating. When the signals PREA and PREB become “L”, the MO
Node N which is the gate electrode of S capacitor Qd1, Qd2
1 and N2 are in a floating state. Subsequently, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is 1.5V, the non-selection control gates CG1A, CG3A, CG4A and the selection gate S
G1A and SG2A are set to Vcc. If the threshold value of the selected memory cell is 1.5 V or less, the bit line voltage becomes 1.V.
It becomes lower than 5V. If the threshold value of the selected memory cell is 1.5 V or more, the bit line voltage remains at 1.8 V.

At time t2yx, signals BLCA and BLCB are set to "H", and the potential of the bit line is transferred to N1 and N2. After that, the signals BLCA and BLCB become "L", and the bit line BLa is separated from the MOS capacitor Qd1, and the bit line BLb is separated from the MOS capacitor Qd2. Thereafter, at time t3yx, RV2A becomes 1.5V, and in the case of "2" writing and "4" writing, the node N1 is discharged to 0V. When the signal VRFYBAC becomes "L" at time t4yx, in the data circuit holding the "1" or "2" write data, the p-channel MOS transistor Qp12C is "ON" and the node N1 becomes Vcc. As a result, the node N1 writes “1” or “2”.
Vcc for writing, 0 for "4" writing
V.

The signals SAN1 and SAP1 become "L" and "H" respectively, the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized. Thereafter, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t5yx. As a result, only the data circuit holding the “3” write data detects whether the data of the corresponding memory cell is sufficiently in the “3” write state. If the data of the memory cell is "3", the write data is changed to "1" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data of the memory cell is not "3", the flip-flop FF1 senses and latches the voltage of the node N2, and the write data is held at "3". Thereafter, additional writing is performed. The write data of the data circuit holding the “1”, “2” or “4” write data is not changed.

Next, the selected control gate is set to 2.5V. If the threshold of the selected memory cell is less than 2.5V, the bit line voltage will be less than 1.5V. If the threshold value of the selected memory cell is 2.5 V or more, the bit line voltage remains at 1.8 V. PRE at time t6yx
A and PREB become Vcc, and nodes N1 and N2 become 1.8.
After V and 1.5V, it becomes floating. Thereafter, at time t7yx, the signals BLCA and BLCB are set to "H", and the potential of the bit line is transferred to N1 and N2. Thereafter, the signals BLCA and BLCB become "L", and the bit line BLa and the MOS capacitor Qd1, and the bit lines BLb and M
OS capacitor Qd2 is disconnected. When the signal VRFYBAC becomes "L" at time t8yx, the data circuit holding "1" or "2" write data and "3"
In a data circuit in which "1" write data is held due to sufficient writing, a p-channel MOS
The transistor Qp12C is "ON" and the node N1 is at V
cc.

Signals SAN1 and SAP1 become "L" and "H", respectively, so that flip-flop FF1 is inactivated, and signal ECH1 becomes "H" and equalized. Thereafter, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t9yx. As a result, only the data circuit holding the “4” write data detects whether the data of the corresponding memory cell is sufficiently in the “4” write state. If the data of the memory cell is "4", the write data is changed to "2" by sensing and latching the voltage of the node N1 by the flip-flop FF1, and the write operation is not performed thereafter. If the data in the memory cell is not "4", the voltage of the node N1 is sensed and latched by the flip-flop FF1, so that the write data is "4".
After that, additional writing is performed. The write data of the data circuit holding the “1”, “2” or “3” write data is not changed.

If all the selected memory cells have reached the desired threshold, the node N4C of the data circuit goes to "L". By detecting this, it is known whether or not all the selected memory cells have reached the desired threshold. For example, the write end detection transistor Qn5C may be used to detect the write end as shown in FIG.
After the verify read, VRTC is first precharged to, for example, Vcc. If there is at least one insufficiently written memory cell, the n-channel MOS transistor Qn5C turns "ON" because the node N4C of the data circuit is "H",
VRTC falls from the precharge potential. When all the memory cells are sufficiently written, the data circuits 3-0, 3-
All the nodes N4C of 1,..., 3-m-1, 3-m become “L”. As a result, n-channel MOS in all data circuits
Since the transistor Qn5C is turned "OFF", VRTC maintains the precharge potential, and the end of writing is detected.

<Read Operation of Upper Page> In read of the upper page, "1" or "3" or "2" or "4" is read. According to FIGS. 30 and 31,
The read operation will be described. First, at time t1RD, the voltage V
A and VB become 1.8V and 1.5V, respectively, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. The signals BLCA and BLCB become "L", the bit line BLa and the MOS capacitor Qd1, and the bit lines BLb and M
The OS capacitor Qd2 is cut off and the bit lines BLa, B
Lb is floating. Signals PREA, PREB
Becomes "L", and the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, enter a floating state. Subsequently, the selected control gate CG2 of the block selected by the control gate / selection gate drive circuit 2
A is 1V, non-selection control gates CG1A, CG3A, CG
4A and select gates SG1A and SG2A are set to Vcc.
If the threshold value of the selected memory cell is 1 V or less, the bit line voltage becomes lower than 1.5 V. If the threshold value of the selected memory cell is 1 V or more, the bit line voltage is 1.8 V
Will remain.

Thereafter, at time t2RD, signals BLCA, BL
CB becomes "H", and the data on the bit line is transferred to the MOS capacitors Qd1 and Qd2. Then, again, the signal BLC
A and BLCB become “L”, and the bit lines BLa and MO
The S capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected. The signals SAN2 and SAP2 become "L" and "H", respectively, so that the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized. Thereafter, the signals RV2A and RV2B become "H". At time t3RD, the signals SAN2 and SAP2 become "H" and "L", respectively, whereby the voltage of the node N1 is sensed and latched. As a result, “the data of the memory cell is“ 1 ”or“ 2 ”, or“ 3 ”or“ 4 ”
Is sensed by the flip-flop FF2,
That information is latched. At this time, the nodes N5C and N6C of the flip-flop FF2 are as shown in FIG.

Next, the selected control gate is set to 2V. If the threshold value of the selected memory cell is 2 V or less,
The bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 2 V or more, the bit line voltage becomes 1.V.
It remains at 8V. At time t4RD, signals PREA and PRE are output.
B becomes "H" and the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, are respectively 1.8V,
1.5V. The signals PREA and PREB become "L", and the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, enter a floating state. Thereafter, at time t5RD, the signals BLCA and BLCB are set to "H". Again, the signals BLCA and BLCB become "L", and the bit line BLa is separated from the MOS capacitor Qd1, and the bit line BLb is separated from the MOS capacitor Qd2. Signal S
AN1 and SAP1 become "L" and "H", respectively, so that the flip-flop FF1 is inactivated and the signal ECH1
Becomes “H” and is equalized. After this, the signal RV
1A and RV1B become "H". At time t6RD, the signals SAN1 and SAP1 become "H" and "L" respectively, whereby the voltage of the node N1 is sensed and latched.
Thus, “whether the data of the memory cell is“ 1 ”,“ 2 ”,“ 3 ”, or“ 4 ”” is determined by the flip-flop FF.
1 and that information is latched. At this time, the nodes N3C of the flip-flops FF1 and FF2,
The potential of N5C is as shown in FIG.

Subsequently, reading is performed as shown in FIG. First, at time t7RD, the voltages VA and VB become 1.8 V and 1.5 V, respectively, and the bit lines BLa and BLb
Are 1.8V and 1.5V, respectively. The signal BLCA,
BLCB becomes "L", and the bit line BLa and the MOS capacitor Qd1 and the bit line BLb and the MOS capacitor Qd2
Are disconnected, and the bit lines BLa and BLb become floating. The signals PREA and PREB become “L”,
Nodes N1 and N2, which are gate electrodes of MOS capacitors Qd1 and Qd2, enter a floating state. Subsequently, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 has 0V, and the unselected control gates CG1A, CG3A, CG4A and the selection gate S
G1A and SG2A are set to Vcc. If the threshold value of the selected memory cell is 0 V or less, the bit line voltage is 1.5 V
Lower. The threshold value of the selected memory cell is 0 V
In this case, the bit line voltage remains at 1.8 V. Thereafter, at time t8RD, the signals BLCA and BLCB become "H", and the data on the bit line is transferred to the MOS capacitors Qd1 and Qd2. Thereafter, the signals BLCA and BLCB again become "L", and the bit line BLa and the MOS capacitor Q
d1, the bit line BLb and the MOS capacitor Qd2 are disconnected. Subsequently, at time t9RD, VRFYBA1C becomes "H".
become. At this time, the node N of the flip-flop FF2
As can be seen from FIG. 33, 5C is "H" when "3" or "4" is read. In this case, the n-channel MOS transistor Qn2C in FIG.
Alternatively, the node N1 for “4” read is grounded.

Subsequently, at time t10RD, VRFYBAC becomes "L". At this time, the node N3C of the flip-flop FF1 is at "H" and the node N4C is at "L" in the case of "3" reading as can be seen from FIG. in this case,
The p-channel MOS transistor Qp12C of FIG.
N ”and“ 4 ”read node N1 goes to Vcc, after which signals SAN1 and SAP1 become“ L ”,
The signal becomes "H", the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized.
Thereafter, the signals RV1A and RV1B become "H". At time t11RD, the signals SAN1 and SAP1 become "H" and "L", respectively, whereby the voltage of the node N1 is sensed and latched. Thus, the potentials of the nodes N3C and N4C are sensed by the flip-flop FF1,
That information is latched. At this time, the nodes N3C of the flip-flop FF1 and the flip-flop FF2,
N4C, N5C and N6C are as shown in FIG.

The data of the upper page has been read to the nodes N3C and N4C (see FIG. 34) of the flip-flop FF1. That is, in the “1” state and the “3” state, the node N3C becomes “L” and the N4C becomes “H”. In the “2” and “4” states, the node N3C becomes “H” and the N4C becomes “L”. Become. As described in <Writing of upper page>, the data of the upper page stores "1" or "3" or "2" or "4", and this write data is stored in the flip-flop FF1. Is read correctly. The data held in the flip-flop FF1 is output to the outside of the chip by activating CENB1.

<Read operation of lower page> In reading of lower page, "1" or "2" or "3" or "4" is read. The read operation will be described with reference to FIG. First, at time t1RD, the voltages VA, VB
Become 1.8V and 1.5V, respectively, and the bit line BL
a and BLb become 1.8V and 1.5V, respectively. The signals BLCA and BLCB become “L”, and the bit line BLa
, The MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are separated, and the bit lines BLa and BLb float. Signals PREA and PREB are "L"
As a result, the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, enter a floating state.

Subsequently, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 has 1V, and the non-selected control gates CG1A, CG3
A, CG4A and select gates SG1A, SG2A are set to Vcc. If the threshold value of the selected memory cell is 1 V or less, the bit line voltage becomes lower than 1.5 V. If the threshold value of the selected memory cell is 1 V or more, the bit line voltage remains at 1.8 V. Thereafter, at time t2RD, the signal BL
CA and BLCB become “H” and the data on the bit line becomes MO.
The data is transferred to the S capacitors Qd1 and Qd2. Then again
The signals BLCA and BLCB become “L” and the bit line B
La and MOS capacitor Qd1, bit line BLb and MOS
The capacitor Qd2 is disconnected. Signals SAN2 and SAP
2 become "L" and "H" respectively, the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized. Thereafter, the signals RV2A, RV2B
Becomes “H”. At time t3RD, the signals SAN2 and S
When AP2 becomes “H” and “L”, the voltage of the node N1 is sensed and latched. Thus, "whether the data in the memory cell is" 1 "or" 2 "or" 3 "or" 4 "" is sensed by the flip-flop FF2, and the information is latched. The flip at this time
The nodes N5C and N6C of the flop FF2 are as shown in FIG.

The data of the lower page has been read to the nodes N5C and N6C (see FIG. 32) of the flip-flop FF2. That is, in the “1” state and the “2” state, the node N5C becomes “L” and the N6C becomes “H”, and in the “3” state and the “4” state, the node N5C becomes “H” and the N6C becomes “L”. Become. As described in <Writing of lower page>, the data of the lower page stores "1" or "2", or "3" or "4", and this write data is stored in the flip-flop FF2. Is read correctly. The data held in the flip-flop FF2 is output to the outside of the chip by activating CENB2.

As can be seen from the above description, reading of the lower page is an operation up to time t3RD of reading of the upper page. Therefore, for example, when reading the upper page following the lower page, the lower page may be read first, and then the upper page data may be read while the lower page data is being output to the outside of the chip. . That is, the data of the lower page is latched by the flip-flop FF2 at the time t3RD and output to the outside of the chip, and at the same time, the operation after the time t3RD shown in FIGS. . Thereby, the reading of the upper page can be apparently performed at high speed.

[Third Embodiment] In the second embodiment, the upper page is read and the data inversion operation is performed before the lower page is written. The lower page can be written without performing the data inversion operation before writing the lower page. Hereinafter, a method of writing the lower page will be described. FIG. 18 shows the data circuit of this embodiment, similarly to the previous embodiment. The writing of the upper page is the same as in the second embodiment.

(1) Reading of upper page before writing of lower page Prior to writing of the lower page, data of the upper page is written in the memory cell, and as shown in FIG.
It is in the “1” state or the “2” state. The lower page data is externally input to the flip-flop FF1 via IOA and IOB, and at the same time, the upper page data stored in the memory cell is read and held in the flip-flop FF2. Read operation of upper page is second
This is almost the same as the embodiment of FIG. However, since the data inversion is not performed, the operation ends when the sensing is performed at time t4yd. As a result, the write data of the lower page is not as shown in FIG. 25 but as shown in FIG. Since the data inversion operation is not performed, compared with FIG.
The logic of 5C and N6C is reversed.

(2) Lower page program write operation is shown in FIG. At time t1pq, the voltage VA becomes the bit line write control voltage 1V, and the bit line BLa becomes 1V. When the voltage drop by the threshold value of n-channel MOS transistor Qn39 becomes a problem, signal BLCA may be boosted. Subsequently, the signal PR
EA becomes "L" and the bit line is floated. Next, at time t2pq, the signal VRFYBA1C is set to Vcc. Thereby, when data “2” or “4” is held, n-channel MOS transistor Q
Since n2C is turned "ON", the bit line control voltage 0V is applied to the bit line. VRFYBA1C may be set to Vcc or more as shown in FIG. Then, at time t3pq, VRFY
The BAC becomes 0V, and the bit line write control voltage Vcc is output to the bit line from the data circuit holding the data “1” or the data “2”. As a result, the bit line for writing “1” or “2” is Vcc, “3”
The bit line for writing becomes 1V, and the bit line for writing "4" becomes 0V.

At time t1pq, the control gate / selection gate drive circuit 2 selects the selection gate SG of the selected block.
1A, the control gates CG1A to CG4A become Vcc. The selection gate SG2A is at 0V. Next, the control gate CG2A selected at the time t4pq is set to the high voltage Vpp (for example, 20 V).
V), non-selection control gates CG1A, CG3A, CG4A
Becomes VM (for example, 10 V). In the memory cell corresponding to the data circuit holding data "4", electrons are injected into the floating gate due to the difference between the channel potential of 0 V and the potential of Vpp of the control gate, and the threshold value increases. In the memory cell corresponding to the data circuit holding data "3", electrons are injected into the floating gate due to the difference between the channel potential of 1 V and the potential of Vpp of the control gate, and the threshold value rises.

The channel potential in the case of writing “3” is set to 1
The reason for setting V is to make the injection amount of electrons smaller than in the case of writing “4” data. Data "1"
Alternatively, in a memory cell corresponding to a data circuit in which "2" is held, electrons are not effectively injected into the floating gate because the potential difference between the channel potential and Vpp of the control gate is small. Therefore, the threshold value of the memory cell does not change. During a write operation, signals SAN1, SAN2, PREB, B
LCB is “H” and signals SAP1, SAP2, RV1A,
RV1B, RV2B, ECH1, and ECH2 are at "L" level, and voltage VB is at 0V.

(3) Verify read of lower page After the write operation, it is detected whether or not the write has been sufficiently performed (write verify). If the desired threshold value has been reached, the node N3 of the flip-flop FF1
Change C to "H". If the threshold value has not been reached, the data of the data circuit is held and the write operation is performed again. The write operation and the write verify are repeated until all the memory cells to which "3" is to be written and the memory cells to which "4" are to be written have reached desired threshold values.

The write verify operation will be described with reference to FIGS. First, it is detected whether the memory cell to which "3" is to be written has reached a predetermined threshold value. First, at time t1ys, the voltages VA and VB are set to 1.
8V and 1.5V, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. Signals BLCA, BL
When CB becomes "L", the bit line BLa is disconnected from the MOS capacitor Qd1, the bit line BLb is disconnected from the MOS capacitor Qd2, and the bit lines BLa and BLb are floating. When the signals PREA and PREB become “L”, the MO
Node N which is the gate electrode of S capacitor Qd1, Qd2
1 and N2 are in a floating state. Subsequently, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is 1.5V, the non-selection control gates CG1A, CG3A, CG4A and the selection gate S
G1A and SG2A are set to Vcc. If the threshold value of the selected memory cell is 1.5 V or less, the bit line voltage becomes 1.V.
It becomes lower than 5V. If the threshold value of the selected memory cell is 1.5 V or more, the bit line voltage remains at 1.8 V. At time t2ys, the signals BLCA and BLCB are set to "H", and the bit line potential is transferred to N1 and N2. After that, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit lines BLb and M
OS capacitor Qd2 is disconnected. After this time t3ys
VRFYBA1C becomes Vcc, and Qn2C is turned "ON" in the case of "2" write and in the case of "4" write.
Then, the node N1 is discharged to 0V. When the signal VRFYBAC becomes "L" at time t4ys, in the data circuit holding "1" or "2" write data, the p-channel MOS transistor Qp12C is "ON" and the node N1 becomes Vcc. As a result, the node N1 becomes Vcc in the case of "1" write or "2" write, and becomes 0 V in the case of "4" write.

The signals SAN1 and SAP1 become "L" and "H" respectively, the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized. Thereafter, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t5ys. As a result, only the data circuit holding the “3” write data detects whether the data of the corresponding memory cell is sufficiently in the “3” write state. If the data of the memory cell is "3", the write data is changed to "1" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data of the memory cell is not "3", the flip-flop FF1 senses and latches the voltage of the node N2, and the write data is held at "3". Thereafter, additional writing is performed. The write data of the data circuit holding the “1”, “2” or “4” write data is not changed.

Next, the selected control gate is set to 2.5V. If the threshold of the selected memory cell is less than 2.5V, the bit line voltage will be less than 1.5V. If the threshold value of the selected memory cell is 2.5 V or more, the bit line voltage remains at 1.8 V. PRE at time t6ys
A and PREB become Vcc, and nodes N1 and N2 become 1.8.
After V and 1.5V, it becomes floating. Thereafter, at time t7ys, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. After that, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit lines BLb and M
OS capacitor Qd2 is disconnected. When the signal VRFYBAC becomes "L" at time t8ys, the data circuit holding "1" or "2" write data and "3"
In a data circuit in which "1" write data is held due to sufficient writing, a p-channel MOS
The transistor Qp12C is "ON" and the node N1 is at V
cc.

The signals SAN1 and SAP1 become "L" and "H", respectively, so that the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and is equalized. Thereafter, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t9ys. As a result, only the data circuit holding the “4” write data detects whether the data of the corresponding memory cell is sufficiently in the “4” write state. If the data of the memory cell is "4", the write data is changed to "2" by sensing and latching the voltage of the node N1 by the flip-flop FF1, and the write operation is not performed thereafter. If the data in the memory cell is not "4", the voltage of the node N1 is sensed and latched by the flip-flop FF1, so that the write data is "4".
After that, additional writing is performed. The write data of the data circuit holding the “1”, “2” or “3” write data is not changed.

If all the selected memory cells have reached the desired threshold, the node N4C of the data circuit goes to "L". By detecting this, it is known whether or not all the selected memory cells have reached the desired threshold. For example, the write end detection transistor Qn5C may be used to detect the write end as shown in FIG.
After the verify read, VRTC is first precharged to, for example, Vcc. If there is at least one insufficiently written memory cell, the n-channel MOS transistor Qn5C turns "ON" because the node N4C of the data circuit is "H",
VRTC falls from the precharge potential. When all the memory cells are sufficiently written, the data circuits 3-0, 3-
All the nodes N4C of 1,..., 3-m-1, 3-m become “L”. As a result, n-channel MOS in all data circuits
Since the transistor Qn5C is turned "OFF", VRTC maintains the precharge potential, and the end of writing is detected.

[Fourth Embodiment] In the second and third embodiments, as shown in FIG. 6, when a write operation is performed on a memory cell in the erased state “1” based on externally input write data, The threshold distribution in the “3” state written in the lower page write operation has a higher threshold level than the threshold distribution in the “2” state written in the page write operation. In the present embodiment, as shown in FIG. 3, the threshold distribution in the “2” state written in the write operation of the upper page is opposite to the threshold distribution in the “3” state written in the write operation of the lower page. It has a high threshold level. FIG. 18 shows the data circuit of this embodiment. Hereinafter, write and read operations will be described.

<Program and Verify Read of Upper Page> The write operation of the upper page is almost the same as in the second embodiment. FIG. 38 shows the write data, FIG. 20 shows the write timing, and FIG. 39 shows the verify read operation timing. The difference from the second embodiment is that the selected control gate voltage during the verify read (FIG.
9). In the present embodiment, since the memory cell to be programmed performs programming in the "2" state having a threshold value between 1.5 V and 1.8 V, the verify voltage (CG2A in FIG. 39) of the selected memory cell is 1 0.5V. As a result, the memory cell to which "2" is written is written until the threshold value becomes 1.5V.

<Writing of lower page> (1) Reading of upper data and data inversion, and data loading Reading of upper data and data inversion are performed in substantially the same manner as in the second embodiment (FIG. 23). However, in the second embodiment, the control gate voltage selected at the time of reading (FIG.
3 is 0 V, but in the present embodiment, “2”
Due to the different threshold levels of the state and the "3" state, it is 1V instead of 0V.

(2) Program FIG. 40 shows the program data of the lower page. When the input data is "H", the state is maintained at "1" or "2". When the input data is "L", the "1" state is written to the "3" state, and the "2" state is written to the "4" state. FIG. 41 shows the nodes of the data circuit at the time of writing the lower page. FIG. 42 is a timing chart of the write operation. At time t1ps, the voltage VA becomes the bit line write control voltage 2V, and the bit line BLa becomes 2V. When the voltage drop by the threshold value of n-channel MOS transistor Qn39 becomes a problem, signal BLCA may be boosted. Subsequently, the signal PREA changes to "L" to float the bit line. Next, at time t2ps, the signal RV2A is set to 1.5V. As a result, the bit line control voltage 0V is applied to the bit line from the data circuit holding the data “2” or “4”. Assuming that the threshold value of the n-channel MOS transistor Qn32 is 1 V, when writing "1" or "3", the n-channel MOS transistor
The transistor Qn32 is turned "ON" when "OFF", "2" or "4" is written. Then, at time t3ps, V
RFYBAC becomes 0V, and the bit line write control voltage Vcc is output to the bit line from the data circuit holding data "1" or data "2". as a result,
The bit line for writing “1” or “2” is Vc
c, The bit line for writing "3" has 2V, and the bit line for writing "4" has 0V. At time t4ps, the control gate / selection gate drive circuit 2 selects the selection gate SG1A and the control gates CG1A to CG4A of the selected block.
Becomes Vcc. The selection gate SG2A is at 0V. Next, the selected control gate CG2A is set to the high voltage Vpp (for example, 20 V) and the non-selected control gates CG1A, CG3A, C
G4A becomes VM (for example, 10 V). In a memory cell corresponding to a data circuit holding data “4”,
Due to the potential difference between the channel potential of 0 V and the potential Vpp of the control gate, electrons are injected into the floating gate, and the threshold increases.
In the memory cell corresponding to the data circuit holding data “3”, the channel potential of 2V and the control gate Vpp
, Electrons are injected into the floating gate to increase the threshold. The reason why the channel potential in the case of writing “3” is 2 V is to make the injection amount of electrons smaller than in the case of writing “4” data. In a memory cell corresponding to a data circuit in which data "1" or "2" is held, electrons are not effectively injected into the floating gate because the potential difference between the channel potential and Vpp of the control gate is small. Therefore, the threshold value of the memory cell does not change. During a write operation, signals SAN1, SAN2, PRE
B, BLCB are “H”, and signals SAP1, SAP2, VR
FYBA1C, RV1A, RV1B, RV2B, ECH
1, ECH2 is "L" and voltage VB is 0V.

(3) Verify read of lower page After the write operation, it is detected whether or not the write has been sufficiently performed (write verify). If the desired threshold value has been reached, the node N3 of the flip-flop FF1
Change C to "H". If the threshold value has not been reached, the data of the data circuit is held and the write operation is performed again. The write operation and the write verify are repeated until all the memory cells to which "3" is to be written and the memory cells to which "4" are to be written have reached desired threshold values.

The write verify operation will be described with reference to FIGS. First, it is detected whether the memory cell to which "3" is to be written has reached a predetermined threshold value. First, at time t1yy, the voltages VA and VB are respectively set to 1.
8V and 1.5V, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. Signals BLCA, BL
When CB becomes "L", the bit line BLa is disconnected from the MOS capacitor Qd1, the bit line BLb is disconnected from the MOS capacitor Qd2, and the bit lines BLa and BLb are floating. When the signals PREA and PREB become “L”, the MO
Node N which is the gate electrode of S capacitor Qd1, Qd2
1 and N2 are in a floating state. Subsequently, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 has a voltage of 0.5 V, and the non-selected control gates CG1A, CG3A, CG4A and the selection gate S
G1A and SG2A are set to Vcc. If the threshold value of the selected memory cell is 0.5 V or less, the bit line voltage becomes 1.V.
It becomes lower than 5V. If the threshold value of the selected memory cell is 0.5 V or more, the bit line voltage remains at 1.8 V.

At time t2yy, signals BLCA and BLCB are set to "H", and the bit line potential is transferred to N1 and N2. After that, the signals BLCA and BLCB become "L", and the bit line BLa is separated from the MOS capacitor Qd1, and the bit line BLb is separated from the MOS capacitor Qd2. Thereafter, at time t3yy, RV2A becomes 1.5V, and in the case of "2" writing and "4" writing, the node N1 is discharged to 0V. When the signal VRFYBAC becomes "L" at time t4yy, in the data circuit holding "1" or "2" write data, the p-channel MOS transistor Qp12C is "ON" and the node N1 becomes Vcc. As a result, the node N1 writes “1” or “2”.
Vcc for writing, 0 for "4" writing
V.

Signals SAN1 and SAP1 become "L" and "H", respectively, so that flip-flop FF1 is inactivated, and signal ECH1 becomes "H" and equalized. Thereafter, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t5yy. As a result, only the data circuit holding the “3” write data detects whether the data of the corresponding memory cell is sufficiently in the “3” write state. If the data of the memory cell is "3", the write data is changed to "1" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data of the memory cell is not "3", the flip-flop FF1 senses and latches the voltage of the node N2, and the write data is held at "3". Thereafter, additional writing is performed. The write data of the data circuit holding the “1”, “2” or “4” write data is not changed.

Next, the selected control gate is set to 2.5V. If the threshold of the selected memory cell is less than 2.5V, the bit line voltage will be less than 1.5V. If the threshold value of the selected memory cell is 2.5 V or more, the bit line voltage remains at 1.8 V. PRE at time t6yy
A and PREB become Vcc, and nodes N1 and N2 become 1.8.
After V and 1.5V, it becomes floating. Thereafter, at time t7yy, the signals BLCA and BLCB are set to "H", and the potential of the bit line is transferred to N1 and N2. After that, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit lines BLb and M
OS capacitor Qd2 is disconnected. When the signal VRFYBAC becomes "L" at time t8yy, the data circuit holding "1" or "2" write data and "3"
In a data circuit in which "1" write data is held due to sufficient writing, a p-channel MOS
The transistor Qp12C is "ON" and the node N1 is at V
cc.

The signals SAN1 and SAP1 become "L" and "H", respectively, so that the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and is equalized. Thereafter, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t9yy. As a result, only the data circuit holding the “4” write data detects whether the data of the corresponding memory cell is sufficiently in the “4” write state. If the data of the memory cell is "4", the write data is changed to "2" by sensing and latching the voltage of the node N1 by the flip-flop FF1, and the write operation is not performed thereafter. If the data in the memory cell is not "4", the voltage of the node N1 is sensed and latched by the flip-flop FF1, so that the write data is "4".
After that, additional writing is performed. The write data of the data circuit holding the “1”, “2” or “3” write data is not changed.

If all the selected memory cells have reached the desired threshold, the node N4C of the data circuit goes to "L". By detecting this, it is known whether or not all the selected memory cells have reached the desired threshold. For example, the write end detection transistor Qn5C may be used to detect the write end as shown in FIG.
After the verify read, VRTC is first precharged to, for example, Vcc. If there is at least one insufficiently written memory cell, the n-channel MOS transistor Qn5C turns "ON" because the node N4C of the data circuit is "H",
VRTC falls from the precharge potential. When all the memory cells are sufficiently written, the data circuits 3-0, 3-
All the nodes N4C of 1,..., 3-m-1, 3-m become “L”. As a result, n-channel MOS in all data circuits
Since the transistor Qn5C is turned "OFF", VRTC maintains the precharge potential, and the end of writing is detected.

<Read of upper page> In reading of the upper page, whether the memory cell is "1" or "3",
Alternatively, "2" or "4" is read. For this purpose, 1 V may be applied to the selected control gate to detect whether a current flows. The timing diagram is shown in FIG.
At time t3RD in FIG. 30, flip-flop FF
After the data is latched by 2 and CENB2 is set to "H", the write data of the upper page is output to the outside. Flip flop FF at this time
The data of No. 2 is shown in FIG.

<Reading of lower page> In reading of lower page, whether the memory cell is "0" or "2",
Alternatively, "1" or "3" is read. The timing charts are shown in FIG. 30 and FIG. FIG. 34 shows the flip-flop node as a result of reading. The data of the lower page is flip-flop 1 (node N3C,
N4C). By activating CENB1, lower page data can be output to the outside.

As can be seen from the above description, reading of the upper page is an operation up to time t3RD of reading of the lower page. Therefore, for example, when reading the lower page subsequent to the upper page, the lower page data may be read while the upper page data is being output to the outside of the chip after reading the upper page first. . That is, at the time t3RD, the data of the upper page is latched by the flip-flop FF2 and output to the outside of the chip, and at the same time, the operation after the time t3RD shown in FIGS. . As a result, the lower page can be apparently written at a high speed.

<Another Write Method for Lower Page> In the above embodiment, when writing the lower page, the data of the upper page is read and the data is inverted. As in the third embodiment, the data inversion operation of the upper page can be omitted in this embodiment. FIG. 18 shows the data circuit. The timing chart for reading the upper data is almost the same as that until time t4yd in FIG. 23 is different from FIG. 23 in that the CG2A is set to 1 V instead of 0 V because the “2” state has a threshold value between 1.5 V and 1.8 V in this embodiment. The operation timings of the program and verify read are shown in FIGS. 44 and 45. The details of the operation are almost the same as those of the third embodiment, and a detailed description is omitted here.

[Fifth Embodiment] In the present embodiment, "1"
The state has a first threshold level and the "2" state is a second state.
The "3" state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is the i-th state. In a memory cell storing an n value having a threshold level, FIG.
, The memory cells are in the “1” state, the “2” state,.
When the “2 ^k−1 −1” state or the “2 ^k−1 ” state (k is a natural number of 2 or more) is held, based on write data input from outside the memory cell and data held by the memory cell. , The memory cells are set to a “1” state, a “2” state,.
When the memory cell is set to the “2 ^k −1” state or the “2 ^k ” state and the memory cell holds the “1” state, the “2” state,..., The “2 ^k −1” state or the “2 ^k ” state, Based on write data input from outside the cell and data held by the memory cell, the memory cell is set to a “1” state, a “2” state,
, "2 ^{k + 1} -1" state or "2 ^{k +1} " state, and the memory cells are in "1" state, "2" state, ..., "2 ^m-1 -1" state.
When the state or the “2 ^m−1 ” state (m is a natural number that satisfies n = 2 ^m ) is held, the memory cell is set to “based on the write data input from outside the memory cell and the data held by the memory cell. 1 "state," 2 "state, ...," 2 ^m
-1 "state or" 2 ^m "state.

For example, in the case of a four-level memory cell, FIG.
When the memory cell holds the “1” state or the “2” state as described above, based on the write data input from outside the memory cell and the data held by the memory cell,
The memory cell is set to a “1” state, a “2” state, a “3” state, or a “4” state.

In this embodiment, as shown in FIG.
In the write operation, when the first logical level is input, the memory cell is set to the “1” state, when the second logical level is input, the memory cell is set to the “2” state, and thereafter, the result of the first write operation is “1”. The memory cell in the state is set to “1” when the third logic level is input in the second write operation.
State, when the fourth logical level is input, the state becomes "3". When the third logical level is input in the second write operation, the memory cell in the "2" state as a result of the first write operation is input. It is characterized in that the state becomes "2" and the state becomes "4" when the fourth logic level is inputted.

In this embodiment, the “1” state has a first threshold level, the “2” state has a second threshold level, and the “3” state has a third threshold level. Value level,
The “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) holds a memory cell storing an n value having an i-th threshold level and write data of the memory cell. The data circuit is configured as shown in FIG.

When the memory cell holds the “1” state or the “2” state, after the data circuit holds the write data input from outside the memory cell and the data read from the memory cell, The memory cell is set to a “1” state, a “2” state, a “3” state, or a “4” state based on data held in the data circuit.

In the first write operation, when the write data is at the first logical level according to the first write data held in the data circuit, the memory cell goes into the “1” state, and Is at the second logic level, the state becomes "2". After that, after the data circuit holds the write data input from outside the memory cell and the data read from the memory cell, the memory cell When the data circuit holds that the state is "1" and the second write data is at the third logic level, the memory cell is in the state "1", the memory cell is in the state "1", and If the data circuit holds that the data is at the fourth logic level, the memory cell is in the "3" state, the memory cell is in the "2" state and the second write When the data circuit holds that the data is at the third logic level, the memory cell is in the "2" state, the memory cell is in the "2" state and the second write data is at the fourth logic level. When the data circuit holds the memory cell, the memory cell enters the state "4".

Therefore, in the case of a four-level memory cell, for example, a threshold distribution as shown in FIG. 46 may be used. Writing may be performed as shown in FIGS. The data circuit may be composed of, for example, a first latch circuit and a second latch circuit.

In the first write operation, the first write data is input from the I / O line to the first latch circuit, and the write data is changed to the first logic according to the first write data held in the data circuit. When the write data is at the second logical level, the memory cell is in the "1" state. When the write data is at the second logical level, the memory cell is in the "2" state. In the second write operation, the first latch circuit in the data circuit latches the second write data input from outside the memory cell,
Hold the first write data read from the memory cell. Thereafter, when the data circuit holds that the memory cell is in the “1” state and the second write data is at the third logic level, the memory cell is in the “1” state and the memory cell is in the “1” state. If the data circuit holds that the memory cell is in the state and the second write data is at the fourth logic level, the memory cell is in the "3" state, the memory cell is in the "2" state, and the second write If the data circuit holds that the data is at the third logic level, the memory cell is in the "2" state, the memory cell is in the "2" state and the second write data is at the fourth logic level. If the data circuit holds that there is, the memory cell is in the "4" state. The present embodiment is not limited to the four-valued memory cell, but may be an eight-valued memory cell if collapsed, a sixteen-valued memory cell, or a 2 ^m value (m is a natural number)
It may be a memory cell. The information stored in one memory cell is not limited to a multiple of 2, but may be a ternary, quinary, quinary, ten, or 280 value.

FIGS. 48 and 49 show an example of the threshold value distribution and the write operation of the 8-level memory cell. The data circuit may be composed of, for example, a first latch circuit, a second latch circuit, and a third latch circuit.

In the first write operation, the first write data is input from the I / O line to the first latch circuit, and the write data is changed to the first logic according to the first write data held in the data circuit. When the write data is at the second logical level, the memory cell is in the "1" state. When the write data is at the second logical level, the memory cell is in the "2" state. In the second write operation, the first latch circuit in the data circuit latches the second write data input from outside the memory cell,
Hold the first write data read from the memory cell. Thereafter, when the data circuit holds that the memory cell is in the “1” state and the second write data is at the third logic level, the memory cell is in the “1” state and the memory cell is in the “1” state. When the data circuit holds that the memory cell is in the state and the second write data is at the fourth logic level, the memory cell is in the "3" state, the memory cell is in the "2" state and the second write If the data circuit holds that the data is at the third logic level, the memory cell is in the "2" state, the memory cell is in the "2" state, and the second write data is at the fourth logic level. If the data circuit holds that there is, the memory cell is in the "4" state. In the third write operation, the first latch circuit in the data circuit latches third write data input from outside the memory cell, and the second and third latch circuits are read from the memory cell. The first write data and the second write data are held. Thereafter, when the level is from the third write data to the fifth logic level, the memory cell maintains the “1”, “2”, “3”, or “4” state. When the third write data is at the sixth logic level, the memory cells in the “1” state, “2” state, “3” state, and “4” state are “5” state and “6” state, respectively. Status,
The state becomes "7" state or "8" state.

FIGS. 50 and 51 show an example of the threshold distribution and write operation of the 16-level memory cell. The data circuit may include, for example, a first latch circuit, a second latch circuit, a third latch circuit, and a fourth latch circuit.

In the first write operation, the first write data is input from the I / O line to the first latch circuit, and the write data is changed to the first logic according to the first write data held in the data circuit. When the write data is at the second logical level, the memory cell is in the "1" state. When the write data is at the second logical level, the memory cell is in the "2" state. In the second write operation, the first latch circuit in the data circuit latches the second write data input from outside the memory cell, and
Hold the first write data read from the memory cell. Thereafter, when the data circuit holds that the memory cell is in the “1” state and the second write data is at the third logic level, the memory cell is in the “1” state and the memory cell is in the “1” state. When the data circuit holds that the memory cell is in the state and the second write data is at the fourth logic level, the memory cell is in the "3" state, the memory cell is in the "2" state and the second write If the data circuit holds that the data is at the third logic level, the memory cell is in the "2" state, the memory cell is in the "2" state, and the second write data is at the fourth logic level. If the data circuit holds that there is, the memory cell is in the "4" state. In the third write operation, the first latch circuit in the data circuit latches third write data input from outside the memory cell, and the second and third latch circuits are read from the memory cell. The first write data and the second write data are held. Thereafter, when the third write data is at the fifth logic level, the memory cell becomes “1”.
Alternatively, the state “2”, “3”, or “4” is maintained. When the third write data is at the sixth logic level,
The memory cells in the “1” state, the “2” state, the “3” state, and the “4” state are “5” state, “6” state, and “7” state, respectively.
State, "8" state.

In the fourth write operation, the first latch circuit in the data circuit operates manually from outside the memory cell.
, And the second, third, and fourth latch circuits hold the first write data, the second write data, and the third write data read from the memory cells. Thereafter, when the fourth write data is at the seventh logical level, the memory cell is “1” or “2” or “3” or “4” or “5” or “6” or “7” or Maintain “8” state. When the fourth write data is at the eighth logic level, the state is “1”,
"2" state, "3" state, "4" state, "5" state,
The memory cells in the “6” state, the “7” state, and the “8” state are:
State "9", state "10", state "11",
"12" state, "13" state, "14" state, "15" state
State, "16" state. FIG. 52 shows an example of a threshold distribution and a write operation of a 2 ^m value (m is a natural number) memory cell.
FIG. The data circuit is, for example, a first latch circuit,
The second latch circuit, the third latch circuit, the fourth latch circuit,..., The m-th latch circuit may be used.

In the first write operation, the first write data is input from the I / O line to the first latch circuit, and the write data is changed to the first logic according to the first write data held in the data circuit. When the write data is at the second logical level, the memory cell is in the "1" state. When the write data is at the second logical level, the memory cell is in the "2" state. In the second write operation, the first latch circuit in the data circuit latches the second write data input from outside the memory cell, and
Hold the first write data read from the memory cell. Thereafter, when the data circuit holds that the memory cell is in the “1” state and the second write data is at the third logical level, the memory cell is in the “1” state and the memory cell is in the “1” state. When the data circuit holds that the memory cell is in the state and the second write data is at the fourth logic level, the memory cell is in the "3" state, the memory cell is in the "2" state, and the second write If the data circuit holds that the data is at the third logic level, the memory cell is in the "2" state, the memory cell is in the "2" state and the second write data is at the fourth logic level. If the data circuit holds the memory cell, the memory cell enters the "4" state.

In the third write operation, the first latch circuit in the data circuit receives the third input from outside the memory cell.
, And the second and third latch circuits hold the first write data and the second write data read from the memory cells. Then the third
Is the fifth logic level,
The memory cell keeps “1” or “2” or “3” or “4” state. When the third write data is at the sixth logic level, the “1” state, the “2” state, the “3” state,
The memory cells in the “4” state are “5” state,
The states are "6" state, "7" state and "8" state. In the fourth write operation, the first latch circuit in the data circuit latches the fourth write data input from outside the memory cell, and the second, third, and fourth latch circuits read from the memory cell. The output first write data, second write data, and third write data are held. Thereafter, when the fourth write data is at the seventh logical level, the memory cell is “1” or “2” or “3” or “4” or “5” or “6” or “7” or Keep "8" state. When the fourth write data is at the eighth logic level, the “1” state, the “2” state, the “3” state,
"4" state, "5" state, "6" state, "7" state,
The memory cells in the “8” state are the “9” state and the “1” state, respectively.
The states are "0" state, "11" state, "12" state, "13" state, "14" state, "15" state and "16" state.

In the m-th write operation, the first latch circuit in the data circuit inputs the m-th input from outside the memory cell.
, The second, third, fourth,...,
The m-th latch circuit holds the first write data, the second write data, the third write data,..., The (m−1) -th write data read from the memory cells. Thereafter, the m-th write data is changed to the (2m-
If the logic level is 1), the memory cell is "1".
"Or" 2 "or" 3 "... or" 2 ^m-1 -1 "or" 2
^m-1 "state. When the m-th write data is at the 2m-th logic level, the" 1 "state, the" 2 "state,
The memory cells in the “3” state,..., “2 ^m−1 −1” state, and “2 ^m−1 ” state are “2 ^m−1 +1” state and “2 ^m−1 +1” state, respectively.
^m-1 +2 "state,...," 2 ^m -1 "state, and" 2 ^m "state.

[Sixth Embodiment] In the present embodiment, "1"
The state has a first threshold level and the "2" state is a second state.
The "3" state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) is the i-th state. In a memory cell capable of storing a plurality of bits of data that stores an n value having a threshold level, a threshold distribution of data written in a p-th (p is a natural number of 1 or more) write operation The width is smaller than the threshold distribution width of the threshold distribution width of data newly written in the (p + 1) th write operation. This embodiment will be described with reference to the drawings, taking a 4-level NAND flash memory as an example. A single memory cell can store a plurality of bits of data that can be divided into upper bits and lower bits. Each of the plurality of bits of data is written to a memory cell group forming a page which is a unit of data writing by upper bit data in an upper page write operation and lower bit data in a lower page write operation.

FIG. 54 shows the write operation procedure. That is, FIG. 54A is a diagram showing writing of the upper page. When the write data of the upper page is High, the memory cell keeps the “1” state, which is the erased state, and Lo.
In the case of w, the memory cell is written to the "2" state.
FIG. 54B is a diagram showing writing of a lower page. When the write data of the lower page is High, the memory cells in the “1” state and “2” state maintain that state, and when the write data in the lower page is Low, the memory cell in the “1” state is “3”.
In the state, the memory cell in the “2” state is written to the “4” state. By writing data in one memory cell in a plurality of pages as described above, writing is speeded up. As shown in FIG. 54, in the lower page write, a "3" verify read for checking whether the "3" write has been sufficiently performed and a "4" verify read for checking whether the "4" write has been sufficiently performed are performed. On the other hand, in the writing of the upper page, only the "2" verify read for checking whether the "2" writing has been sufficiently performed is performed. In addition, normally, as the data has a higher threshold level such as the “4” state, the verify read operation itself tends to be longer. Therefore, in order to shift the threshold value of the transistor of the memory cell in such a write operation, when a pulse as a write bias is supplied to the word line, the write bias is gradually increased until sufficient writing is performed. If the increase width (step-up width of the write voltage) is equal in the writing of the upper page and the lower page, the writing of the upper page can be performed faster than the writing of the lower page.

However, the write time usually defined by the time required for page write is ultimately determined by the longer time of the upper page write and the lower page write, and the chip write time specification is longer than the write time of the chip. Is set to the write time of the lower page. Therefore, there is little advantage even if only the writing of the upper page is performed at high speed. In the present embodiment, in consideration of such points, the writing of the upper page is slowly performed with high accuracy so that the writing time of the upper page is substantially equal to the writing time of the lower page. That is, the step-up width of the write voltage when writing the upper page is ΔV
pp1, when the step-up width of the write voltage at the time of writing the lower page is ΔVpp2, ΔVpp1 <ΔVpp
Satisfy the relationship of 2. By performing the writing of the upper page with high accuracy in this manner, the threshold distribution width of the memory cell in the “2” state is narrowed, and the reliability of the memory cell is improved. Hereinafter, the present embodiment will be described in more detail in comparison with the case where ΔVpp1 = ΔVpp2.

FIG. 55 shows that the step-up width of the write voltage is equal between the upper page and the lower page (ΔVpp1 = Δ
Vpp2), the threshold distribution width of data "2" written in the upper page write operation is equal to the threshold distribution width of data "3" and "4" newly written in the lower page write operation. FIG. 14 is a diagram showing a threshold distribution of a memory cell when the values are equal. VCG2V, VCG3V, VC in the figure
G4V stores data “2”, “3”,
This corresponds to a verify voltage for checking whether "4" has been sufficiently written. FIG. 56 shows a waveform of a pulse supplied to the memory cell in writing here.

As shown in FIG. 55, the "2" state,
All threshold distribution widths of the “3” state and the “4” state are 0.
When the voltage is 8 V, the write voltage of the upper page is increased by, for example, 0.8 V from the initial value of 15 V as shown in FIG. The lower page write voltage has an initial value of 17.8 V obtained by adding the voltage difference between the verify voltage for “2” write and the verify voltage for “4” write to the initial value of the write voltage for the upper page.
It is also increased from 7.8V by 0.8V. Further, at this time, the channel and bit line of the memory cell to which "4" is written are set to 0 V, and the channel and bit line of the memory cell to which "3" is written are set to the verify voltage for "3" write and the verify voltage for "4" write. By setting the voltage to 1.4 V corresponding to the voltage difference, the “3” state and the “4” state can be written almost simultaneously in the lower page write operation. On the other hand, FIG. 57 shows the threshold voltage distribution of the memory cell in this embodiment, and FIG. 5 shows the waveform of the pulse supplied to the memory cell during writing.
8, shown in FIG. First, in order to obtain the threshold distribution shown in FIG. 57A, a pulse as shown in FIGS. 58A and 58B may be used as the write voltage. By supplying a pulse that increases by 0.3 V from the initial value of 15 V as the write voltage for the upper page, the threshold distribution width in the “2” state can be reduced to 0.3 V. When the step-up width of the write voltage is reduced in this manner, writing is performed with high accuracy, but the writing time is lengthened. Therefore, it is preferable that the magnitude of the step-up width of the write voltage is set so that the write time including the time required for the verify read is substantially the same between the writing of the upper page and the writing of the lower page.

On the other hand, the write voltage for the lower page is as shown in FIG.
As shown in (b), the initial value is increased from 17.3V by 0.8V. That is, the initial value of the write voltage of the lower page is obtained by adding the voltage difference between the verify voltage for “2” write and the verify voltage for “4” write to the initial value of the write voltage of the upper page.
3 V, and the step-up width of the write voltage is shown in FIG.
0.8 V as in the case of obtaining the threshold distribution of 5. At this time, the channel and the bit line of the memory cell to which "4" is to be written are set to 0 V, and the channel and the bit line of the memory cell to which "3" is to be written are the voltages of the verify voltage for "3" write and the verify voltage for "4" write. By setting to 1.4V, which corresponds to the difference,
In the lower page write operation, the "3" state and the "4" state can be written almost simultaneously. Here, FIG.
As shown in (a), the threshold distribution width of the “2” state is narrowed to 0.3 V, so that the threshold distribution of the “4” state having the highest threshold level is about 0 .5V. As a result, in the memory cell, the leakage of the charge stored in the floating gate to the substrate can be suppressed, and the data retention time of the memory cell can be lengthened by about two to three times to improve the reliability. When the writing of the upper page is performed with high accuracy, the writing speed of the upper page is reduced. However, since the writing of the lower page takes a longer time, the specification of the writing speed of the chip is determined by the writing speed of the lower page, so unless the writing speed of the upper page is lower than the writing speed of the lower page. The writing speed specification of the chip does not decrease.

In the present embodiment, the threshold voltage distribution of the memory cell is not limited to the above, but has arbitrary characteristics. For example, a threshold distribution as shown in FIG. That is, also in this case, the threshold distribution width of the “2” state is narrowed to 0.3 V by writing the upper page with high accuracy. However, here, "3"
Both the voltage difference between the threshold distribution in the state and the threshold distribution in the “4” state and the voltage difference between the threshold distribution in the “2” state and the threshold distribution in the “3” state 55 and 57
It is set larger than that of FIG. Specifically, FIG.
In FIG. 5 and FIG. 57 (a), the voltage difference between such threshold distributions is 0.6 V, and when the data “3” or “4” is held in the memory cell, the accumulated charge in the floating gate is reduced. If the decrease of the threshold value due to the leak exceeds 0.6 V, the memory cell may be in the "2" state or the "3" state, and data may be destroyed. On the other hand, FIG.
Since the voltage difference between the threshold distributions in (b) is 0.8 V, the data will not be destroyed unless the similar threshold decrease exceeds 0.8 V, and as a result, the life of the memory cell is improved. Reliability is improved.

In order to obtain the threshold distribution shown in FIG. 57 (b), a pulse as shown in FIGS. 58 (a) and 58 (c) may be used as the write voltage. By supplying a pulse that increases by 0.3 V from the initial value of 15 V as the write voltage of the upper page, the threshold distribution width of the “2” state is set to 0.1.
It can be reduced to 3V. When the step-up width of the write voltage is reduced in this manner, writing is performed with high accuracy, but the writing time is lengthened. Therefore, it is preferable that the magnitude of the step-up width of the write voltage is set so that the write time including the time required for the verify read is substantially the same between the writing of the upper page and the writing of the lower page. On the other hand, the write voltage of the lower page is increased by 0.8 V from the initial value of 17.7 V as shown in FIG. That is, the initial value of the write voltage of the lower page is set to 17.7 V which is the initial value of the write voltage of the upper page plus the voltage difference between the verify voltage for "2" write and the verify voltage for "4" write. The step-up width of the voltage is set to 0.8 V as in the case of obtaining the threshold distribution in FIG. At this time, the channel and the bit line of the memory cell to which “4” is written are set to 0 V,
The channel and bit line of the memory cell to which "3" is written correspond to the voltage difference between the verify voltage for "3" write and the verify voltage for "4" write.
By setting the voltage to 6 V, the “3” state and the “4” state can be written almost simultaneously in the lower page write operation.

FIG. 57C shows another example of the threshold voltage distribution of the memory cells. In FIGS. 57A and 57B, the voltage difference between the threshold distribution in the “3” state and the threshold distribution in the “4” state, and the threshold voltage distribution in the “2” state and “3” Although the voltage difference between the threshold distributions in the “state” is set equal, the voltage difference between the threshold distribution in the “3” state and the threshold distribution in the “4” state is “2”. The voltage difference between the threshold distribution in the “3” state and the threshold distribution in the “3” state is made larger. That is, considering that the higher the threshold level is, the more the accumulated charge in the floating gate leaks and the lower the threshold is, the threshold distribution in the “2” state and the threshold in the “3” state are considered. 0.7V voltage difference between distributions
In contrast, the voltage difference between the threshold distribution in the “3” state and the threshold distribution in the “4” state is 1V.

In order to obtain the threshold distribution shown in FIG. 57 (c), a pulse as shown in FIGS. 58 (a) and 58 (d) may be used as the write voltage. As the write voltage for the upper page, the initial value is 1 as in the case of FIGS. 57 (a) and (b).
A pulse which increases from 5V by 0.3V is supplied. On the other hand, the write voltage for the lower page is increased from the initial value of 17.8 V by 0.8 V as shown in FIG. That is, the initial value of the write voltage for the lower page is set to 17.8 V, which is the sum of the initial voltage of the write voltage for the upper page and the voltage difference between the verify voltage for "2" write and the verify voltage for "4" write. The step-up width of the voltage is set to 0.8 V as in the case of obtaining the threshold distribution in FIG. At this time, the channel and the bit line of the memory cell to which "4" is to be written are set to 0 V, and the channel and the bit line of the memory cell to which "3" is to be written are the voltages of the verify voltage for "3" write and the verify voltage for "4" write. By setting the voltage to 1.8 V corresponding to the difference, the “3” state and the “4” state can be written almost simultaneously at the time of the lower page write operation.

The memory cell of this embodiment is similar to that of FIG.
(D) or a threshold distribution as shown in FIG. 57 (e). Here, quaternary data “1”,
The magnitude relation between the threshold levels “2”, “3”, and “4” is different from FIGS. 57 (a), (b), and (c). That is,
As in the case of the fourth embodiment, when writing is performed on a memory cell in the erased state “1” based on write data input from the outside, a threshold of a “2” state written by a write operation of an upper page. The value distribution has a higher threshold level than the threshold distribution in the “3” state written by the lower page write operation. Also in these, the threshold distribution width of the “2” state is narrowed to 0.3 V by performing the writing of the upper page with high accuracy, and the threshold distribution of the “4” state, which is the highest threshold level, is reduced. It can be reduced. Further, in FIG. 57 (d), FIG.
7 (c), from the viewpoint of increasing the voltage difference between the threshold distributions for two data having a high threshold level,
The voltage difference between the threshold distribution in the “3” state and the threshold distribution in the “2” state is 0.6 V, and the voltage difference between the threshold distribution in the “2” state and the threshold distribution in the “4” state. Is set to 1V.

In order to obtain the threshold distribution shown in FIG. 57D, a pulse as shown in FIGS. 59A and 59B may be used as the write voltage. As the write voltage for the upper page, a pulse that increases by 0.3 V from the initial value of 16.4 V shown in FIG. 59A is supplied. On the other hand, the write voltage of the lower page is increased by 0.8 V from the initial value of 17.7 V as shown in FIG. That is, the initial value of the write voltage of the lower page is set to 17.7 V which is the initial value of the write voltage of the upper page plus the voltage difference between the verify voltage for "2" write and the verify voltage for "4" write. The step-up width of the voltage is set to 0.8 V as in the case of obtaining the threshold distribution in FIG. At this time, the channel and the bit line of the memory cell to which “4” is written are set to 0 V,
1. The channel and bit line of the memory cell to which "3" is written correspond to the voltage difference between the verify voltage for "3" write and the verify voltage for "4" write.
By setting the voltage to 7 V, the “3” state and the “4” state can be written almost simultaneously in the lower page write operation.

In FIG. 57 (e), the voltage difference between the threshold distribution in the "3" state and the threshold distribution in the "2" state, and
The voltage difference between the threshold distribution in the “2” state and the threshold distribution in the “4” state is both set to 0.6V.
In writing, the initial value of the write voltage of the lower page is 17.3 V, and the channel and bit line of the memory cell to which "3" is written in the lower page write operation are set to 2.3.
Except for V, the threshold distribution can be obtained in the same manner as in the case of FIG. The above is
Although the present embodiment has been described by taking the first write operation and the second write operation to the quaternary cell as an example, the present embodiment is not limited to this. That is, for a memory cell capable of storing a plurality of bits of data, the step-up width of the write voltage is set smaller in the preceding write operation than in the subsequent write operation, and the threshold value of the data written in the preceding write operation is set. The value distribution width may be narrower than the threshold distribution width of the threshold distribution width of data newly written in the subsequent write operation.

For example, the present embodiment may be applied to a 2 ^m value (m is a natural number) memory cell in the fifth embodiment. That is, the "1" state has a first threshold level, the "2" state has a second threshold level, the "3" state has a third threshold level, “I”
The state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is a memory cell storing an n value having an i-th threshold level. When the memory cell is at the level, the first write is performed based on the write data input from outside the memory cell, and the memory cell attains one of the threshold levels of the "1" state and the "2" state, The memory cell is in the "1" state,
When the threshold level is one of the “2” state,..., “2 ^k−1 −1” state, and “2 ^k−1 ” state (k is a natural number of 2 or more), The k-th write is performed based on the input write data and the threshold level of the memory cell.
.., “2 ^k −1” state, or “2 ^k ” state, and the memory cell becomes “1” state, “2” state ^,. If the threshold level is any of the 1 "state and the" 2 ^k "state, the (k + 1) th write is performed based on the write data input from outside the memory cell and the threshold level of the memory cell,
The memory cells are in a "1" state, a "2" state,.
The threshold level becomes ^{one of the (k +} 1−1) state and the “2 ^{k + 1} ” state, and the memory cell is in the “1” state, the “2” state,
..., "2 ^m-1 -1" state, "2 ^m-1 " state (m is n = 2
If the threshold level is any of (the number of self-heating that satisfies ^m ), the m-th write is performed based on the write data input from the outside of the memory cell and the threshold level of the memory cell. This embodiment can be applied to a case where the cell has any one of the threshold levels of “1” state, “2” state,..., “2 ^m −1” state, and “2 ^m ” state. is there. FIG. 60 shows the threshold distribution of the memory cell at this time.

On the other hand, the "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) is n For a memory cell storing a value, when the memory cell is at the threshold level of the "1" state, a first write is performed based on write data input from outside the memory cell, and the memory cell is set to "1". 1 "state," 2 "state, ...," m-
1 ”state or“ m ”state (m is a natural number of 2 or more), and the memory cell is in the“ 1 ”state,
When the threshold level is any of the “2” state,..., “M−1” state, and “m” state, the write data inputted from outside the memory cell and the threshold level of the memory cell are used. A second write is performed, and the memory cells are in a “1” state, a “2” state,..., A “k−1” state,
The present embodiment can be applied to any of the threshold levels in the “k” state (k is a natural number greater than m).
FIG. 61 shows the threshold voltage distribution of the memory cell at this time.

The "1" state has a first threshold level, the "2" state has a second threshold level,
The “3” state has a third threshold level, and the “i” state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) is n such that it has an i-th threshold level. Regarding the memory cell that stores the value, the threshold level of the memory cell is any one of “1” state, “2” state,..., “R−1” state, and “r” state (r is a natural number of 2 or more). , The j-th (j is a natural number of 2 or more) write is performed based on the write data input from outside the memory cell and the threshold level of the memory cell, and the memory cell is in the “1” state. , "S-1" state, "s" state (s
Is a natural number greater than r), and the memory cell is in the “1” state, the “2” state,.
If the threshold level is one of the "-1" state and the "s" state, the j + 1-th state is determined based on the write data input from outside the memory cell and the threshold level of the memory cell.
Is written, and the memory cell is in a "1" state.
, "T-1" state, "t" state (t is s
The present embodiment can be applied to any threshold level of (a larger natural number). FIG. 62 shows the threshold voltage distribution of the memory cells at this time. Further, the "1" state has a first threshold level, the "2" state has a second threshold level, the "3" state has a third threshold level, “I” state (where i is a natural number less than or equal to n and n
Is a natural number greater than or equal to 3) for a memory cell storing an n value having an i-th threshold level, the memory cell enters a “1” state when a first logic level is input during a first write operation. When the second logic level is input, the memory cell enters the “2” state, and the memory cell that is in the “A” state as a result of the k−1 (k is a natural number of 2 or more) write operation becomes the k-th state.
In this write operation, the present embodiment may be applied to the case where the state becomes "A" when the 2k-1 logical level is inputted, and the state becomes "A + 2 ^k-1 " when the 2k logical level is inputted. .

[Seventh Embodiment] The present embodiment will be described with reference to the drawings, taking a 4-level NAND flash memory as an example. The configuration of the multi-value storage type EEPROM of the present embodiment is as follows.
FIG. 7 is similar to the second embodiment, and the data circuit is the same as in FIG.
It is. In the present embodiment, the relationship between the four write states of the memory cells and the threshold is different from that of the second embodiment. FIG.
3 shows the threshold voltage of the memory cell M and four write states (four-level data “1”,
"2", "3", "4"). Data "1"
Is the same as the state after erasing, for example, has a negative threshold value. The "2" state has a threshold value between 0.5V and 0.8V, for example. The “3” state has a threshold value between, for example, 1.4V and 2.2V. The "4" state has a threshold between 2.8V and 3.6V, for example.

In this embodiment, for example, a read voltage of 1.1 V is applied to the control gate CG of the memory cell M, and the data of the memory cell is changed to “1” or “1” depending on whether the memory cell is “ON” or “OFF”. 2 ”or“ 3 ”or“ 4 ”. Subsequently, for example, the read voltage 2.
By applying 5V and 0V, data in the memory cell is completely detected. On the other hand, verify voltages VCG2V, VCG3V, VC
G4V is, for example, 0.5 V, 1.4 V, and 2.8 V, respectively.
It is said.

Hereinafter, the operation will be described in more detail. In the present embodiment, a quaternary storage is used as an example. n-channel MO
S transistors Qn21, Qn22, Qn23 and p-channel M
The write / read data is latched in a flip-flop FF1 composed of OS transistors Qp9, Qp10 and Qp11 and an FF2 composed of n-channel MOS transistors Qn29, Qn30 and Qn31 and p-channel MOS transistors Qp16, Qp17 and Qp18. These also operate as sense amplifiers. Flip flop F
F1 and FF2 latch “write“ 1 ”, write“ 2 ”, write“ 3 ”, or write“ 4 ”as write data information,
Whether the memory cell holds the information “1” or “2”
, Or "3" or "4" is sensed and latched as read data information. Data input / output line IO
A, IOB and flip-flop FF1 are connected via n-channel MOS transistors Qn28, Qn27. Data input / output lines IOA and IOB and flip-flop FF2 are connected to n-channel MOS transistors Qn35 and Qn35, respectively.
Connected via n36. Data input / output lines IOA, IO
B is also connected to the data input / output buffer 4 in FIG. The read data held in the flip-flop FF1 is output to IOA and IOB by activating CENB1. The read data held in the flip-flop FF2 is output to IOA and IOB by activating CENB2.

N-channel MOS transistors Qn26, Qn
n34 equalizes the flip-flops FF1 and FF2 when the signals ECH1 and ECH2 become "H". The n-channel MOS transistors Qn24 and Qn32 are
The connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd1 is controlled. The n-channel MOS transistors Qn25 and Qn33 are connected to flip-flops FF1 and FF2.
And the connection of the MOS capacitor Qd2. The circuit composed of the p-channel MOS transistors Qp12C and Qp13C responds to the activation signal VRFYBAC in accordance with the data of the flip-flop FF1 and the MOS capacitor Qd1.
Change the gate voltage of The circuit composed of p-channel MOS transistors Qp14C and Qp15C has an activation signal VR
By FYBBC, the gate voltage of the MOS capacitor Qd2 is changed according to the data of the flip-flop FF1. The circuit composed of the n-channel MOS transistors Qn1C and Qn2C responds to the activation signal VRFYBA1C in response to the data of the flip-flop FF2.
The gate voltage of the S capacitor Qd1 is changed. The circuit composed of n-channel MOS transistors Qn3C and Qn4C is flip-flopped by an activation signal VRFYBB1C.
According to the data of the flop FF2, the MOS capacitor Q
Change the gate voltage of d2.

The MOS capacitors Qd1 and Qd2 are constituted by depletion type n-channel MOS transistors.
This is made sufficiently smaller than the bit line capacity. n-channel MOS
The transistor Qn37 charges the MOS capacitor Qd1 to the voltage VA by the signal PREA. n-channel MOS
Transistor Qn38 charges MOS capacitor Qd2 to voltage VB in response to signal PREB. n-channel MOS
The transistors Qn39 and Qn40 output signals BLCA and BLC
B controls the connection between the data circuit 3 and the bit lines BLa and BLb, respectively. The circuit composed of the n-channel MOS transistors Qn37 and Qn38 also functions as a bit line voltage control circuit. Next, the EEPRO thus configured
The operation of M will be described with reference to a timing chart. Hereinafter, a case where the control gate CG2A is selected will be described.

<Writing of Upper Page> (1) Program of Upper Page The input data is input to the data circuit 3 via the data input / output buffer 4 before the write operation. The size of one page is 256 bits, and the data circuit is 256 bits.
If there are the write data, the input 256-bit write data of the upper page is input to the flip-flop FF1 via IOA and IOB when the column activation signal CENB1 is "H". Write data and node N of FF1
FIG. 19 shows the relationship between 3C and N4C. Input data is Hi
gh, the state is kept “1” and the input data is Low.
In the case of, it is written to the "2" state. The write operation is shown in FIG. VRFYBAC becomes 0 at time t1s
V, and the bit line write control voltage Vcc is output to the bit line from the data circuit holding the data “1”. Thereafter, when RV1A becomes Vcc at time t2s, the data circuit holding the data “2” outputs 0 from the data circuit.
V is output to the bit line. As a result, the bit line for writing “1” is Vcc, and the bit line for writing “2” is 0
V. At time t1s, the control gate / selection gate drive circuit 2 selects the selection gate SG1 of the selected block.
A, the control gates CG1A to CG4A become Vcc. The selection gate SG2A is at 0V. Next, at time t3s, the selected control gate CG2A is set to the high voltage Vpp (for example, an initial value of 15V) and the non-selected control gates CG1A, CG3A, CG
4A becomes VM (for example, 10V). In the memory cell corresponding to the data circuit holding data “2”, 0
Due to the difference between the channel potential of V and the potential of Vpp of the control gate, electrons are injected into the floating gate to raise the threshold.
In the memory cell corresponding to the data circuit holding the data “1”, the channel of the memory cell becomes floating because the selection gate SG1A is turned “OFF”.

As a result, the channel of the memory cell becomes about 8 V due to capacitive coupling with the control gate. In the memory cell into which data "1" is to be written, the channel is 8 V and the control gate is 20 V, so that electrons are not injected into the memory cell and the erase state ("1") is maintained. During the write operation, the signals SAN1, SAN2, PREB, BLCB are "H", and the signals SAP1, SAP2, VRFYBA1C,
RV1B, RV2B, ECH1, and ECH2 are at "L" level, and voltage VB is at 0V.

(2) Verify read of upper page After the write operation, it is detected whether or not the write has been performed sufficiently (write verify). If the desired threshold value has been reached, the data of the data circuit is changed to "1". If the threshold value has not been reached, the data of the data circuit is held and the write operation is performed again. The write operation and the write verify are repeated until all the memory cells to which "2" is written reach a desired threshold. At this time, the voltage Vpp applied to the control gate CG2A is increased stepwise according to the repetition of the write operation and the write verify here. Specifically, for example, as shown in FIG. 58A, the step-up width is set to 0.3 V, and the value of Vpp is increased from the initial value of 15 V in steps of 0.3 V. The write verify operation will be described with reference to FIGS. First, at time t1yc
The voltages VA and VB are 1.8 V and 1.5 V, respectively, and the bit lines BLa and BLb are 1.8 V and
1.5V. The signals BLCA and BLCB become "L", the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb become floating. Signal PRE
A and PREB become "L", and the MOS capacitor Qd
1. Nodes N1 and N2, which are gate electrodes of Qd2, are in a floating state. Subsequently, at time t2yc, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is 0.5V, the non-selected control gates CG1A, CG3A, CG4A and the selection gate S
G1A and SG2A are set to Vcc. If the threshold value of the selected memory cell is 0.5 V or less, the bit line voltage becomes 1.V.
It becomes lower than 5V. If the threshold value of the selected memory cell is 0.5 V or more, the bit line voltage remains at 1.8 V. At time t3yc, the signals BLCA and BLCB are set to "H", and the bit line potential is transferred to N1 and N2. After that, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit lines BLb and M
OS capacitor Qd2 is disconnected.

Thereafter, when VRFYBAC becomes "L" at time t4yc, in the data circuit holding the "1" write data, the p-channel MOS transistor Qp1
2C is "ON", and the node N1 becomes Vcc. As a result, the node N1 becomes Vcc when "1" is written. In the case of writing "2", the p-channel MOS transistor Qp12C is turned "OFF". That is, when "2" write is sufficiently performed, N1 becomes Vcc,
If "2" write is insufficient, N1 becomes 0V. Thereafter, the signals SAN1 and SAP1 become "L" and "H" respectively, the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized. Thereafter, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H", respectively.
When it becomes "L", the voltage of the node N1 is sensed and latched at time t5yc. As a result, only the data circuit holding the “2” write data detects whether the data of the corresponding memory cell is sufficiently in the “2” write state. If the data of the memory cell is "2", the write data is changed to "1" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data of the memory cell is not “2”, the write data is held at “2” by sensing and latching the voltage of the node N1 with the flip-flop FF1. The write data of the data circuit holding the “1” write data is not changed.

If all the selected memory cells have reached the desired threshold, the node N4C of the data circuit goes to "L". By detecting this, it is known whether or not all the selected memory cells have reached the desired threshold. For example, the write end detection transistor Qn5C may be used to detect the write end as shown in FIG.
After the verify read, VRTC is first precharged to, for example, Vcc. If there is at least one insufficiently written memory cell, the n-channel MOS transistor Qn5C turns "ON" because the node N4C of the data circuit is "H",
VRTC falls from the precharge potential. When all the memory cells are sufficiently written, the data circuits 3-0, 3-
All the nodes N4C of 1,..., 3-m-1, 3-m become “L”. As a result, n-channel MOS in all data circuits
Since the transistor Qn5C is turned "OFF", VRTC maintains the precharge potential, and the end of writing is detected.
Here, the threshold distribution of the “2” write data written in this manner is based on the voltage Vpp applied to the control gate CG2A.
Based on the step-up width of 0.3V,
It is kept in the range of 0.5V to 0.8V.

<Writing of lower page> (1) Reading of upper data and data loading Prior to writing of the lower page, data of the upper page is written in the memory cell, and as shown in FIG.
It is in the “1” state or the “2” state. The lower page data is externally input to the flip-flop FF1 via IOA and IOB, and at the same time, the upper page data stored in the memory cell is read and held in the flip-flop FF2. Reading of the data of the upper page written in the memory cell will be described with reference to FIGS.

First, at time t1yd, the voltages VA and VB become 1.8 V and 1.5 V, respectively, and the bit lines BLa and B
Lb becomes 1.8V and 1.5V, respectively. Signal BLC
A and BLCB become “L”, and the bit lines BLa and MO
The S capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are cut off, and the bit lines BLa and BLb float. The signals PREA and PREB become "L", and the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, enter a floating state.

Subsequently, at time t2yd, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is set to 0V and the non-selected control gate CG1 is set.
A, CG3A, CG4A and select gates SG1A, SG2
A is set to Vcc. If the threshold value of the selected memory cell is 0V or less, the bit line voltage will be lower than 1.5V.
If the threshold value of the selected memory cell is 0 V or more, the bit line voltage remains at 1.8 V. At time t3yd, the signals BLCA and BLCB are set to "H", and the bit line potential is transferred to N1 and N2. After that, the signals BLCA, BL
CB becomes "L", and the bit line BLa is separated from the MOS capacitor Qd1, and the bit line BLb is separated from the MOS capacitor Qd2. Thereafter, the signals SAN2 and SAP2 become "L" and "H", respectively, so that the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized. Thereafter, the signals RV2A and RV2B become "H". Again, when the signals SAN2 and SAP2 become "H" and "L", respectively, the node N1 at time t4yd
Are sensed and latched. The flip at this time
The nodes N5C and N6C of the flop FF2 are shown in FIG.
become. Here, as in the third embodiment, the data inversion operation of the read upper data is not performed, and the holding of the read data in the flip-flop FF1 ends at the time of sensing at time t4yd. The write data of the lower page input to the flip-flop FF1 from the outside is shown in FIG.
4 If the input data of the lower page is "H", writing is not performed, and the memory cell maintains the "1" or "2" state. On the other hand, if the input data of the lower page is "L", writing is performed, and the memory cell in the "1" state is set to the "3" state and the memory cell in the "2" state is set to "4".
Written to state.

To summarize the above, the flip-flop nodes N3C, N4C, N5 at the time of writing the lower page
The data of C and N6C are as shown in FIG.

(2) Lower page program writing operation is almost the same as that of FIG. However, FIG.
The difference is that at time t1pq, the voltage VA becomes the bit line write control voltage 1.4V and the bit line BLa becomes 1.4V.
It is a point that is. This will be described below with reference to FIG. n
If the voltage drop by the threshold value of the channel MOS transistor Qn39 becomes a problem, the signal BLCA may be boosted. Subsequently, the signal PREA changes to "L" to float the bit line. Next, at time t2pq, the signal V
RFYBA1C is set to Vcc. As a result, when data "1" or "3" is held, the n-channel MOS transistor Qn2C is turned "ON", so that the bit line control voltage 0V is applied to the bit line. VRFYBA1C may be set to Vcc or more as shown in FIG. Thereafter, at time t3pq, VRFYBAC becomes 0 V, and the bit line write control voltage Vcc is output to the bit line from the data circuit holding data "1" or data "2". As a result, the bit line for writing “1” or “2” is Vcc, and the bit line for writing “3” is 1.
The bit line for writing 4V and "4" becomes 0V.

At time t1pq, the control gate / selection gate drive circuit 2 selects the selection gate SG of the selected block.
1A, the control gates CG1A to CG4A become Vcc. The selection gate SG2A is at 0V. At time t4pq, the selected control gate CG2A is driven to high voltage Vpp (for example, initial value 1).
7.3V), non-select control gates CG1A, CG3A, C
G4A becomes VM (for example, 10 V). In a memory cell corresponding to a data circuit holding data “4”,
Due to the potential difference between the channel potential of 0 V and the potential Vpp of the control gate, electrons are injected into the floating gate, and the threshold increases.
In the memory cell corresponding to the data circuit holding data "3", electrons are injected into the floating gate due to the potential difference between the channel potential of 1.4 V and Vpp of the control gate, and the threshold value rises. The reason why the channel potential in the case of "3" write is set to 1.4 V is to make the injection amount of electrons smaller than in the case of "4" data write. In a memory cell corresponding to a data circuit in which data “1” or “2” is held, the channel potential and V
Since the potential difference of pp is small, electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During a write operation, signals SAN1, SAN2, P
REB and BLCB are “H”, and signals SAP1, SAP2,
VRFYBA1C, RV1A, RV1B, RV2B, E
CH1 and ECH2 are "L", and voltage VB is 0V.

(3) Verify read of lower page After the write operation, it is detected whether or not the write has been sufficiently performed (write verify). If the desired threshold value has been reached, the node N3 of the flip-flop FF1
Change C to "H". If the threshold has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and the write verify are repeated until all the memory cells to which "3" is to be written and the memory cells to which "4" are to be written have reached desired threshold values. At this time, according to the repetition of the write operation and the write verify here, the control gate CG2A
The applied voltage Vpp is gradually increased. In particular,
For example, as shown in FIG. 58B, the step-up width is set to 0.8 V, and the value of Vpp is changed from the initial value 17.3 V to 0.3 V.
Increase in 8V increments. The write verify operation will be described with reference to FIGS. First,
It is detected whether the memory cell to which "3" is to be written has reached a predetermined threshold value. First, at time t1ys, the voltages VA, V
B become 1.8 V and 1.5 V, respectively.
La and BLb become 1.8V and 1.5V, respectively. The signals BLCA and BLCB become “L”, and the bit line BL
a and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb become floating. The signals PREA and PREB become "L", and the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, enter a floating state. Subsequently, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is 1.4V, and the unselected control gates CG1A, CG3A, CG
4A and select gates SG1A and SG2A are set to Vcc.
If the threshold value of the selected memory cell is 1.4 V or less,
The bit line voltage will be lower than 1.4V. If the threshold value of the selected memory cell is 1.4 V or more, the bit line voltage remains at 1.8 V.

At time t2ys, signals BLCA and BLCB are set to "H", and the potential of the bit line is transferred to N1 and N2. After that, the signals BLCA and BLCB become "L", and the bit line BLa is separated from the MOS capacitor Qd1, and the bit line BLb is separated from the MOS capacitor Qd2. Thereafter, at time t3ys, VRFYBA1C becomes Vcc, and in the case of "2" write and "4" write, Qn2C is turned "ON" and the node N1 is discharged to 0V. Time t4y
When the signal VRFYBAC becomes "L" at s, in the data circuit holding "1" or "2" write data, the p-channel MOS transistor Qp12C is "ON" and the node N1 becomes Vcc. As a result, the node N1
Is Vcc for "1" write or "2" write.
In the case of “4” writing, the voltage becomes 0V.

The signals SAN1 and SAP1 become "L" and "H" respectively, the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized. Thereafter, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t5ys. As a result, only the data circuit holding the “3” write data detects whether the data of the corresponding memory cell is sufficiently in the “3” write state. If the data of the memory cell is "3", the write data is changed to "1" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data of the memory cell is not "3", the flip-flop FF1 senses and latches the voltage of the node N2, and the write data is held at "3". Thereafter, additional writing is performed. The write data of the data circuit holding the “1”, “2” or “4” write data is not changed. Next, the selected control gate is 2.8V
To be. The threshold value of the selected memory cell is 2.8V
Below, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 2.8 V or more, the bit line voltage remains at 1.8 V. PRE at time t6ys
A and PREB become Vcc, and nodes N1 and N2 become 1.8.
After V and 1.5V, it becomes floating. Thereafter, at time t7ys, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. Thereafter, the signals BLCA and BLCB become "L", and the bit line BLa and the MOS capacitor Qd1, and the bit lines BLb and M
OS capacitor Qd2 is disconnected.

At time t8ys, signal VRFYBAC goes low.
In the data circuit holding "1" or "2" write data and the data circuit holding "1" write data because "3" write is sufficiently performed, the p-channel MOS transistor Qp12C is "ON" and node N1 is at Vcc. Signal SAN
1 and SAP1 become "L" and "H" respectively, the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and is equalized. Thereafter, the signal RV1
A and RV1B become "H". Again, the signals SAN1, S
AP1 becomes “H” and “L”, respectively, so that at time t
The voltage of the node N1 is sensed and latched at 9ys. As a result, only the data circuit holding the “4” write data detects whether the data of the corresponding memory cell is sufficiently in the “4” write state. If the data of the memory cell is "4", the write data is changed to "2" by sensing and latching the voltage of the node N1 by the flip-flop FF1, and the write operation is not performed thereafter. If the data of the memory cell is not "4", the write data is held at "4" by sensing and latching the voltage of the node N1 by the flip-flop FF1, and additional writing is performed thereafter. The write data of the data circuit holding the “1”, “2” or “3” write data is not changed.

If all the selected memory cells have reached the desired threshold value, the node N4C of the data circuit goes to "L". By detecting this, it is known whether or not all the selected memory cells have reached the desired threshold. For example, the write end detection transistor Qn5C may be used to detect the write end as shown in FIG.
After the verify read, VRTC is first precharged to, for example, Vcc. If there is at least one insufficiently written memory cell, the n-channel MOS transistor Qn5C turns "ON" because the node N4C of the data circuit is "H",
VRTC falls from the precharge potential. When all the memory cells are sufficiently written, the data circuits 3-0, 3-
All the nodes N4C of 1,..., 3-m-1, 3-m become “L”. As a result, n-channel MOS in all data circuits
Since the transistor Qn5C is turned "OFF", VRTC maintains the precharge potential, and the end of writing is detected.

<Read Operation of Upper Page> In read of the upper page, "1" or "3" or "2" or "4" is read. According to FIGS. 65 and 66,
The read operation will be described. First, at time t1RD, the voltage V
A and VB become 1.8V and 1.5V, respectively, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. The signals BLCA and BLCB become "L", the bit line BLa and the MOS capacitor Qd1, and the bit lines BLb and M
The OS capacitor Qd2 is cut off and the bit lines BLa, B
Lb is floating. Signals PREA, PREB
Becomes "L", and the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, enter a floating state. Subsequently, the selected control gate CG2 of the block selected by the control gate / selection gate drive circuit 2
A is 1.1V, non-selection control gates CG1A, CG3A,
CG4A and select gates SG1A and SG2A are set to Vcc. If the threshold value of the selected memory cell is 1.1V or less, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 1 V or more, the bit line voltage remains at 1.8 V. Thereafter, at time t2RD, the signal BL
CA and BLCB become “H” and the data on the bit line becomes MO.
The data is transferred to the S capacitors Qd1 and Qd2. Then again
The signals BLCA and BLCB become “L” and the bit line B
La and MOS capacitor Qd1, bit line BLb and MOS
The capacitor Qd2 is disconnected. Signals SAN2 and SAP
2 become "L" and "H" respectively, the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized. Thereafter, the signals RV2A, RV2B
Becomes “H”. At time t3RD, the signals SAN2 and S
When AP2 becomes "H" and "L", the voltage of the node N1 is sensed and latched. Thus, "whether the data in the memory cell is" 1 "or" 2 "or" 3 "or" 4 "" is sensed by the flip-flop FF2, and the information is latched. The flip at this time
The nodes N5C and N6C of the flop FF2 are as shown in FIG.

Next, the selected control gate is set to 2.5V. If the threshold of the selected memory cell is less than 2.5V, the bit line voltage will be less than 1.5V. If the threshold value of the selected memory cell is 2.5 V or more, the bit line voltage remains at 1.8 V. Signal PR at time t4RD
EA and PREB become “H”, and the MOS capacitor Q
Nodes N1 and N2, which are gate electrodes of d1 and Qd2, are at 1.8V and 1.5V, respectively. Signals PREA, PREB
Becomes "L", and the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, enter a floating state. Thereafter, at time t5RD, the signals BLCA and BLCB are set to "H". Again, the signals BLCA and BLCB become "L", and the bit line BLa and the MOS capacitor Q
d1, the bit line BLb and the MOS capacitor Qd2 are disconnected. The signals SAN1 and SAP1 are “L”, respectively.
The signal becomes "H", the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized.
Thereafter, the signals RV1A and RV1B become "H". At time t6RD, the signals SAN1 and SAP1 become "H" and "L" respectively, whereby the voltage of the node N1 is sensed and latched. Thus, "whether the data of the memory cell is" 1 "," 2 "," 3 ", or" 4 "" is sensed by the flip-flop FF1, and the information is latched. The flip-flops FF1 and F at this time
The potentials of the nodes N3C and N5C of F2 are as shown in FIG.

Subsequently, reading is performed as shown in FIG. First, at time t7RD, the voltages VA and VB become 1.8 V and 1.5 V, respectively, and the bit lines BLa and BLb
Are 1.8V and 1.5V, respectively. The signal BLCA,
BLCB becomes "L", and the bit line BLa and the MOS capacitor Qd1 and the bit line BLb and the MOS capacitor Qd2
Are disconnected, and the bit lines BLa and BLb become floating. The signals PREA and PREB become “L”,
Nodes N1 and N2, which are gate electrodes of MOS capacitors Qd1 and Qd2, enter a floating state. Subsequently, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 has 0V, and the unselected control gates CG1A, CG3A, CG4A and the selection gate S
G1A and SG2A are set to Vcc. If the threshold value of the selected memory cell is 0 V or less, the bit line voltage is 1.5 V
Lower. The threshold value of the selected memory cell is 0 V
In this case, the bit line voltage remains at 1.8 V. Thereafter, at time t8RD, the signals BLCA and BLCB become "H", and the data on the bit line is transferred to the MOS capacitors Qd1 and Qd2. Thereafter, the signals BLCA and BLCB again become "L", and the bit line BLa and the MOS capacitor Q
d1, the bit line BLb and the MOS capacitor Qd2 are disconnected. Subsequently, at time t9RD, VRFYBA1C becomes "H".
become. At this time, the node N of the flip-flop FF2
As can be seen from FIG. 33, 5C is "H" when "3" or "4" is read. In this case, the n-channel MOS transistor Qn2C in FIG.
Alternatively, the node N1 for “4” read is grounded.

Subsequently, at time t10RD, VRFYBAC becomes "L". At this time, the node N3C of the flip-flop FF1 is at "H" and the node N4C is at "L" in the case of "4" reading as can be seen from FIG. in this case,
The p-channel MOS transistor Qp12C of FIG.
N ”and“ 4 ”read node N1 goes to Vcc, after which signals SAN1 and SAP1 become“ L ”,
The signal becomes "H", the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized.
Thereafter, the signals RV1A and RV1B become "H". At time t11RD, the signals SAN1 and SAP1 become "H" and "L", respectively, whereby the voltage of the node N1 is sensed and latched. Thus, the potentials of the nodes N3C and N4C are sensed by the flip-flop FF1,
That information is latched. At this time, the nodes N3C of the flip-flop FF1 and the flip-flop FF2,
N4C, N5C and N6C are as shown in FIG. The data of the upper page is the node N3 of the flip-flop FF1.
C and N4C (see FIG. 34). That is, in the “1” state and the “3” state, the node N3C becomes “L” and the N4C becomes “H”, and the “2” state and the “4” state.
In this state, the node N3C becomes "H" and the node N4C becomes "L". As described in <Writing of upper page>, the data of the upper page stores "1" or "3" or "2" or "4", and this write data is stored in the flip-flop FF1. Is read correctly. The data held in the flip-flop FF1 is output to the outside of the chip by activating CENB1.

<Read operation of lower page> In reading of lower page, "1" or "2" or "3" or "4" is read. The read operation will be described with reference to FIG. First, at time t1RD, the voltages VA, VB
Become 1.8V and 1.5V, respectively, and the bit line BL
a and BLb become 1.8V and 1.5V, respectively. The signals BLCA and BLCB become “L”, and the bit line BLa
, The MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are separated, and the bit lines BLa and BLb float. Signals PREA and PREB are "L"
As a result, the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, enter a floating state. Subsequently, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is 1.
1V, non-select control gates CG1A, CG3A, CG4A
And the selection gates SG1A and SG2A are set to Vcc. If the threshold value of the selected memory cell is 1.1V or less, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 1.1 V or more, the bit line voltage becomes 1.
It remains at 8V. Thereafter, at time t2RD, signal BLC
A, BLCB become "H" and the data on the bit line is MOS.
The data is transferred to the capacitors Qd1 and Qd2.

Thereafter, the signals BLCA and BLCB again become "L" and the bit line BLa and the MOS capacitor Q
d1, the bit line BLb and the MOS capacitor Qd2 are disconnected. The signals SAN2 and SAP2 are "L", respectively.
The signal becomes "H", the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized.
Thereafter, the signals RV2A and RV2B become "H". At time t3RD, the signals SAN2 and SAP2 become "H" and "L", respectively, whereby the voltage of the node N1 is sensed and latched. Thus, "whether the data in the memory cell is" 1 "or" 2 "or" 3 "or" 4 "" is sensed by the flip-flop FF2, and the information is latched. At this time, the nodes N5C and N6C of the flip-flop FF2 are as shown in FIG.

The data of the lower page has been read to the nodes N5C and N6C (see FIG. 32) of the flip-flop FF2. That is, in the “1” state and the “2” state, the node N5C becomes “L” and the N6C becomes “H”, and in the “3” state and the “4” state, the node N5C becomes “H” and the N6C becomes “L”. Become. As described in <Writing of lower page>, the data of the lower page stores "1" or "2", or "3" or "4", and this write data is stored in the flip-flop FF2. Is read correctly. The data held in the flip-flop FF2 is output to the outside of the chip by activating CENB2. As can be seen from the above description, the reading of the lower page is performed at the time t3RD of reading the upper page.
This is the operation up to. Therefore, for example, when reading the upper page following the lower page, the lower page may be read first, and then the upper page data may be read while the lower page data is being output to the outside of the chip. . That is, at time t3RD, the data of the lower page is latched by the flip-flop FF2 and output to the outside of the chip, and at the same time, <read of the upper page>
The operation after time t3RD in FIGS. 65 and 66 described in FIG. Thereby, the reading of the upper page can be apparently performed at high speed.

[Eighth Embodiment] The present embodiment is characterized in that the write operation of the lower page is started after the write operation of the upper page is completed in all the memory cells in the device. FIG. 67 shows a memory cell array in this embodiment. Here, it is assumed that the memory cell array is composed of quaternary cells and can store 2-bit information per memory cell. 4000 memory cells are arranged in the column direction and the row direction, respectively, and a total of 16M (16 × 10 ⁶ ) memory cells are integrated in a matrix. One memory cell has 2
Since bit information can be stored, the total capacity that can be stored in the memory cell array is 32 Mbits. The column address corresponds to each bit line. For example, the bit line BL1 corresponds to the column address C1, and the bit line BL2 corresponds to the column address C2. On the other hand, the row address is 1
Two addresses of an upper page and a lower page correspond to each word line. For example, the row address Q1U, Q1L corresponds to the word line WL1, and the row address Q2U, Q2L corresponds to the word line WL2. Note that U and L in the row address in FIG. 67 represent an upper page and a lower page, respectively.

FIG. 68 shows a conventional memory cell array composed of quaternary cells when the write page size is the same. Here, while the number of bits in one page to be simultaneously written is 4000 bits, two bits are simultaneously written into one memory cell without being divided into upper bits and lower bits.
00 memory cells are arranged. In other words, the number of bit lines is 2000. On the other hand, in order for the total capacity to be 32 Mbits like the memory cell shown in FIG.
8000 memory cells are arranged in the row direction. In such a memory cell array, two bits correspond to one bit line for a column address. For example, A1 and A2 are assigned to the bit line BL1, and A3 is assigned to the bit line BL2.
, A4 correspond. As for the row address, for example, R1 corresponds to the word line WL1, and R2 corresponds to the word line WL2. Next, writing to these memory cell arrays will be described. First, in this embodiment, an upper page write operation for writing upper bit data almost simultaneously into one page of memory cells is sequentially performed for each row address, and then the lower bit of the one page of memory cells is written into one page of the memory cells. A lower page write operation for writing data almost simultaneously is performed. That is, the first 4000 bits of data are stored in word line W corresponding to address Q1U in FIG.
Written to 4000 memory cells sharing L1,
The next 4000 bits of data are written to the 4000 memory cells sharing the word line WL2 corresponding to the address Q2U, and 4 bits are added to the memory cells sharing the word lines WL3 to WL4000 corresponding to the addresses Q3U to Q4000U.
000 bits of data are sequentially written.

On the other hand, in the memory cell array shown in FIG. 68, the first 4000 bits of data are written by writing 2-bit data to each of the 2000 memory cells sharing word line WL1. Therefore, when writing the first 4000 bits of data, an upper page write operation and a lower page write operation to 2,000 memory cells sharing the word line WL1 are performed. Further, for writing the next 4000 bits of data, 2 bits of data are written into each of the 2000 memory cells sharing the word line WL2.

Here, FIG. 69 shows that the "2" state is written to the memory cell in the erased "1" state during the upper page write operation, and the memory cell further becomes "4" in the lower page write operation. Assume that the state is written. In the present embodiment, when 16 Mbits of data corresponding to half of the total capacity of the memory cell array is written, the write operation of the upper page is completed in all the memory cells, and as shown in FIG. Then, all the memory cells are in the "2" state. On the other hand, when 16M bits of data are similarly written into the memory cell array shown in FIG. 68, half of all memory cells are in the "4" state and the other half are "1" as shown in FIG. State. Therefore, in FIG. 69 (a), since the "4" state where the threshold level is high and the data is likely to be destroyed due to the leakage of the accumulated charge in the floating gate is not written, the life of the memory cell is improved and the reliability is improved. The performance is improved. Further, when an electrically rewritable nonvolatile semiconductor memory device is actually used for a memory card or the like, the garbage coll.
In general, the storage area is not used, for example, about 70% of the entire area, and the remaining 30% is made an empty area from the viewpoint of performing the section (known example N. Niijima; I).
BM J. DEVELOP. VOL. 39 No. 5 pp.531-545 995).
FIG. 70 shows a case in which data of 70% of the total capacity of the memory cell array is written in this manner.

As shown in FIG. 70A, in this embodiment, the operation of writing the “2” state to the memory cell in the “1” state and writing the “4” state to the memory cell in the “2” state is entirely performed. At 70% of the capacity, 60% of the memory cells are in the "2" state and 40% of the memory cells are in the "4" state. On the other hand, when similar data is written to 70% of the total capacity of the memory cell array shown in FIG. 68, the "4" state is written to 70% of the memory cells as shown in FIG. The "1" state, which is the erased state, is held in the memory cell. Therefore, in the present embodiment, the number of memory cells to which the "4" state having a high threshold level is written is reduced to 4/7 as compared with the memory cell array shown in FIG. 68, and data destruction in the memory cells occurs. Probability decreases to about 57%. Further, here, the case where data is written in the order of word lines WL1, WL2, WL3 to WL4000 has been described, but the order of writing is not limited to this. For example, the order of writing may be controlled by a controller outside the chip such that memory cells in a chip of a semiconductor storage device such as a flash memory are uniformly set to the “4” state having a high threshold level. More specifically, the number of times the lower page write operation has been performed is stored for each page of 4000 memory cells in which one word line is shared and write is performed at substantially the same time. Determine the order of pages to be operated. In the present embodiment,
By making the number of times of writing of the memory cells belonging to each page uniform in this way, it is possible to suppress the progress of intensive deterioration in the memory cells of a specific page and improve the reliability. The area for storing the number of times of writing may be provided on the word line separately from the data area, for example. That is, a memory cell sharing one word line is, for example, 522 bytes, of which 512 bytes are a data area and 10 bytes are the number of times of writing or ECC.
(Error Correcting Code) may be used as the storage area.

[Ninth Embodiment] In the ninth embodiment, a storage system in which the semiconductor storage device of the present invention is used as a storage unit is configured. FIG. 71 is a diagram showing the configuration of the storage system of this embodiment. As shown, the controller 100 controls the operation of a plurality of chips 101 _q (q is a natural number).
The plurality of chips 101 _q is, for example, those having the same memory cell array, respectively Figure 67, where the controller 100 has four chip 101 _{1-101 4}
In the case of controlling the operation of FIG. In this embodiment,
The write operation of the lower page is started after the write operation of the upper page is completed in all the memory cells in all the devices constituting the storage section of the storage system.
Hereinafter, as in the eighth embodiment, the “2” state is written to the memory cell in the erased “1” state during the upper page write operation, and the memory cell further becomes “4” in the lower page write operation. The case where the state is written will be described. First, FIG. 72 is a diagram showing a state when writing is performed for half of the total capacity of the storage unit. As shown, the threshold levels of all the memory cells in all of the chips 101 _{1 to} 101 ₄ are in the “2” state.

FIG. 73 shows a state in which writing is performed for 70% of the total capacity of the storage unit. In this state, as described in the eighth embodiment, 60 out of all memory cells
% Of the memory cells are in the “2” state, and 40% of the memory cells are in the “4” state. In this embodiment, all the memory cells of the _first chip A101 ₁ and the second chip B101 _{2 are present.}
80% of the memory cells of the second chip B101 ₂ and the third chip C
101 ₃ and all the memory cells of the fourth chip D101 ₄ is "2" is written. Therefore, also in the present embodiment, the number of memory cells to which the "4" state having a high threshold level is written can be reduced, and the reliability is improved.
Here, the word line WL of the _first chip A101 ₁ is used.
1～WL4000, second chip B101 ₂ of the word line WL1～WL4000, third chip C101 ₃ of word lines WL1～WL4000, if the order of the fourth chip D101 ₄ word lines WL1～WL4000 writing data However, the order of writing is not limited to this. For example, the order of writing may be controlled by the controller 100 so that the memory cells in the chips 101 _{1 to} 101 ₄ are uniformly in the “4” state having a high threshold level. More specifically, as in the eighth embodiment, each page including 4000 memory cells sharing one word line and writing almost simultaneously is performed.
Stores the number of times a write operation of the lower page is performed, to the writing order based on the number of times may be determined in units of pages, the number of times a write operation of the lower page is performed on the chip 101 _1-101 per ₄ were stored, the writing order based on the number of times may be determined by the chip 101 _{1-101 4} units.

In the present embodiment, by making the number of times of writing of the memory cells belonging to each page or each of the chips 101 _{1 to} 101 ₄ uniform, the progress of intensive deterioration in the memory cells of a specific page or device can be prevented. Can be suppressed and reliability is improved. Here, the area for storing the number of times of writing may be provided on a word line separately from the data area, for example, as in the eighth embodiment, and a memory cell sharing one word line is, for example, 522 bytes. Of these, 512 bytes may be used as a data area and 10 bytes may be used as an area for storing the number of times of writing and ECC.

[0242]

As described above, according to the present invention, by devising a data write operation in a multi-value storage semiconductor memory device, the write circuit is simplified and the time required for writing is shortened as compared with the prior art. And reliability can be further improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing correspondence between memory cells and addresses in a first embodiment;

FIG. 2 is a diagram illustrating writing of an upper page according to the first embodiment;

FIG. 3 is a diagram for explaining a write operation according to the first embodiment;

FIG. 4 is a diagram illustrating writing of a lower page according to the first embodiment;

FIG. 5 is a diagram for explaining a read operation according to the first embodiment;

FIG. 6 is a view for explaining another write operation in the first embodiment;

FIG. 7 is a block diagram of a multilevel semiconductor memory device according to the first embodiment;

FIG. 8 is a view for explaining a write operation in the first embodiment;

FIG. 9 is a view for explaining a read operation in the first embodiment;

FIG. 10 is a diagram illustrating an example of a memory cell unit according to the first embodiment;

FIG. 11 shows another example of a memory cell unit.

FIG. 12 is a diagram showing another example of the memory cell unit;

FIG. 13 is a diagram showing another example of the memory cell unit;

FIG. 14 is a diagram illustrating a configuration of a memory cell array and a data circuit according to the first embodiment;

FIG. 15 is a diagram showing a threshold distribution of a memory cell according to the first embodiment;

FIG. 16 is a diagram illustrating a configuration of a data circuit according to the second embodiment;

FIG. 17 is a diagram illustrating a read operation according to the second embodiment;

FIG. 18 is a diagram showing a specific configuration of a data circuit according to the present invention.

FIG. 19 is a diagram illustrating write data of an upper page according to the second embodiment;

FIG. 20 is a diagram illustrating a write operation of an upper page according to the second embodiment;

FIG. 21 is a diagram showing a verify read operation of an upper page according to the second embodiment;

FIG. 22 shows a state before writing a lower page according to the second embodiment;
Diagram for reading upper page and data inversion

FIG. 23 shows a state before writing a lower page according to the second embodiment;
Diagram for reading upper page and data inversion

FIG. 24 is a diagram illustrating write data of a lower page according to the second embodiment;

FIG. 25 is a diagram showing a node of a data circuit at the time of writing a lower page according to the second embodiment;

FIG. 26 is a diagram illustrating a lower page write operation according to the second embodiment;

FIG. 27 is a diagram illustrating another data circuit according to the second embodiment;

FIG. 28 is a view for explaining another method of writing a lower page according to the second embodiment;

FIG. 29 is a view for explaining verify read of a lower page of the second embodiment;

FIG. 30 is a view for explaining a read operation of the second embodiment;

FIG. 31 is a view for explaining a read operation according to the second embodiment;

FIG. 32 is a diagram illustrating a node of a flip-flop FF2 during reading according to the second embodiment;

FIG. 33 is a diagram showing a node of a data circuit during reading according to the second embodiment;

FIG. 34 is a diagram showing read data according to the second embodiment;

FIG. 35 is a diagram showing nodes of a data circuit at the time of writing a lower page according to the third embodiment;

FIG. 36 is a diagram showing a lower page write operation according to the third embodiment;

FIG. 37 is a view showing a verify read operation of a lower page according to the third embodiment;

FIG. 38 is a diagram illustrating write data of an upper page according to the fourth embodiment;

FIG. 39 is a diagram showing a verify read of an upper page according to the fourth embodiment;

FIG. 40 is a diagram illustrating write data of a lower page according to the fourth embodiment;

FIG. 41 is a diagram showing a node of a data circuit at the time of writing a lower page according to the fourth embodiment;

FIG. 42 is a diagram illustrating writing of a lower page according to the fourth embodiment;

FIG. 43 is a diagram showing a verify read of a lower page according to the fourth embodiment;

FIG. 44 is a diagram showing another write operation of the lower page according to the fourth embodiment;

FIG. 45 is a view showing another verify read of a lower page of the fourth embodiment;

FIG. 46 is a view showing a quaternary cell write operation in the fifth embodiment;

FIG. 47 is a diagram showing a configuration of a data circuit of a quaternary cell according to the fifth embodiment;

FIG. 48 is a view showing a write operation of an 8-level cell in the fifth embodiment;

FIG. 49 is a diagram showing a configuration of a data circuit of a quaternary cell according to the fifth embodiment;

FIG. 50 is a view showing a 16-level cell write operation in the fifth embodiment;

FIG. 51 is a diagram showing a configuration of a data circuit of 16-level cells in the fifth embodiment;

FIG. 52 is a view showing a write operation of a 2 m value cell in the fifth embodiment;

FIG. 53 is a diagram showing a configuration of a data circuit of 2 m value cells in the fifth embodiment;

FIG. 54 is a view showing a write operation procedure in the sixth embodiment;

FIG. 55 is a diagram showing a comparison with the threshold distribution of a memory cell according to the sixth embodiment;

FIG. 56 is a view showing a comparison with a waveform of a pulse supplied to a memory cell in the sixth embodiment;

FIG. 57 is a view showing a threshold distribution of a memory cell according to the sixth embodiment;

FIG. 58 is a view showing a waveform of a pulse supplied to a memory cell in the sixth embodiment;

FIG. 59 is a view showing a waveform of a pulse supplied to a memory cell in the sixth embodiment;

FIG. 60 is a view showing a threshold voltage distribution of a memory cell according to the sixth embodiment;

FIG. 61 is a view showing a threshold voltage distribution of a memory cell in a sixth embodiment;

FIG. 62 is a view showing a threshold distribution of a memory cell according to the sixth embodiment;

FIG. 63 is a view showing a threshold voltage distribution of a memory cell according to a seventh embodiment;

FIG. 64 is a view for explaining verify read of a lower page of the seventh embodiment;

FIG. 65 is a view for explaining a read operation of the seventh embodiment;

FIG. 66 is a view for explaining a read operation of the seventh embodiment;

FIG. 67 is a view showing a memory cell array according to the eighth embodiment;

FIG. 68 is a diagram showing a conventional memory cell array including four-valued cells;

FIG. 69 is a diagram showing a state in which the “2” state and the “4” state are written to the memory cell in the “1” state

FIG. 70 is a diagram showing a case where 70% of the total capacity of a memory cell array is written;

FIG. 71 is a view showing the configuration of a storage system according to a ninth embodiment;

FIG. 72 is a diagram illustrating a state in which writing is performed only for half of the total capacity of the storage unit according to the ninth embodiment;

FIG. 73 illustrates the total capacity of the storage unit according to the ninth embodiment.
The figure which shows the state at the time of performing writing for 0%.

74A is a plan view showing one NAND cell in a NAND type EEPROM, and FIG. 74B is a circuit diagram;

75 (a) is a sectional view taken along line AA ′ of the NAND cell shown in FIG. 71 (a), and FIG. 75 (b) is a sectional view taken along line BB ′ of FIG.

FIG. 76 is a circuit diagram showing a memory cell array of NAND cells

FIG. 77 is a diagram showing a relationship between threshold voltage and quaternary data of a conventional memory cell.

FIG. 78 illustrates a conventional write operation of a memory cell.

FIG. 79 is a diagram showing correspondence between conventional memory cells and addresses.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Control gate / selection gate drive circuit 3 ... Data circuit 4 ... Data input / output buffer 5 ... Address buffer 6 ... Data control circuit 100 ... Controller 101 _q ... Chip M ... Memory cell S ... Select transistor SG ... Select Gate CG: Control gate BL: Bit line Qn: n-channel MOS transistor Qp: p-channel MOS transistor Qd: depletion type n-channel MOS transistor FF: flip-flop I: inverter G: NAND logic circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-18018 (JP, A) JP-A-62-6493 (JP, A) JP-A-8-315586 (JP, A) JP-A-7- 93979 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (91)

(57) [Claims] The "1" state has a first threshold level, the "2" state has a second threshold level, and the "3" state has a first threshold level.
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) stores an n value having the i-th threshold level. , "M-1", "1" state, "2" state,...
State or “m” state (m is a natural number of 2 or more), the memory cell is set to “1” based on write data input from outside the memory cell and data held by the memory cell. State, "2" state, ..., "k-
A semiconductor memory device in one of a 1 "state and a" k "state (k is a natural number larger than m). 2. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) stores an n value having the i-th threshold level. A memory cell to be supplied; writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels; and each time a bias is supplied to the memory cell for a predetermined time,
Verifying means for detecting whether the threshold value of the memory cell has shifted between desired threshold levels, and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts; A semiconductor memory device in which a bias value increases stepwise in accordance with the number of repetitions when the supply of bias to the memory cell by the writing means is repeated. In some cases, based on write data input from outside the memory cell, the memory cell is set to a “1” state, a “2” state,
.., A first write mode for setting the threshold level to one of the “m−1” state and the “m” state (m is a natural number of 2 or more), and the “1” state and the “2” state of the memory cell , ..., "m-1"
When the memory cell is at one of the threshold levels of the state and the "m" state, the memory cell is set to the state of "1" and " 2 "state, ...," k-1 "state,
A second write mode for setting any threshold level in a “k” state (k is a natural number greater than m), wherein the increase in the bias value in the first write mode is ΔVpp1, 2, when the increasing width of the bias value in the write mode 2 is ΔVpp2,
A semiconductor memory device satisfying a relationship of pp1 <ΔVpp2. 3. The "1" state is an erased state, and the threshold distribution width of the "2" state, "3" state,..., "M-1" state, "m" state is "m + 1" state, "M + 2" state, ...,
3. The semiconductor memory device according to claim 1, wherein a threshold distribution width of the "k-1" state and the "k" state is narrower. 4. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. , "2" state,..., "2 ^m-1-
When holding either the 1 ”state or the“ 2 ^m−1 ”state (m is a natural number that satisfies n = 2 ^m ), based on the write data input from outside the memory cell and the data held by the memory cell. , The memory cell is set to one of a “1” state, a “2” state,..., A “2 ^m −1” state, and a “2 ^m ” state. 5. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. A memory cell to be supplied; writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels; and each time a bias is supplied to the memory cell for a predetermined time,
Verifying means for detecting whether the threshold value of the memory cell has shifted between desired threshold levels, and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts; A semiconductor memory device in which a bias value increases stepwise in accordance with the number of repetitions when the supply of bias to the memory cell by the writing means is repeated. In some cases, based on write data input from outside the memory cell, a first write mode for setting the memory cell to a threshold level of either a “1” state or a “2” state; "1" state, "2" state, ..., "2 ^m-1-
When the threshold level is one of the 1 ”state and the“ 2 ^m−1 ”state (m is a natural number satisfying n = 2 ^m ), the write data input from outside the memory cell and the threshold of the memory cell An m-th write mode for setting the memory cell to any one of the threshold levels of “1” state, “2” state,..., “2m−1” state, and “2m” state based on the value level When the increasing width of the bias value in the first write mode is ΔVpp1 and the increasing width of the bias value in the m-th write mode is ΔVppm,
A semiconductor memory device satisfying a relationship of pp1 <ΔVppm. 6. The threshold distribution width of the “2” state is “2 ^m−1 +
1 "state," 2 ^m-1 +2 "state, ...," 2 ^m-1 "state,
6. The semiconductor memory device according to claim 5, wherein the width of the threshold distribution in the "2 ^m " state is narrower. 7. The threshold distribution width of the "1" state is an erased state, and the "2" state, "3" state,..., "2 ^m-1 -1" state, and "2 ^m-1 " state. Is "2 ^m-1 +1" state, "2 ^m-1 +
6. The semiconductor memory device according to claim 4, wherein the threshold value distribution width of each of the "2" state,..., "2 ^m-1 " state, and "2 ^m " state is narrower. 8. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. In a semiconductor memory device having a memory cell, when the memory cell holds the “1” state or the “2” state, based on write data inputted from outside the memory cell and data held by the memory cell, A semiconductor memory device wherein a memory cell is set to a "1" state, a "2" state, a "3" state, or a "4" state. 9. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) stores an n value having the i-th threshold level. A memory cell to be supplied; writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels; and each time a bias is supplied to the memory cell for a predetermined time,
Verifying means for detecting whether the threshold value of the memory cell has shifted between desired threshold levels, and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts; A semiconductor memory device in which a bias value increases stepwise in accordance with the number of repetitions when the supply of bias to the memory cell by the writing means is repeated. In some cases, based on write data input from outside the memory cell, a first write mode for setting the memory cell to a threshold level of either a “1” state or a “2” state; When the threshold level is in the “1” state or the “2” state, the write data input from outside the memory cell and the threshold level of the memory cell are changed. A second write mode for setting the memory cell to any one of a threshold level of a “1” state, a “2” state, a “3” state, or a “4” state based on the When the increase width of the bias value in the first write mode is ΔVpp1 and the increase width of the bias value in the second write mode is ΔVpp2,
A semiconductor memory device satisfying a relationship of pp1 <ΔVpp2. 10. A state wherein the "1" state is an erased state, and the threshold distribution width of the "2" state is narrower than the threshold distribution widths of the "3" state and the "4" state. 10. The semiconductor memory device according to claim 8 or 9. 11. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. , "R-1", "1" state, "2" state,...
State or “r” state (r is a natural number of 2 or more), the memory cell is set to “1” based on write data input from outside the memory cell and data held by the memory cell. State, "2" state, ..., "s-
1 "state or" s "state (s is a natural number greater than r), and the memory cell is in" 1 "state," 2 "state,...," S-1 "
State or the "s" state, the memory cell is set to the "1" state, the "2" state,... Based on the write data input from outside the memory cell and the data held by the memory cell. , “T−1” state, “t” state (t
Is a natural number greater than s). 12. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. A memory cell to be supplied; writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels; and each time a bias is supplied to the memory cell for a predetermined time,
Verifying means for detecting whether the threshold value of the memory cell has shifted between desired threshold levels, and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts; A semiconductor memory device in which the bias value increases stepwise according to the number of repetitions when the supply of bias to the memory cell by the writing unit is repeated, wherein the memory cell is in a “1” state, a “2” state, …, “R-1”
The threshold value of the memory cell based on the write data input from outside the memory cell and the threshold level of the memory cell when the threshold level is any of the state and the “r” state (r is a natural number of 2 or more). When the cell is in the “1” state, the “2” state,
, A j-th (j is 2) state which is a threshold level of one of the "s-1" state and the "s" state (s is a natural number larger than r)
(The above natural number) and the memory cells are in the “1” state, the “2” state,.
When the memory cell is at one of the threshold levels of the "1" state and the "s" state, the memory cell is set to the "1" state, 2 "state, ...," t-1 "state,
A (j + 1) -th write mode for setting any threshold level in a “t” state (t is a natural number larger than s), and an increase width of the bias value in the j-th write mode is ΔVppj. A semiconductor memory device which satisfies the relationship of ΔVppj <ΔVpp (j + 1), where ΔVpp (j + 1) is the increase width of the bias value in the write mode of j + 1. 13. An "r + 1" state, an "r + 2" state,.
The threshold distribution width of the “s−1” state and the “s” state is “s +
1 "state," s + 2 "state, ...," t-1 "state,
13. The semiconductor memory device according to claim 11, wherein the width is smaller than a threshold distribution width in the "t" state. 14. The "1" state is an erase state, and the threshold distribution width of the "2" state, "3" state,..., "R-1" state, "r" state is "r + 1" state, "R + 2" state, ...,
14. The semiconductor memory device according to claim 11, wherein the threshold value distribution width of the "s-1" state and the "s" state is narrower. 15. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. In a semiconductor memory device having a memory cell that changes, the memory cell is in a “1” state, a “2” state,..., “2 ^k−1 −
When holding either the 1 "state or the" 2 ^k-1 "state (k is a natural number of 2 or more), the memory is controlled based on write data input from outside the memory cell and data held by the memory cell. When the cell is in a “1” state, a “2” state,.
One of the “2 ^k−1 ” state and the “2 ^k ” state, and the memory cell is in the “1” state, the “2” state,..., “2 ^k −
When holding either the “1” state or the “2 ^k ” state,
Based on the write data input from outside the memory cell and the data held by the memory cell, the memory cell is set in a “1” state, a “2” state,..., A “2 ^{k + 1} −1” state,
A semiconductor memory device in ^{one of the} “2 ^{k + 1} ” states. 16. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. A memory cell to be supplied; writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels; and each time a bias is supplied to the memory cell for a predetermined time,
Verifying means for detecting whether the threshold value of the memory cell has shifted between desired threshold levels, and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts; A semiconductor memory device in which the bias value increases stepwise according to the number of repetitions when the supply of bias to the memory cell by the writing unit is repeated, wherein the memory cell is in a “1” state, a “2” state, …, “2 ^k-1 −
When the threshold level is any of the 1 ”state and the“ 2 ^k−1 ”state (k is a natural number of 2 or more), the write data input from outside the memory cell and the threshold level of the memory cell The memory cell is set to a “1” state based on
A k-th write mode for setting any one of the threshold levels of the “2” state,..., “2 ^k −1” state, and “2 ^k ” state; …, “2 ^k −
When the threshold level is any of the "1" state and the "2 ^k " state, the memory cell is set to "1" based on the write data inputted from outside the memory cell and the threshold level of the memory cell. State, "2" state, ..., "2 ^{k + 1-}
A (k + 1) -th write mode for setting any one of a threshold level of a “1” state and a “2 ^{k + 1} ” state, wherein the increase in the bias value in the k-th write mode is ΔVppk and the (k + 1) -th mode. A semiconductor memory device that satisfies the relationship of ΔVppk <ΔVpp (k + 1), where ΔVpp (k + 1) is the increase width of the bias value in the write mode. 17. The threshold distribution width of the “2 ^{k −1} +1” state, “2 ^k−1 +2” state,..., “2 ^k −1” state, “2 ^k ” state is “2 ^k +1”. State, “2 ^k +2” state,..., “2 ^{k + 1}
17. The semiconductor memory device according to claim 15, wherein the threshold value distribution width in the "-1" state and the "2 ^{k + 1} " state is narrower. 18. The "1" state is an erased state, and the threshold distribution widths of the "2" state, "3" state,..., "2 ^k-1 -1" state, and "2 ^k-1 " state Is "2 ^k-1 +1" state, "2 ^k-1 +
18. The semiconductor memory according to claim 15, wherein a threshold distribution width of each of the "2" state,..., "2 ^k -1" state, and "2 ^k " state is narrower. apparatus. 19. The "1" state is an erased state, and the threshold distribution width of the "2" state is "3" state, "4" state,.
19. The semiconductor memory device according to claim 15, wherein a threshold distribution width of the "2 ^k-1 -1" state and the threshold distribution width of the "2 ^k-1 " state are narrower. 20. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) stores an n value having the i-th threshold level. In a semiconductor memory device provided with a memory cell, a memory cell becomes "1" when a first logic level is inputted and becomes "2" when a second logic level is inputted in a first write operation. The memory cell which is in the “A” state as a result of the k−1th (k is a natural number of 2 or more) write operation enters the “A” state when the 2k−1th logic level is input during the kth write operation. , When the 2kth logic level is input, "A + 2 ^k-1 "
A semiconductor memory device which is in a state. 21. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) stores an n value having the i-th threshold level. A memory cell to be supplied; writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels; and each time a bias is supplied to the memory cell for a predetermined time,
Verifying means for detecting whether the threshold value of the memory cell has shifted between desired threshold levels, and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts; A semiconductor memory device in which the bias value is increased stepwise according to the number of repetitions when the supply of the bias to the memory cell by the writing means is repeated. When a logical level is input, the state becomes "1". When a second logical level is input, the state becomes "2". As a result of the k-1 (k is a natural number of 2 or more) write operation, the state is "A". At the time of the k-th write operation, the memory cell enters the “A” state when the 2k−1 logical level is input, and “A + 2 ^k−1 ” when the 2k logical level is input.
And the increase in the bias value in the first write mode in which the first write operation is performed is ΔVpp1, and the increase in the bias value in the k-th write mode in which the k-th write operation is performed is ΔVppk. When
A semiconductor memory device satisfying a relationship of ΔVpp1 <ΔVppk. 22. The semiconductor memory device according to claim 20, wherein the "1" state is an erased state, and the threshold distribution width of the "2" state is smaller than the threshold distribution width of the "A + 2 ^k-1 " state. 22. The semiconductor memory device according to claim 21. 23. The threshold distribution width of the "A" state is "A + 2".
22. The semiconductor memory device according to claim 20, wherein the threshold value distribution width is smaller than the threshold value distribution width in the " ^k-1 " state. 24. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. In a semiconductor memory device provided with a memory cell, a memory cell becomes "1" when a first logic level is inputted and becomes "2" when a second logic level is inputted in a first write operation. In the second write operation, the memory cell that is in the “1” state as a result of the first write operation is set to the “1” state when the third logical level is input, and is set to “3” when the fourth logical level is input. In the second write operation, the memory cell which is in the state “2” as a result of the first write operation becomes the state “2” when the third logical level is inputted, and becomes the state “2” when the fourth logical level is inputted. It is characterized by being in the “4” state That the semiconductor memory device. 25. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. A memory cell to be supplied; writing means for supplying a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels; and each time a bias is supplied to the memory cell for a predetermined time,
Verifying means for detecting whether the threshold value of the memory cell has shifted between desired threshold levels, and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts; A semiconductor memory device in which the bias value is increased stepwise according to the number of repetitions when the supply of the bias to the memory cell by the writing means is repeated. When a logic level is input, the memory cell enters a “1” state. When a second logic level is input, the memory cell enters a “2” state. As a result of the first write operation, a memory cell in the “1” state performs a second write operation. When the third logic level is input, the state becomes "1". When the fourth logic level is input, the state becomes "3". As a result of the first write operation, the state is "2". In the second write operation, the memory cell becomes the "2" state when the third logical level is inputted, and becomes the "4" state when the fourth logical level is inputted, and performs the first write operation. When the increase width of the bias value in the first write mode is ΔVpp1, and the increase width of the bias value in the second write mode for performing the second write operation is ΔVpp2,
A semiconductor memory device satisfying a relationship of Vpp1 <ΔVpp2. 26. The semiconductor memory device according to claim 26, wherein the "1" state is an erased state, and the threshold distribution width of the "2" state is smaller than the threshold distribution widths of the "3" state and the "4" state. 26. The semiconductor memory device according to claim 24 or claim 25. 27. The semiconductor memory device according to claim 24, wherein said third threshold level is higher than said second threshold level. 28. A threshold voltage distribution between the "3" state threshold distribution and the "4" state threshold distribution, wherein the "2" state threshold distribution and the "3" state threshold distribution 28. The semiconductor memory device according to claim 27, wherein the voltage difference is equal to the voltage difference between the two. 29. A voltage difference between the threshold distribution in the “3” state and the threshold distribution in the “4” state is represented by a threshold distribution in the “2” state and a threshold distribution in the “3” state. 28. The semiconductor memory device according to claim 27, wherein the voltage difference is larger than the voltage difference between the two. 30. The semiconductor memory device according to claim 24, wherein said third threshold level is smaller than said second threshold level. 31. A voltage difference between a threshold distribution in a “2” state and a threshold distribution in a “4” state is represented by a threshold distribution in a “3” state and a threshold distribution in a “2” state. 31. The semiconductor memory device according to claim 30, wherein the voltage difference is equal to the voltage difference between the two. 32. A voltage difference between a threshold distribution in a "2" state and a threshold distribution in a "4" state is represented by a threshold distribution in a "3" state and a threshold distribution in a "2" state. 31. The semiconductor memory device according to claim 30, wherein the voltage difference is larger than the voltage difference between. 33. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. In a semiconductor memory device provided with a memory cell, a memory cell becomes "1" when a first logic level is inputted and becomes "2" when a second logic level is inputted in a first write operation. When a third logic level is input at the time of the second write operation, the memory cell that is in the “1” state as a result of the first write operation changes the “1” data held in the memory cell to the third logic level. When a fourth logic level is input based on the first logic level and the fourth logic level, the status changes to a "3" state based on the "1" data held in the memory cell and the fourth logic level. The memory cell in the “2” state is In the write operation of No. 2, when the third logical level is input, the state becomes "2" based on the "2" data held in the memory cell and the third logical level, and when the fourth logical level is input, the memory becomes A semiconductor memory device, which enters a "4" state based on "2" data held in a cell and a fourth logic level. 34. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. In a semiconductor memory device including a memory cell to be written, and a data circuit that holds write data of the memory cell, the memory cell performs a write operation according to the first write data held in the data circuit during a first write operation. When the data is at the first logic level, the state is "1". When the write data is at the second logic level, the state is "2". Then, the data circuit is inputted from outside the memory cell. After holding the second write data and the data read from the memory cell, if the memory cell is in the "1" state and the second write data is at the third logical level, the data When the data circuit holds the memory cell, the memory cell is in the "1" state, and when the data circuit holds that the memory cell is in the "1" state and the second write data is at the fourth logic level, The memory cell is in the "3" state, and when the data circuit holds that the memory cell is in the "2" state and the second write data is at the third logic level, the memory cell is in the "2" state. State, and when the data circuit holds that the memory cell is in the “2” state and the second write data is at the fourth logical level, the memory cell is in the “4” state. Semiconductor storage device. 35. The semiconductor device according to claim 24, wherein the first logic level and the third logic level are equal, and the second logic level and the fourth logic level are equal. The semiconductor memory device according to claim 1. 36. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) stores an n value having the i-th threshold level. A memory cell including a memory cell to be written and a data circuit for holding write data of the memory cell, wherein the memory cell is in a “1” state, a “2” state,..., “M−1”
When the data circuit holds the state “m” (m is a natural number of 2 or more), the data circuit holds the write data input from outside the memory cell and the data read from the memory cell, Based on the data held in the circuit, the memory cell is set in a “1” state, a “2” state,.
A semiconductor memory device, which is set in a "k-1" state or a "k" state (k is a natural number larger than m). 37. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) stores an n value having the i-th threshold level. A memory cell to be written; a data circuit that holds write data of the memory cell; a writing unit that supplies a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels; Each time a bias is applied to the cell for a predetermined time,
Verifying means for detecting whether the threshold value of the memory cell has shifted between desired threshold levels, and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts; A semiconductor memory device in which a bias value increases stepwise in accordance with the number of repetitions when the supply of bias to the memory cell by the writing means is repeated. In some cases, after the data circuit holds the write data input from outside the memory cell, the memory cell is set in the “1” state, “2” state,..., “M” based on the data held in the data circuit. A first write mode in which the threshold level is set to one of the -1 "state and the" m "state (m is a natural number of 2 or more); "State, ...," m-1 "
The data circuit holds the write data input from outside the memory cell and the data read from the memory cell when the data circuit is at one of the threshold level of the state and the “m” state. , "2" state,...,
A second write mode in which one of a threshold level of a “k−1” state and a “k” state (k is a natural number larger than m) is provided, and the bias value of the first write mode is When the increase width is ΔVpp1 and the increase width of the bias value in the second write mode is ΔVpp2, ΔVpp1
A semiconductor memory device satisfying a relationship of pp1 <ΔVpp2. 38. The "1" state is an erase state, and the threshold distribution width of the "2" state, "3" state,..., "M-1" state, "m" state is "m + 1" state, "M + 2" state, ...,
38. The semiconductor memory device according to claim 36, wherein the threshold distribution width in the "k-1" state and the "k" state is narrower. 39. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. In a semiconductor memory device including a memory cell to be written and a data circuit that holds write data of the memory cell, when the memory cell holds the “1” state or the “2” state, the data circuit After holding the write data input from the memory cell and the data read from the memory cell, the memory cell is set to the “1” state, the “2” state, the “3” state based on the data held in the data circuit.
A semiconductor memory device in a state or a “4” state. 40. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) stores an n value having the i-th threshold level. A memory cell to be written; a data circuit that holds write data of the memory cell; a writing unit that supplies a bias to the memory cell to shift a threshold value of the memory cell between desired threshold levels; Each time a bias is applied to the cell for a predetermined time,
Verifying means for detecting whether the threshold value of the memory cell has shifted between desired threshold levels, and repeating the supply of bias to the memory cell by the writing means until the threshold value shifts; A semiconductor memory device in which a bias value increases stepwise in accordance with the number of repetitions when the supply of bias to the memory cell by the writing means is repeated. In some cases, after the data circuit holds the write data input from outside the memory cell, the memory cell is switched to either the “1” state or the “2” state based on the data held in the data circuit. A first write mode in which the threshold level is set, and a data write mode in which the memory cell is at a threshold level of either the “1” state or the “2” state. After the data circuit holds the write data input from outside the memory cell and the data read from the memory cell, the memory cell sets the memory cell to “1” state, “2” based on the data held in the data circuit. A second write mode in which the threshold level is set to any one of a "state", a "3" state, and a "4" state, wherein the increase in the bias value in the first write mode is ΔVpp1, 2, when the increasing width of the bias value in the write mode 2 is ΔVpp2,
A semiconductor memory device satisfying a relationship of pp1 <ΔVpp2. 41. A state wherein the "1" state is an erased state, and the threshold distribution width of the "2" state is narrower than the threshold distribution widths of the "3" state and the "4" state. 41. The semiconductor memory device according to claim 39 or 40. 42. The semiconductor memory device according to claim 1, wherein the memory cells share a word line to form a memory cell array. 43. A semiconductor memory device comprising: a memory cell capable of storing a plurality of bits of data; and a data circuit for holding write data of the memory cell, wherein the plurality of bits of data are first stored in a memory cell. When data to be written is upper bit data and data to be written to the memory cell later is lower bit data, the first write data is input to the data circuit from outside the memory cell and temporarily stored. An upper bit data write operation is performed, and after the upper bit data write operation is completed, the second write data is input to the data circuit from outside the memory cell and temporarily stored, and then the lower circuit is written. A semiconductor memory device in which a bit data write operation is performed. 44. The write operation of the lower bit data, wherein the data circuit holds second write data inputted from outside the memory cell and data of the upper bit read from the memory cell. 44. The semiconductor memory device according to claim 43, which is performed later. 45. A memory cell capable of storing a plurality of bits of data, and a data circuit for holding write data of the memory cell, wherein a memory cell group including a plurality of predetermined memory cells is a write unit. In a semiconductor memory device for forming a page, a memory for forming the page, wherein data to be written to a memory cell first is data of an upper bit, and data to be written to a memory cell later is data of a lower bit. In writing the plurality of bits of data to each of the cells, the operation of writing the upper bits of data is referred to as an upper page write operation.
When the operation of writing the data of the lower bits is a write operation of the lower page, the write operation of the lower page is started after the write operation of the upper page is completed for each memory cell group forming the page. A semiconductor memory device characterized by the following. 46. A write operation of the upper page is performed after first write data is inputted to the data circuit from outside the memory cell and temporarily stored therein, and then the data circuit is supplied to the data circuit from outside the memory cell. 5. The write operation of the lower page is performed after the second write data is input and temporarily stored.
6. The semiconductor memory device according to 5. 47. The semiconductor memory device according to claim 45, wherein a plurality of said data circuits are provided corresponding to a memory cell group comprising a plurality of memory cells. 48. A memory cell capable of storing a plurality of bits of data, a data circuit holding write data of the memory cell, and a write operation to the memory cell in accordance with the write data held in the data circuit Writing means for performing the following operations: detecting whether or not write data held in the data circuit has been written to the memory cell, and detecting whether the desired writing has been performed; Verifying means for repeating the write operation to the memory cell, wherein the data of the plurality of bits which is first written to the memory cell is the data of the upper bit, and the data which is written to the memory cell later is the data of the lower bit. When the data is used, the data of the upper bits is determined by the writing unit. A semiconductor memory device, wherein a write operation to a memory cell is performed, and after the verify means detects that a desired write has been performed, a write operation to the memory cell by the write means is performed on the lower-order bit data. Storage device. 49. The write operation of data of the lower bits is such that, after the data of the upper bits are written, the data circuit reads write data inputted from outside the memory cell and read data from the memory cell. 49. The semiconductor memory device according to claim 48, wherein the operation is performed after holding the upper bit data. 50. A memory cell capable of storing a plurality of bits of data, a data circuit holding write data of the memory cell, and a write operation to the memory cell according to the write data held in the data circuit. Writing means for performing the following operations: detecting whether or not write data held in the data circuit has been written to the memory cell, and detecting whether the desired writing has been performed; Verifying means for repeating a write operation to a memory cell group, wherein a memory cell group consisting of a predetermined plurality of memory cells forms a page as a write unit, wherein the memory cell The data written to the memory cell is the upper bit data, and the data written to the memory cell later is the lower bit. A bit of data, per the write data of the plurality of bits for each memory cell group to form said pages, the write operation of the upper page operation for writing data of the upper bits,
When the operation of writing the data of the lower bits is a write operation of a lower page, a write operation of an upper page is performed by the write unit for each of the memory cell groups forming the page, and all of the memory cell groups are written. A write operation of a lower page is performed by the write unit after the verify unit detects that desired write has been performed in the memory cell. 51. In the lower page write operation, after the upper page write operation, the data circuit holds write data input from outside the memory cell and data read from the memory cell. 51. The semiconductor memory device according to claim 50, which is performed later. 52. The semiconductor memory device according to claim 50, wherein a plurality of said data circuits are provided corresponding to a memory cell group including a plurality of memory cells. 53. A semiconductor memory device in which a memory cell group consisting of a predetermined plurality of memory cells forms a page serving as a write unit, wherein the memory cell is capable of storing a plurality of bits of data.
Value (n is a natural number of 3 or more) storage memory cell, and a p-th (p is a natural number of 1 or more) write operation and p +
When by one write operation of the plurality of bits of data writing into the memory cell, the first based on the first write data to the first bit of said plurality of bits of the first memory cells belonging to the first page p write operation, and the plurality of second memory cells belonging to the second page
After performing the p-th write operation on the first bit of the bits based on the second write data, the third bit is set on the second bit of the plurality of bits of the first memory cell.
And a p + 1-th write operation based on the write data. 54. A memory cell capable of storing a plurality of bits of data, a data circuit holding write data of the memory cell, and a write operation to the memory cell in accordance with the write data held in the data circuit Writing means for performing the following operations: detecting whether or not write data held in the data circuit has been written to the memory cell, and detecting whether the desired writing has been performed; A verifying means for repeating a write operation to the memory cell, wherein a memory cell group including a plurality of predetermined memory cells forms a page serving as a write unit, wherein a p-th (p is a natural number of 1 or more) Write operation and p +
When by one write operation of the plurality of bits of data writing into the memory cell, the first based on the first write data to the first bit of said plurality of bits of the first memory cells belonging to the first page p write operation, and the plurality of second memory cells belonging to the second page
After performing the p-th write operation on the first bit of the bits based on the second write data, the third bit is set on the second bit of the plurality of bits of the first memory cell.
And a p + 1-th write operation based on the write data. 55. The plurality of bits of the first memory cell
Of the plurality of bits of the second memory cell following the (p + 1) th write operation to the second bit of the second memory cell.
The p based on the fourth write data to the second bit Chino
The write operation of +1 is performed.
The semiconductor memory device according to claim 3 or 54. 56. A result of the p write operation to the first bit of the first memory cell, a first first memory cell
After the verifying means detects that desired writing has been performed on the first bit , a p-th writing operation to the first bit of the second memory cell by the writing means is performed. 55. The semiconductor memory device according to claim 54. 57. As a result of the p-th write operation to the first bit of the second memory cell , the first write operation of the second memory cell is performed.
After the verifying means detects that desired writing has been performed on the bits of the first memory cell , the writing means performs a (p + 1) -th write operation on the second bit of the first memory cell . 55. The semiconductor memory device according to claim 54. 58. The write operation according to claim 53, wherein the p-th write operation is a first write operation, and the (p + 1) -th write operation is a second write operation. 13. The semiconductor memory device according to item 9. 59. The memory cell has a "1" state having a first threshold level, a "2" state having a second threshold level, and a "3" state having a third threshold level. A "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) having a threshold level,
When the memory cell is at the threshold level of the "1" state, the first write is performed based on write data input from outside the memory cell, and the memory cell is reset. "1" state, "2" state, ..., "m-1" state,
A first write mode for setting any one of the threshold levels in the “m” state (m is a natural number of 2 or more), and the memory cells in the “1” state, the “2” state,.
The second write is performed when the threshold level is any one of the state and the "m" state, and based on the write data input from outside the memory cell and the threshold level of the memory cell, the second write is performed. Cell in "1" state, "2"
58. A second write mode having a threshold level of any one of a state,..., A “k−1” state, and a “k” state (k is a natural number greater than m).
13. The semiconductor memory device according to claim 1. 60. The memory cell, wherein the "1" state has a first threshold level, the "2" state has a second threshold level, and the "3" state has a third threshold level. A "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) having a threshold level
, "R-1", "1" state, "2" state,.
The p-th write is performed when the threshold level is any one of the state and the “r” state (r is a natural number of 2 or more), and the write data input from outside the memory cell and the threshold of the memory cell are written. .., “S−1” state,..., “2” state,.
A j-th (j is a natural number of 2 or more) write mode for setting any one of the threshold levels in the “s” state (s is a natural number greater than r), and the “1” state, the “2” state, ..., "s-1"
The (p + 1) -th write is performed when the threshold level is any one of the state and the "s" state, and the memory is determined based on the write data input from outside the memory cell and the threshold level of the memory cell. Cell in "1" state,
, "T-1" state, "t" state (t is s
58. The semiconductor memory device according to claim 53, further comprising: a (j + 1) -th write mode in which one of the threshold levels is set to (a larger natural number). 61. A semiconductor memory device in which a memory cell group consisting of a predetermined plurality of memory cells forms a page serving as a writing unit, wherein the memory cell is capable of storing a plurality of bits of data.
Value (n is a natural number of 3 or more) storage memory cell, and a p-th (p is a natural number of 1 or more) write operation and p +
When writing a plurality of bits of data into the memory cell by the write operation of No. 1, the first bit of the plurality of bits of the plurality of memory cells belonging to the first page is assigned to the p-th data based on the first write data. Perform a write operation,
Of the plurality of bits of the memory cell group belonging to the second page.
After the first bit of the out was performed first p write operation based on the second write data, a second bit of said plurality of bits of memory cells belonging to the first page
And a p + 1-th write operation based on third write data. 62. A memory cell capable of storing a plurality of bits of data, a data circuit holding write data of the memory cell, and a write operation to the memory cell in accordance with the write data held in the data circuit Writing means for performing the following operations: detecting whether or not write data held in the data circuit has been written to the memory cell, and detecting whether the desired writing has been performed; A verifying means for repeating a write operation to the memory cell, wherein a memory cell group including a plurality of predetermined memory cells forms a page serving as a write unit, wherein a p-th (p is a natural number of 1 or more) Write operation and p +
When writing a plurality of bits of data into the memory cell by the write operation of No. 1, the first bit of the plurality of bits of the plurality of memory cells belonging to the first page is assigned to the p-th data based on the first write data. Perform a write operation,
Of the plurality of bits of the memory cell group belonging to the second page.
After the first bit of the out was performed first p write operation based on the second write data, a second bit of said plurality of bits of memory cells belonging to the first page
And a p + 1-th write operation based on third write data. 63. A memory cell group belonging to the first page
Following the first p + 1 of the write operation to the second bit of said plurality of bits, the fourth write data to the second bit of said plurality of bits of memory cells belonging to the second page 63. The semiconductor memory device according to claim 61, wherein a p + 1-th write operation is performed based on the write operation. 64. A memory cell group belonging to the first page
As a result of the p-th write operation to the first bit of the memory cell group, the memory cells of the memory cell group forming the first page
After the verifying means detects that the desired writing has been performed with one bit , the writing means performs a p-th writing operation on the first bit of the memory cell group belonging to the second page. 63. The semiconductor memory device according to claim 62, wherein: 65. A memory cell group belonging to the second page
As a result of the p-th write operation to the first bit of the memory cell group, the memory cells in the memory cell group forming the second page
After the verifying unit detects that the desired writing has been performed with one bit , the writing unit performs the (p + 1) th writing operation on the second bit of the memory cell group belonging to the first page. 63. The semiconductor memory device according to claim 62, wherein: 66. The method according to claim 61, wherein the p-th write operation is a first write operation, and the (p + 1) -th write operation is a second write operation. 13. The semiconductor memory device according to item 9. 67. The memory cell, wherein a "1" state has a first threshold level, a "2" state has a second threshold level, and a "3" state has a third threshold level. A "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) having a threshold level,
When the memory cell is at the threshold level of the "1" state, the first write is performed based on write data input from outside the memory cell, and the memory cell is reset. "1" state, "2" state, ..., "m-1" state,
A first write mode for setting any one of the threshold levels in the “m” state (m is a natural number of 2 or more), and the memory cells in the “1” state, the “2” state,.
The second write is performed when the threshold level is any one of the state and the "m" state, and based on the write data input from outside the memory cell and the threshold level of the memory cell, the second write is performed. Cell in "1" state, "2"
66. A second write mode having a threshold level of any one of a state,..., A “k−1” state, and a “k” state (k is a natural number greater than m).
13. The semiconductor memory device according to claim 1. 68. The memory cell, wherein the "1" state has a first threshold level, the "2" state has a second threshold level, and the "3" state has a third threshold level. A "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) having a threshold level
, "R-1", "1" state, "2" state,.
The p-th write is performed when the threshold level is any one of the state and the “r” state (r is a natural number of 2 or more), and the write data input from outside the memory cell and the threshold of the memory cell are written. .., “S−1” state,..., “2” state,.
A j-th (j is a natural number of 2 or more) write mode for setting any one of the threshold levels in the “s” state (s is a natural number greater than r), and the “1” state, the “2” state, ..., "s-1"
The (p + 1) -th write is performed when the threshold level is any one of the state and the "s" state, and the memory is determined based on the write data input from outside the memory cell and the threshold level of the memory cell. Cell in "1" state,
, "T-1" state, "t" state (t is s
66. The semiconductor memory device according to claim 61, further comprising: a (j + 1) th write mode in which any one of the threshold levels is set to (a larger natural number). 69. After the p-th write operation is performed on the memory cells belonging to all pages in the device, the memory cell group belonging to the first page is transferred to the second bit . 69. The semiconductor memory device according to claim 61, wherein the (p + 1) th write operation is performed. 70. The number of times the (p + 1) th write operation has been performed is stored for each page, and the order of writing is determined based on the number of times. 2. The semiconductor memory device according to claim 1. 71. A memory cell group comprising a predetermined plurality of memory cells sharing a single word line and a plurality of predetermined memory cells sharing the word line.
71. The semiconductor memory device according to claim 43, wherein a page serving as a writing unit is formed. 72. A storage system comprising a plurality of semiconductor memory devices each having a memory cell capable of storing data of a plurality of bits as a plurality of storage units, wherein a plurality of said memory cells are provided for each semiconductor memory device. A page as a write unit is formed by a memory cell group consisting of memory cells of the p-th (p is a natural number of 1 or more) write operation and p +
When writing a plurality of bits of data to the memory cell by the write operation of No. 1, the first bit of the plurality of bits of the memory cell group belonging to the page in the first semiconductor memory device
A p-th write operation is performed on one bit based on the first write data, and a first bit of the plurality of bits of the memory cell group belonging to the page in the second semiconductor memory device is performed.
After the p-th write operation is performed on the basis of the second write data, the second of the plurality of bits of the memory cell group belonging to the page in the first semiconductor memory device is read .
A storage system, wherein a (p + 1) -th write operation is performed on a bit based on third write data. 73. A second bit of the plurality of bits of a memory cell group belonging to a page in the first semiconductor memory device.
Following the p + 1 of the write operation to Tsu bets, the memory cell group belonging to a page within the second semiconductor memory device
73. The storage system according to claim 72, wherein a (p + 1) -th write operation is performed on a second bit of the plurality of bits based on fourth write data. 74. A memory cell belonging to a page in the second semiconductor memory device after performing the (p + 1) th write operation only on a memory cell group belonging to a part of the page in the first semiconductor memory device. 74. The storage system according to claim 73, wherein a (p + 1) -th write operation is performed on the group. 75. The write operation according to claim 72, wherein the p-th write operation is a first write operation, and the p + 1-th write operation is a second write operation. The storage system according to item. 76. The memory cell, wherein the "1" state has a first threshold level, the "2" state has a second threshold level, and the "3" state has a third threshold level. A "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 3) having a threshold level,
When the memory cell is at the threshold level of the "1" state, the first write is performed based on write data input from outside the memory cell, and the memory cell is reset. "1" state, "2" state, ..., "m-1" state,
A first write mode for setting any one of the threshold levels in the “m” state (m is a natural number of 2 or more), and the memory cells in the “1” state, the “2” state,.
The second write is performed when the threshold level is any one of the state and the "m" state, and based on the write data input from outside the memory cell and the threshold level of the memory cell, the second write is performed. Cell in "1" state, "2"
76. A second write mode for setting a threshold level of any one of a state,..., A “k−1” state, and a “k” state (k is a natural number larger than m).
The storage system of any of the preceding claims. 77. The memory cell has a "1" state having a first threshold level, a "2" state having a second threshold level, and a "3" state having a third threshold level. A "i" state (i is a natural number less than or equal to n and n is a natural number greater than or equal to 4) having a threshold level
, "R-1", "1" state, "2" state,.
The p-th write is performed when the threshold level is any one of the state and the “r” state (r is a natural number of 2 or more), and the write data input from outside the memory cell and the threshold of the memory cell are written. .., “S−1” state,..., “2” state,.
A j-th (j is a natural number of 2 or more) write mode for setting any one of the threshold levels in the “s” state (s is a natural number greater than r), and the “1” state, the “2” state, ..., "s-1"
The (p + 1) -th write is performed when the threshold level is any one of the state and the "s" state, and the memory is determined based on the write data input from outside the memory cell and the threshold level of the memory cell. Cell in "1" state,
, "T-1" state, "t" state (t is s
75. The storage system according to any one of claims 72 to 74, further comprising: a (j + 1) th write mode in which any one of the threshold levels is set to (a larger natural number). 78. After the p-th write operation is performed on the first bits of the memory cell group belonging to all pages in all the semiconductor memory devices forming the storage unit, the first semiconductor memory device the inner group of memory cells belonging to the page of
78. The storage system according to claim 72, wherein the (p + 1) -th write operation to a second bit is performed. 79. The storage system according to claim 72, further comprising means for controlling an operation of said semiconductor memory device. 80. The storage system according to claim 79, wherein said means for controlling the operation of said semiconductor memory device controls the order of writing to each memory cell group forming said page. 81. The storage system according to claim 80, wherein said write order is determined in page units. 82. The storage system according to claim 80, wherein said write order is determined for each device. 83. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the “4” state is the fourth threshold level.
In a semiconductor memory device having a memory cell storing a quaternary value having a threshold level of “1”, the “1” state is an erased state, and the first write data is changed to the first write data during the first write operation. When the logic level is at the logic level, the memory cell maintains the "1" state. When the first write data is at the second logic level, the memory cell is at the "2" state. As a result of the first write operation, "1" In the second write operation, when the second write data is at the first logical level, the memory cell maintains the "1" state, and the second write data is at the second logical level. In the case of, the memory cell which is in the state "3" as a result of the first write operation is in the state "2" during the second write operation. Cell is A semiconductor memory device, which maintains a "2" state and enters a "4" state when second write data is at a second logical level. 84. The semiconductor memory according to claim 83, wherein the value of the threshold level is larger or smaller in the order of said first, second, third and fourth threshold levels. apparatus. 85. The semiconductor memory according to claim 83, wherein the value of the threshold level is larger or smaller in the order of said first, third, second and fourth threshold levels. apparatus. 86. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the “4” state is the fourth threshold level.
The "5" state has a fifth threshold level, the "6" state has a sixth threshold level, and the "7" state has a seventh threshold level. Has threshold level, "8"
In a semiconductor memory device including a memory cell storing an octal value whose state has an eighth threshold level, a "1" state is an erased state, and a first write operation is performed in a first write operation. Is at the first logic level, the memory cell maintains the "1" state, and when the first write data is at the second logic level, the memory cell is at the "2" state. As a result, the memory cell in the “1” state performs the second write operation, and when the second write data is at the first logical level, the memory cell maintains the “1” state, and the second write data is in the second write operation. In the case of the logic level of 2, the memory cell is in the "3" state. As a result of the first write operation, the memory cell which is in the "2" state has the second write data of the first logic level in the second write operation. In case The memory cell keeps the "2" state, becomes the "4" state when the second write data is at the second logical level, and the memory cell which is in the "1" state as a result of the second write operation becomes the third state. At the time of the write operation, when the third write data is at the first logical level, the memory cell maintains the “1” state, and when the third write data is at the second logical level, the memory cell is in the “5” state, The memory cell in the “2” state as a result of the second write operation performs the third write operation, and when the third write data is at the first logical level, the memory cell maintains the “2” state. When the write data of No. 3 is at the second logical level, the state becomes "6". As a result of the second write operation, the memory cell which is in the state of "3" performs the third write operation when the third write data becomes "3". The first logical level In the case of, the memory cell keeps the "3" state, and when the third write data is at the second logical level, the memory cell becomes the "7" state. As a result of the second write operation, the memory is in the "4" state. When the third write data is at the first logical level, the memory cell maintains the "4" state when the third write data is at the first logical level, and when the third write data is at the second logical level, the cell is at the "4" state. A semiconductor memory device which is in an 8 ″ state. 87. The threshold level values may be in the order of the first, second, third, fourth, fifth, sixth, seventh and eighth threshold levels. 87. The semiconductor memory device according to claim 86, wherein the value is larger or smaller. 88. The threshold level values may be in the order of the first, fifth, third, seventh, second, sixth, fourth, and eighth threshold levels. 87. The semiconductor memory device according to claim 86, wherein the value is larger or smaller. 89. The "1" state has a first threshold level, the "2" state has a second threshold level, and "3"
The state has a third threshold level, and the “4” state is the fourth threshold level.
The "5" state has a fifth threshold level, the "6" state has a sixth threshold level, and the "7" state has a seventh threshold level. Has threshold level, "8"
The state has an eighth threshold level, and the "9" state is the ninth threshold level.
The "10" state has a tenth threshold level, the "11" state has an eleventh threshold level, and the "12" state has a twelfth threshold level. The "13" state has a thirteenth threshold level,
The "14" state has a fourteenth threshold level and "1"
In a semiconductor memory device having a memory cell storing 16 values such that the “5” state has a fifteenth threshold level and the “16” state has a sixteenth threshold level, the “1” state Is an erased state. In the first write operation, when the first write data is at the first logical level, the memory cell maintains the "1" state and the first write data is at the second logical level. In this case, the memory cell is in the “2” state, and the memory cell that is in the “1” state as a result of the first write operation performs the second write operation when the second write data is at the first logical level. Indicates that the memory cell keeps the "1" state, becomes "3" when the second write data is at the second logical level, and the memory cell which is in the "2" state as a result of the first write operation is When writing 2 When the second write data is at the first logic level, the memory cell keeps the "2" state, and when the second write data is at the second logic level, it goes to the "4" state. During the third write operation, the memory cell which is in the “1” state as a result of the write operation of “1” is kept in the “1” state when the third write data is at the first logical level. When the data is at the second logic level, the memory cell is in the “5” state. As a result of the second write operation, the memory cell that is in the “2” state performs the third write operation in response to the first write data in the first write operation. In the case of the logic level, the memory cell keeps the "2" state, and in the case where the third write data is the second logic level, the memory cell becomes the "6" state. As a result of the second write operation, the "3" state Some memory cells have a third write In the only operation, when the third write data is at the first logic level, the memory cell keeps the "3" state, and when the third write data is at the second logic level, it goes into the "7" state, The memory cell in the “4” state as a result of the second write operation performs the third write operation. When the third write data is at the first logical level, the memory cell maintains the “4” state. When the write data of No. 3 is at the second logical level, the state becomes "8". When the memory cell which is in the state of "1" as a result of the third write operation performs the fourth write operation, the fourth write data becomes "4". In the case of the first logic level, the memory cell maintains the "1" state, and in the case where the fourth write data has the second logic level, the memory cell is in the "9" state. As a result of the third write operation, "2" Memory During the fourth write operation, when the fourth write data is at the first logical level, the memory cell keeps the "2" state, and when the fourth write data is at the second logical level, "10" The memory cell in the "3" state as a result of the third write operation performs the fourth write operation, and when the fourth write data is at the first logical level, the memory cell is in the "3" state. When the fourth write data is at the second logic level, the memory cell is in the “11” state. As a result of the third write operation, the memory cell that is in the “4” state performs the fourth write operation during the fourth write operation. When the write data is at the first logical level, the memory cell maintains the "4" state, and when the fourth write data is at the second logical level, the memory cell becomes "12". The result “5” At the time of the fourth write operation, when the fourth write data is at the first logical level, the memory cell maintains the “5” state, and the fourth write data is at the second logical level. In the case, the memory cell is in the state "13", and the memory cell in the state "6" as a result of the third write operation is in the fourth write operation, and when the fourth write data is at the first logical level, the memory cell is in the state "13". Maintains the "6" state, and enters the "14" state when the fourth write data is at the second logical level. The memory cell which is in the "7" state as a result of the third write operation performs the fourth write operation. In operation, when the fourth write data is at the first logical level, the memory cell maintains the "7" state, and when the fourth write data is at the second logical level, the memory cell is in the "15" state. Third writing The memory cell which is in the “8” state as a result of the read operation performs the fourth write operation. If the fourth write data is at the first logic level, the memory cell maintains the “8” state and the fourth write data Is in a "16" state when is at a second logic level. 90. The threshold level value of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and ninth 90. The semiconductor memory device according to claim 89, wherein the threshold values are larger or smaller in order of the tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, and sixteenth threshold levels. 91. The method according to claim 91, wherein the values of the threshold levels are the first, ninth, fifth, thirteenth, third, eleventh, seventh, fifteenth, second, and third. 90. The semiconductor memory device according to claim 89, wherein the threshold values are larger or smaller in the order of 10, the sixth, the fourteenth, the fourth, the twelfth, the eighth, and the sixteenth threshold level.