JP4679490B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to, for example, a NAND flash EEPROM, and more particularly to a semiconductor memory device capable of storing multi-value data in one memory cell.

  In a NAND flash memory, all or a half of a plurality of cells arranged in the row direction are connected to bit lines, and write and read latch circuits are connected to each bit line. Data is collectively written in or read out from all or half of the cells arranged in the row direction. Recently, with an increase in memory capacity, multi-level memories that store data of 2 bits or more in one cell have been developed (see, for example, Patent Document 1). In this multilevel memory, when storing 2 bits, it is necessary to set four threshold voltages in the memory cell. When storing 3 bits, it is necessary to set eight threshold voltages, and when storing 4 bits. It is necessary to set 16 threshold voltages.

  As described above, when storing data of a plurality of bits in a memory cell, it is necessary to connect a data storage circuit to the bit line in order to store write data or read data. This data storage circuit is composed of a plurality of latch circuits.

However, as the number of threshold voltages stored in one memory cell increases, the number of latch circuits constituting the data storage circuit increases and the writing speed decreases.
JP 2004-192789 A

  An object of the present invention is to provide a semiconductor memory device capable of storing multilevel data while suppressing an increase in latch circuits and capable of high-speed writing.

According to an aspect of the semiconductor memory device of the present invention, a memory cell array in which a plurality of memory cells connected to a word line and a bit line are arranged in a matrix, and a first control for controlling the potential of the word line and the bit line And a data storage circuit for storing write data for a write operation that is connected to the bit line and sets a threshold of 2 ^k (k is a natural number of 3 or more) in the memory cell in the memory cell array. and, said data storage circuit is composed of the k latch circuits for storing at least one bit of data, respectively, said data storage circuit comprises at least one static latch circuit, a plurality of dynamic latch circuit, wherein At least one static latch circuit is connected to the outside, the at least one static latch circuit and the plurality of static latch circuits The dynamic latch circuit is characterized by inputting write data input from the outside and latching internal write data corresponding to a write operation.

  According to the present invention, it is possible to provide a semiconductor memory device capable of storing multilevel data while suppressing an increase in latch circuits and capable of high-speed writing.

  Embodiments of the present invention will be described below with reference to the drawings.

(First reference example )
FIG. 2 shows a schematic configuration of a NAND flash memory that stores, for example, 4-bit, 16-value data.

  The memory cell array 1 includes a plurality of bit lines, a plurality of word lines, and a common source line, and memory cells that are electrically rewritable, such as EEPROM cells, are arranged in a matrix. A bit control circuit 2 and a word line control circuit 6 for controlling bit lines are connected to the memory cell array 1.

  The bit line control circuit 2 reads the data of the memory cells in the memory cell array 1 via the bit lines, detects the state of the memory cells in the memory cell array 1 via the bit lines, and stores the memory via the bit lines. A write control voltage is applied to the memory cells in the cell array 1 to write to the memory cells. A column decoder 3 and a data input / output buffer 4 are connected to the bit line control circuit 2. The data storage circuit in the bit line control circuit 2 is selected by the column decoder 3. Data of the memory cell read to the data storage circuit is output to the outside from the data input / output terminal 5 via the data input / output buffer 4.

  Write data input from the outside to the data input / output terminal 5 is input to the data storage circuit selected by the column decoder 3 via the data input / output buffer 4.

  The word line control circuit 6 is connected to the memory cell array 1. The word line control circuit 6 selects a word line in the memory cell array 1 and applies a voltage necessary for reading, writing or erasing to the selected word line.

  The memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input / output buffer 4, and the word line control circuit 6 are connected to a control signal and control voltage generation circuit 7, and the control signal and control voltage generation circuit 7 Be controlled. The control signal and control voltage generation circuit 7 is connected to a control signal input terminal 8 and is supplied with control signals ALE (address latch enable) and CLE (command latch enable) input from the outside via the control signal input terminal 8. ) And WE (write enable).

  The bit line control circuit 2, column decoder 3, word line control circuit 6, control signal and control voltage generation circuit 7 constitute a write circuit and a read circuit.

  Further, the control signal and control voltage generation circuit 7 includes a dynamic data cache (DDC) control circuit 7-1. The DDC control circuit 7-1 generates a control signal for controlling refresh operations of a plurality of DRAMs as dynamic latch circuits included in the data storage circuit, as will be described later.

  FIG. 3 shows the configuration of the memory cell array 1 and the bit line control circuit 2 shown in FIG. A plurality of NAND cells are arranged in the memory cell array 1. One NAND cell includes a memory cell MC made up of, for example, 32 EEPROMs connected in series, and select gates S1 and S2. The selection gate S2 is connected to the bit line BL0e, and the selection gate S1 is connected to the source line SRC. The control gates of the memory cells MC arranged in each row are commonly connected to the word lines WL0 to WL29, WL30, and WL31. The selection gate S2 is commonly connected to the select line SGD, and the selection gate S1 is commonly connected to the select line SGS.

  The bit line control circuit 2 has a plurality of data storage circuits 10. A pair of bit lines (BL0e, BL0o), (BL1e, BL1o)... (BLie, BLio), (BL8ke, BL8ko) are connected to each data storage circuit 10.

  The memory cell array 1 includes a plurality of blocks as indicated by broken lines. Each block includes a plurality of NAND cells, and data is erased in units of blocks, for example. The erase operation is simultaneously performed on two bit lines connected to the data storage circuit 10.

  In addition, a plurality of memory cells arranged every other bit line and connected to one word line (memory cells in a range surrounded by a broken line) constitute one sector. Data is written and read for each sector.

  During the read operation, the program verify operation, and the program operation, the address signals (YA0, YA1,... YAi,... YA8k) supplied from the outside of the two bit lines (BLie, BLio) connected to the data storage circuit 10 are used. In response, one bit line is selected. Furthermore, one word line is selected according to the external address, and four pages indicated by broken lines are selected. The four pages are switched by address.

  4A and 4B are cross-sectional views of the memory cell and the select transistor. FIG. 4A shows a memory cell. In the substrate 51 (P-type well region 55 described later), an n-type diffusion layer 42 is formed as the source and drain of the memory cell. A floating gate (FG) 44 is formed on the P-type well region 55 via a gate insulating film 43, and a control gate (CG) 46 is formed on the floating gate 44 via an insulating film 45. Yes. FIG. 4B shows the selection gate. In the P-type well region 55, an n-type diffusion layer 47 as a source and a drain is formed. A control gate 49 is formed on the P-type well region 55 via a gate insulating film 48.

  FIG. 5 shows a cross-sectional view of the NAND flash memory. For example, N-type well regions 52, 53 and 54 and a P-type well region 56 are formed in the P-type semiconductor substrate 51. A P-type well region 55 is formed in the N-type well region 52, and a low-voltage N-channel transistor LVNTr constituting the memory cell array 1 is formed in the P-type well region 55. Further, a low-voltage P-channel transistor LVPTr and a low-voltage N-channel transistor LVNTr constituting the data storage circuit 10 are formed in the N-type well region 53 and the P-type well region 56. In the substrate 51, a high-voltage N-channel transistor HVNTr that connects the bit line and the data storage circuit 10 is formed. In the N-type well region 54, for example, a high voltage P-channel transistor HVPTr constituting a word line driving circuit or the like is formed. As shown in FIG. 5, the high voltage transistors HVNTr and HVPTr have, for example, a thicker gate insulating film than the low voltage transistors LVNTr and LVPTr.

  FIG. 6 shows an example of the voltage supplied to each region shown in FIG. In erasing, programming, and reading, a voltage as shown in FIG. 6 is supplied to each region. Here, Vera is a voltage applied to the substrate at the time of erasing data, Vss is a ground voltage, Vdd is a power supply voltage, Vpgmh is a voltage Vpgm + Vth supplied to a word line at the time of writing data, and Vfix is a memory cell at the time of reading data. The voltage Vreadh supplied to the formed well is the voltage Vread + Vth supplied to the word line when reading data.

  FIG. 1 is a circuit diagram showing an example of the data storage circuit 10 shown in FIG.

  The data storage circuit 10 shows a case where, for example, 4-bit, 16-value data is written and read, and a primary data cache (PDC), a secondary data cache (SDC), a dynamic data cache (DDCA, DDCB, DDCC, DDCD) and temporary data cache (TDC). SDC, PDC, DDCA, DDCB, DDCC, DDCD hold input data at the time of writing, hold read data at the time of reading, hold data temporarily at the time of verification, and store internal data when storing multi-value data Used for operation. The TDC amplifies and temporarily holds bit line data when reading data, and is used to manipulate internal data when storing multilevel data.

  The SDC includes clocked inverter circuits 61a and 61b and transistors 61c and 61d that constitute a static latch circuit. The transistor 61c is connected between the input terminal of the clocked inverter circuit 61a and the input terminal of the clocked inverter circuit 61b. A signal EQ2 is supplied to the gate of the transistor 61c. The transistor 61d is connected between the output terminal of the clocked inverter circuit 61a and the ground. A signal PRST is supplied to the gate of the transistor 61d. The node N2a of the SDC is connected to the input / output data line IOn via the column selection transistor 61e, and the node N2b is connected to the input / output data line IO via the column selection transistor 61f. A column selection signal CSLi is supplied to the gates of the transistors 61e and 61f. The node N2a of the SDC is connected to the node N1a of the PDC via the transistors 61g and 61h. A signal BLC2 is supplied to the gate of the transistor 61g, and a signal BLC1 is supplied to the gate of the transistor 61h.

  The PDC includes clocked inverter circuits 61i and 61j and a transistor 61k that constitute a static latch circuit. The transistor 61k is connected between the input terminal of the clocked inverter circuit 61i and the input terminal of the clocked inverter circuit 61j. A signal EQ1 is supplied to the gate of the transistor 61k. The node N1b of the PDC is connected to the gate of the transistor 61l. One end of the current path of the transistor 61l is grounded through the transistor 61m. A signal CHK1 is supplied to the gate of the transistor 61m. The other end of the current path of the transistor 61l is connected to one end of the current path of the transistors 61n and 61o constituting the transfer gate. A signal CHK2n is supplied to the gate of the transistor 61n. The gate of the transistor 61o is connected to the node N3. The other ends of the current paths of the transistors 61n and 61o are connected to the signal line COMi. This signal line COMi is commonly connected to all the data storage circuits 10, and it can be determined whether or not the verification of all the data storage circuits 10 has been completed based on the level of this signal line COMi. That is, as will be described later, when the verification is completed, the node N1b of the PDC becomes low level (the node N1a is high level). In this state, if the signals CHK1 and CHK2n are set to the high level, the signal COMi is set to the high level when the verification is completed.

  Further, the TDC is constituted by, for example, a MOS capacitor 61p. One end of the capacitor 61p is connected to the connection node N3 of the transistors 61g and 61h, and a signal BOOST described later is supplied to the other end. Further, DDCA, DDCB, DDCC, DDCD are connected to connection node N3 via transistors 61qA-61qD. Signals REGA to REGD are supplied to the gates of the transistors 61qA to 61qD.

  DDCA, DDCB, DDCC, DDCD constituting the dynamic latch circuit are constituted by transistors 61rA to 61rD. The signal VPRE is supplied to one end of the current path of the transistors 61rA to 61rD, and the other end is connected to the current path of the transistors 61qA to 61qD. The gates of the transistors 61rA to 61rD are connected to the node N1a of the PDC via the transistors 61sA to 61sD, respectively. Signals DTGA to DTGD are supplied to the gates of the transistors 61sA to 61sD, respectively.

  Further, one end of a current path of the transistors 61t and 61u is connected to the connection node N3. The signal VPRE is supplied to the other end of the current path of the transistor 61u, and BLPRE is supplied to the gate. A signal BLCLAMP is supplied to the gate of the transistor 61t. The other end of the current path of the transistor 61t is connected to one end of the bit line BLo through the transistor 61v, and is connected to one end of the bit line BLe through the transistor 61w. One end of the bit line BLo is connected to one end of the current path of the transistor 61x. A signal BIASo is supplied to the gate of the transistor 61x. One end of the bit line BLe is connected to one end of the current path of the transistor 61y. A signal BIASe is supplied to the gate of the transistor 61y. A signal BLCRL is supplied to the other ends of the current paths of the transistors 61x and 61y. The transistors 61x and 61y are turned on complementarily to the transistors 61v and 61w in response to the signals BIASo and BIASe, and supply the potential of the signal BLCRL to the unselected bit lines.

  For example, a MOS capacitor 61z is connected between the node N3 and the ground. The capacitor 61z adjusts the potential of the node N3 so that the potential of the node N3 does not rise too much due to coupling when the TDC capacitor 61p described later is boosted by the signal BOOST. Hereinafter, the PDC data is the potential of the node N1a, the SDC data is the potential of the node N2a, and the TDC data is the potential of the node N3. Data of DDCA to DDCD is the potential of the gates of the transistors 61rA to 61rD.

  The above signals and voltages are generated by a control signal and control voltage generation circuit 7 shown in FIG. 2, and data write, verify, and read operations are controlled based on the control of the control signal and control voltage generation circuit 7. Further, DDCA to DDCD are refreshed by the control signal generated by the DDC control circuit 7-1.

  This memory stores 4-bit data with 16 threshold voltages in one cell. This switching of 4 bits is controlled by an address (first page, second page, third page, fourth page).

  FIG. 7 shows a timing diagram illustrating the address input cycle. The command latch enable signal CLE shown in FIG. 7 is set to low level (hereinafter referred to as L level or L), the address latch enable signal ALE is set to high level (hereinafter referred to as H level or H), and the write enable signal is set. When WEn is changed from L level to H level, I / O0-7 input from the outside is read as an address.

  FIG. 8 shows the input cycle and address assignment. As shown in FIG. 8, the first and second cycles are column addresses, and the third cycle I / O0-1 (A16, A17) is an MLC (Multi Level Cell) address for switching page addresses. Lower page when A17) = (L, L), Upper page when (A16, A17) = (H, L), Higher page when (A16, A17) = (L, H), (16, A17) = I / O3 (A18) of the third cycle, which becomes the top page when (H, H), selects one of the two bit lines (BLie, BLio), and the I / O 3-7 of the third cycle (A19-A23) selects one of the 32 word lines in the NAND cell. The fourth and fifth cycles indicate block addresses.

  FIG. 9 shows the relationship between the memory cell array (planes 0 and 1) and blocks. As shown in FIG. 9, the NAND flash memory has two planes 0 and 1. Each plane 0, 1 has, for example, the memory cell array 1, the bit line control circuit 2, the column decoder 3, and the word line control circuit 6 shown in FIG. The control signal and control voltage generation circuit 7, the control signal input terminal 8, the data input / output buffer 4, and the data input / output terminal 5 are shared by each plane. In FIG. 9, only the bit line control circuit 2 is shown.

  In addition, blocks 0 to 2047 are arranged on the plane 0, and blocks 2048 to 4095 are arranged on the plane 1. As described above, since a plurality of blocks are arranged for the planes 0 and 1, the plane is selected by the I / O 3 (A36) of the fifth cycle. It is also possible to select, read, program, and erase one block at a time in each plane, for a total of two blocks.

  The normal memory has a redundancy block in addition to the blocks 0 to 4095 shown in FIG. 9, and if there is a defect in the blocks 0 to 4095, when this defect is accessed, the redundancy block is selected. However, since the redundancy switching circuit is large, blocks EX0 to EX31 are added to increase the original number of blocks as shown in FIG. If the blocks 0 to 4095 and the blocks EX0 to EX31 are defective, the defective block is not used. However, since extra blocks are provided, there are minimum required non-defective blocks. In this case, when a defective block is accessed, the block is not selected and no word line is selected. For example, in the case of reading, the bit line is charged but not discharged, so that the defective block can be distinguished by reading the highest level data.

  However, the user wants to store important data in specific blocks, such as block 0, block 2048, and the like. For this reason, these specific blocks need to be non-defective. For example, when block 0 is defective, it is replaced with block EX31. When block 0 is accessed, block EX31 (non-defective product) is selected, and when block EX31 is accessed, block 0 is to be selected. However, since block 0 is defective, no word line is selected. For example, in the case of reading, the bit line is charged but not discharged. For this reason, a defective block can be distinguished by reading the highest level data. Of course, it is also possible to prepare dedicated redundancy blocks for specific blocks, such as block 0 and block 2048, respectively.

  FIG. 10 shows the relationship between memory cell data and memory cell threshold values. When the erase operation is performed, the memory cell data has the threshold voltage distribution shown on the left. Thereafter, 4-bit (16-valued) data is stored in one cell according to the write operation. That is, first, as shown in FIG. 10, four threshold voltages “0” to “3” are set in the memory cell by the 2-bit data of the lower page and the upper page by the first stage write operation. .

  Next, as shown in FIG. 11, “0” to “F” are stored in the memory cell by 4-bit data of the lower page, upper page, higher page, and top page by the write operation of the second stage and the third stage. 16 threshold voltages are set.

  10 and 11, the R & V level indicates a read and verify level, and VL (3) to VL (0) indicate levels 0 to F in bits. That is, level 0 is represented by (0000), level 1 is represented by (0001), level 2 is represented by (0010)... Level F is represented by (1111).

(Program and program verify)
(Program order)
FIG. 12 shows the order of writing to the memory cells in this reference example . The write operation is performed for each page from the memory cell close to the source line in the block. At this time, the threshold voltage is prevented from changing due to writing of adjacent memory cells. That is, the write operation is performed in a certain order in order that the threshold voltage of the memory cell written earlier reduces the influence of the threshold voltage of the memory cell written later.

  FIG. 13A to FIG. 13F show the transition of the threshold voltage of the memory cell accompanying the write operation. 4-bit (16-valued) data is written to one cell by three write operations of the first stage, the second stage, and the third stage.

  First, in the first write [0] shown in FIG. 12, a memory cell is selected by the word line WL0 and the even bit line BLe. By the first stage write operation, 2-bit (ternary) data of the lower page and the upper page is written into this memory cell. As a result, the threshold voltage as shown in FIG.

  Next, in the second write [1], a memory cell is selected by the word line WL0 and the odd bit line BLo. By the first stage write operation, 2-bit (ternary) data of the lower page and the upper page is written into this memory cell.

  Next, in the third write [2], a memory cell is selected by the word line WL1 and the even bit line BLe. By the first stage write operation, 2-bit (ternary) data of the lower page and the upper page is written into this memory cell.

  Next, in the fourth write [3], a memory cell is selected by the word line WL1 and the odd bit line BLo. By the first stage write operation, 2-bit (ternary) data of the lower page and the upper page is written into this memory cell.

  As described above, when data is written in the adjacent cell, for example, the threshold distribution of the memory cell selected by the word line WL0 and the bit line BLe is changed in the threshold voltage of the adjacent cell as shown in FIG. It is affected and spreads.

  Next, in the fifth write [4], a memory cell is selected by the word line WL0 and the bit line BLe. By the second stage write operation, 4-bit (16-value) data of the lower page, upper page, higher page, and top page is written into this memory cell. As a result, the threshold voltage distribution as shown in FIG.

  Next, in the sixth write [5], a memory cell is selected by the word line WL0 and the bit line BLo. By the second stage write operation, 4-bit (16-value) data of the lower page, upper page, higher page, and top page is written into this memory cell.

  Next, in the seventh write [6], a memory cell is selected by the word line WL2 and the bit line BLe. By the first stage write operation, 2-bit (ternary) data of the lower page and the upper page is written into this memory cell.

  Next, in the eighth write [7], a memory cell is selected by the word line WL2 and the bit line BLo. By the first stage write operation, 2-bit (ternary) data of the lower page and the upper page is written into this memory cell.

  Next, in the ninth write [8], a memory cell is selected by the word line WL1 and the bit line BLe. By the second stage write operation, 4-bit (16-value) data of the lower page, upper page, higher page, and top page is written into this memory cell.

  Next, in the tenth write [9], a memory cell is selected by the word line WL1 and the bit line BLo. By the second stage write operation, 4-bit (16-value) data of the lower page, upper page, higher page, and top page is written into this memory cell.

  Then, for example, the threshold voltage distribution of the memory cell selected by the word line WL0 and the bit line BLe is widened by the change of the threshold voltage of the adjacent cell as shown in FIG.

  Next, in the eleventh write [10], a memory cell is selected by the word line WL0 and the bit line BLe. By the third stage write operation, 4-bit (15 values) data of the lower page, the upper page, the higher page, and the top page are written into the memory cell. Then, as shown in FIG. 13E, the distribution of each threshold voltage is narrowed.

  Next, in the twelfth write [11], a memory cell is selected by the word line WL0 and the bit line BLo. By the third stage write operation, 4-bit (15 values) data of the lower page, the upper page, the higher page, and the top page are written into the memory cell.

  Next, in the 13th write [12], a memory cell is selected by the word line WL3 and the bit line BLe. By the first stage write operation, 2-bit (ternary) data of the lower page and the upper page is written into this memory cell.

  Next, in the 14th write [13], a memory cell is selected by the word line WL3 and the bit line BLo. By the first stage write operation, 2-bit (ternary) data of the lower page and the upper page is written into this memory cell.

  Next, in the fifteenth write [14], a memory cell is selected by the word line WL2 and the bit line BLe. By the second stage write operation, 4-bit (16-value) data of the lower page, upper page, higher page, and top page is written into this memory cell.

  Next, in the 16th write [15], a memory cell is selected by the word line WL2 and the bit line BLo. By the second stage write operation, 4-bit (16-value) data of the lower page, upper page, higher page, and top page is written into this memory cell.

  Next, in the 17th write [16], a memory cell is selected by the word line WL1 and the bit line BLe. By the third stage write operation, 4-bit (15 values) data of the lower page, the upper page, the higher page, and the top page are written into the memory cell.

  Next, in the 18th write [17], a memory cell is selected by the word line WL1 and the bit line BLo. By the third stage write operation, 4-bit (15 values) data of the lower page, the upper page, the higher page, and the top page are written into the memory cell.

  Then, for example, the threshold voltage distribution of the memory cells selected by the word line WL0 and the bit line BLe slightly expands as the threshold voltage of the adjacent cells changes as shown in FIG.

  By writing in this order, the threshold voltage of the adjacent cell changes, the spread of the threshold voltage of the cell can be suppressed, and a narrow threshold voltage distribution can be obtained.

  14 and 15 show a first modification of FIGS. 12 and 13.

  In the first modification shown in FIGS. 14 and 15, only 1-bit (binary) data of the lower page is written in the first stage write operation. This writing method is effective when the coupling capacitance with an adjacent cell is small and the change in threshold voltage is small.

  16 and 17 show a second modification of FIGS. 12 and 13.

  In the second modification shown in FIGS. 16 and 17, 3-bit (eight values) data of a lower page, an upper page, and a higher page is written in the first stage write operation. This writing method is effective when the coupling capacity with an adjacent cell is large and the change in threshold voltage is large.

(Address input and data input)
In this reference example , as shown in FIG. 13 to FIG. 17, first, in the first stage write operation, the memory cell has 2 bits (4 values), 1 bit (2 values), or 3 bits (8 values). Data is written, and thereafter data is similarly written to the adjacent cells. Next, in the second stage write operation, 4 bits (16 values) of data are roughly written to a level lower than the original verify level. Thereafter, data is further written to the adjacent cell. In the third stage write operation, 4-bit (16-valued) data is written to the original verify level.

  FIG. 18 is a timing chart showing the write operation in the third stage. First, as shown in FIG. 18, in the control signal supplied to the control signal input terminal 8 shown in FIG. 2, the command latch enable signal CLE is set to H level, the address latch enable signal ALE is set to L level, and the write signal is written. The enable signal WEn is set to L level and a data load command (80h, h indicates hexadecimal) is fetched. Thereafter, the command latch enable signal CLE is set to L level, the address latch enable signal ALE is set to H level, the write enable signal WEn is set to L level, and the address and write data are input as described above. The write data is stored in the SDC (shown in FIG. 1) in the data storage circuit (shown in FIG. 9) corresponding to the plane specified by the address. Thereafter, when a write command (15h or 10h) or a data transfer command (1Ah) is input, SDC data in the data storage circuit 2 of the selected plane is transferred to the PDC, and further transferred to DDCA to DDCD. Is done. When data “1” (not written) is input from the outside, the node N1a of the PDC becomes H level, and when data “0” (write) is input, it becomes L level. Thereafter, the data of the PDC is the potential of the node N1a, and the data of the SDC is the potential of the node N2a.

  FIG. 19A to FIG. 19K show the relationship between commands and data in the first stage to the third stage.

  FIG. 19A shows a case where 2-bit (4-value) writing is performed in the first stage. First, the address and data of the lower page are input, the data transfer command (1Ah) is input, the upper page address and data are input, and the write command (10h or 15h) is input. In the circuit, since the address of the upper page is input, it can be seen that the writing is four values.

  FIG. 19B shows a case where 1 bit (binary) is written in the first stage. First, the address and data of the lower page are input, and the write command (10h or 15h) is input. Since only the address of the lower page is input in the circuit, it can be seen that binary writing is performed.

  FIG. 19C shows a case where 3 bits (8 values) are written in the first stage. First, the address and data of the lower page are input, and the data transfer command (1Ah) is input. Thereafter, the address and data of the upper page are input, and the data transfer command (1Ah) is input. Thereafter, a higher page address and data are input, and a write command (10h or 15h) is input. Since the address of the higher page is input to the inside of the circuit, it can be seen that 8-level writing is performed.

  FIG. 19D shows a case where 2 bits (4 values) are written in the first stage. Even if the lower page and the upper page are switched, since the upper page is input, it can be recognized as writing four values. That is, FIG. 19E shows a case where 2 bits (4 values) are written in the first stage. First, as shown in FIG. 19B, 1 bit (binary value) is written, and as shown in FIG. 19E, the address and data of only the upper page are input. When a write command (10h or 15h) is input, since the address of the upper page is input, it can be recognized as a 4-value write. In this case, although the data of the lower page is not input, it is also possible to read the data of the lower page previously written in the circuit by a read operation (internal data load).

  FIG. 19F shows a case where 4 bits (16 values) are written in the second stage. First, the address and data of the lower page are input, the data transfer command (1Ah) is input, the address and data of the upper page are input, the data transfer command (1Ah) is input, and then the address and data of the higher page are input. After inputting the data transfer command (1Ah), the address and data of the top page are input, and the write command (10h or 15h) is input. In this case, since the address of the top page is input, it can be recognized that the writing is 4 bits (16 values). However, this sequence is the same as when 4 bits (16 values) are written in the third stage. Therefore, in order to distinguish between the second stage and the third stage, for example, in the case of the second stage, the command 0Dh is input before writing.

  FIG. 19G shows a case where only the address and data of the higher page and the address and data of the top page are input, and the data input to the lower page and upper page is loaded with the previously input data. .

  FIG. 19 (h) shows a case where 4 bits (16 values) are written in the third stage. First, the address and data of the lower page are input, and the data transfer command (1Ah) is input. Thereafter, the address and data of the upper page are input, and the data transfer command (1Ah) is input. Next, the address and data of the higher page are input, and the data transfer command (1Ah) is input. Thereafter, the top page address and data are input, and a write command (15h or 10h) is input. Since the address of the top page is input, it can be recognized that the writing is 4 bits (16 values). In the operation of the third stage, as shown in FIG. 19 (i), the order of input addresses and data may be changed.

  FIG. 19J shows the case of two-plane simultaneous writing in the case of FIG. Furthermore, as shown in FIG. 19 (k), it is possible to input in an arbitrary order. A short busy is output by inputting the command 11h, but it can be omitted.

  In the second stage writing, writing is also performed on the erased cell and writing to level 0 is performed. In the case of writing of REASB (Erased Area Self Boost) described later, the selected word line is set to Vpgm (24 V), the word line adjacent to the source side with respect to the selected word line is set to Vpass or an intermediate potential, and further The potential of the word line adjacent to the word line is set to Vss (ground potential) to turn off the cell. In this way, erroneous writing is prevented, but if the threshold voltage of the erase cell is too low, it will not turn off. Therefore, writing is also performed on the erased cell, and writing to level 0 is performed.

  FIG. 20 shows an example of the DDC control circuit 7-1 shown in FIG. The DDC control circuit 7-1 sequentially generates the signals DTGA to DTGD and the signals REGA to REGD shown in FIG. 1 according to the page address and the selection signal SLDDC (0: 3), and the operations of DDCA, DDCB, DDCC, DDCD To control. Further, the DDC control circuit 7-1 changes the relationship between the data stored in DDCA, DDCB, DDCC, and DDCD and the page address. That is, the write data is supplied to the data storage circuit in an arbitrary order, and is stored in one of DDCA, DDCB, DDCC, DDCD via SDC, PDC. For this reason, it is necessary to recognize which page address corresponds to the data stored in DDCA, DDCB, DDCC, DDCD. Further, DDCA to DDCD are dynamic caches and it is necessary to periodically refresh stored data. At this time, the data stored in DDCA to DDCD and PDC is refreshed by transferring the data using DDCA to DDCD, TDC and PDC. When performing this refresh operation, it is necessary to recognize which data is transferred to DDCA to DDCD and PDC. The DDC control circuit 7-1 can accurately control the positions of a plurality of data by storing which page of data is stored in DDCA, DDCB, DDCC, DDCD, and PDC.

  In FIG. 20, converters 7a to 7e correspond to DDCA, DDCB, DDCC, DDCD, and PDC, respectively. These converters 7a to 7d hold data LDDC0, LDDC1, LDDC2, LDDCQ, and LDCCP indicating logical cache names according to the lower page, upper page, higher page, top page, and PDC, and this data is converted into the converter 7a. To 7e can be transferred.

  Each converter 7a to 7d has first to fifth input ends and first and second output ends, respectively, and converter 7e has an input end and an output end. At the first input terminals of the converters 7a to 7d, for example, a lower page (L), an upper page (U), a higher page (H), and a top page (T) converted into 4-bit data by the decoder 7f. Either is supplied. The decoder 7f sequentially decodes the page address input according to the command. A DDC set signal DDCSET is supplied to the second input terminal. The DDC set signal DDCSET sets a DDC set mode that allows a page address to be input from the decoder 7f. For example, a 4-bit selection signal SLDDC (0: 3) for selecting the DDCA to DDCD is supplied to the third input terminals of the converters 7a to 7d. A mode switching signal MEXC is supplied to the fourth input terminals of the converters 7a to 7d. This mode switching signal MEXC sets the refresh mode. The fifth input terminals of the converters 7a to 7d are connected to the output terminal of the converter 7e. In the refresh mode, the output signal of the converter 7e is transferred to one of the converters 7a to 7d.

  The first output terminals of converters 7a to 7d are connected to one input terminals of AND circuits 7g to 7j that selectively output signals REGA to REGD, and AND circuit 7k that selectively outputs signals DTGA to DTGD. To one input terminal of 7 n. A signal REG is supplied to the other input terminals of the AND circuits 7g to 7j, and a signal DTG is supplied to the other input terminals of the AND circuits 7k to 7n. The AND circuits 7g to 7j are supplied with a signal SLDDC for selecting DDCD from the DDCA, and when signals DDCASL to DDCDSL are output from one or more first output terminals of the converters 7a to 7d, Signals REGA to REGD corresponding to this are output. The AND circuits 7k to 7n are supplied with a signal SLDDC for selecting a DDCD from the DDCA, and when signals DDCASL to DDCDSL are output from one or more first output terminals of the converters 7a to 7d, Signals DTGA to DTGD corresponding to this are output.

  The second output terminals of the converters 7a to 7d are connected to the input terminal of the converter 7e. When DDCA to DDCD are refreshed, data LDDC output from one second output terminal of converters 7a to 7d is supplied to the input terminal of converter 7e in response to mode switching signal MEXC. Data LDDC output from converter 7e is supplied to one of converters 7a-7d. Details of the refresh operation will be described later.

  FIG. 21 shows the configuration of the converter 7a. Converters 7a to 7d have substantially the same configuration, and only input signals are different. Therefore, only the converter 7a will be described.

  The converter 7a includes four flip-flop circuits 7a-1 to 7a-4 constituting a register, a selector 7a-5 that selects an input signal of each flip-flop circuit 7a-1 to 7a-4, and a comparison circuit 7a-6. have. Each flip-flop circuit 7a-1 to 7a-4 holds one of 4-bit data. Each flip-flop circuit 7a-1 to 7a-4 can preset default data. The output signals of the flip-flop circuits 7a-1 to 7a-4 are supplied to the comparison circuit 7a-6 and to an output selector (not shown). In response to the mode switching signal MEXC, the output selector supplies an LDDC signal to the output converter 7e from the converters corresponding to the DDCA to DDCD during the refresh operation among the converters 7a to 7d.

  The comparison circuit 7a-6 compares the output signals of the flip-flop circuits 7a-1 to 7a-4 with the selection signal SLDDC (0: 3), and if they match, the selection signal DDCASL is in an active state, for example, a high level. And

  The selector 7a-5 switches input signals of the flip-flop circuits 7a-1 to 7a-4 according to the mode switching signal MEXC. That is, the selector 7a-5 selects the page address supplied from the decoder 7f when the DDC set signal DDCSET is in an active state, for example, a high level, and the mode switching signal MEXC is in an active state, for example, a high level. When the output signal 7a-6 is in the active state, the data LDDC (0: 3) supplied from the converter 7e is selected. Therefore, the data LDDC (0: 3) output from the converter 7e is supplied to one selected converter.

  FIG. 22 shows an example of the converter 7e. The converter 7e is composed of flip-flop circuits 7e-1 to 7e-4. In response to the mode switching signal MEXC, among the converters 7a to 7d, the data LDDC (0: 3) output from the converter corresponding to the DDCA to DDCD being refreshed is the flip-flop circuits 7e-1 to 7e-4. To be supplied. The data stored in each flip-flop circuit 7e-1 to 7e-4 is supplied to any of converters 7a to 7d corresponding to DDCA to DDCD during the refresh operation.

  The operation of the DDC control circuit 7-1 in the above configuration will be described. Converters 7a to 7d correspond to DDCA to DDCD. In the default state, converters 7a, 7b, 7c, and 7d are set to LDDC0, LDDC1, LDDC2, and LDDCQ, respectively, and converter 7e is set to LDDCP. When an address and data for writing are input, the selection signal SLDDC (0: 3) becomes active in the order of SLDDC2, SLDDC1, SLDDC0, and SLDDCQ. Therefore, the comparator satisfies the input conditions of the comparison circuit 7a-6 shown in FIG. 21 in the order of 7c, 7b, 7a, and 7d. Therefore, the selection signals are output in the order of DDCCSL, DDCBSL, DDCASL, DDCDSL from the comparison circuit 7a-6 of the comparators 7c, 7b, 7a, 7d. At this time, the signal DTG shown in FIG. 20 is in an active state, for example, high level, the AND circuit satisfies the input conditions in the order of 7m, 7l, 7k, and 7n, and the signals are in the order of DTGC, DTGB, DTGA, and DTGD. Is output. For this reason, the data transferred from the SDC to the PDC in FIG. 1 in accordance with the data transfer command is stored in the order of DDCC, DDCB, DDCA, DDCD.

  Thereafter, after the write command is input, when the DDC set signal DDCSET shown in FIG. 20 is in an active state, for example, high level, the page address supplied from the decoder 7f is supplied to the converters 7a to 7d. At this time, the converters are selected in the order of 7c, 7b, 7a, and 7d by the selection signal SLDDC (0: 3). For this reason, the data of the decoder 7f is supplied in the order of converters 7c, 7b, 7a, 7d. Therefore, when the page data supplied from the decoder 7f is a top page (T), a higher page (H), an upper page (U), or a lower page (L) as shown in FIG. 20, for example, the converter 7c, Top page (T), higher page (H), upper page (U), and lower page (L) data are set in the flip-flop circuits 7b, 7a, and 7d.

  In this way, the relationship between the page address and the data stored in DDCA to DDCD shown in FIG.

(refresh)
Next, the refresh operation will be described.

  When the data transfer command 1Ah is input, as described above, the SDC data in the data storage circuit 2 of the selected plane is transferred to the PDC, and further transferred to DDCA to DDCD. However, since DDCA to DDCD are capacitances for storing data by the gate capacitance of the transistor, refresh operation is required. Therefore, after the transfer command 1Ah is input, when the transfer operation from DDCA to DDCD is completed, the chip is changed from the busy state to the ready state to wait for the next data input. The refresh operation is repeated.

  For example, in FIG. 1, when refreshing DDCA data, first, the transistor 61u is turned on with the signal VPRE = Vss (ground voltage) and the signal BLPRE = Vss, and the node N3 of the TDC is set to Vss. Thereafter, the signal VPRE = Vdd and the signal REGA = H level are set to turn on the transistor 61qD. Then, when DDCA = H level, TDC becomes H level, and when DDCA = L level, TDC remains L level. Thereafter, the signal DTGA is once set to the H level, the PDC data is copied to the DDCA, and then the BDC1 is set to the H level to transfer the TDC data to the PDC. With these operations, DDCA data moves to PDC, and PDC data moves to DDCA. By performing these operations once again, the DDCA data is restored. Thus, when refreshing the DDCA data, two refresh operations are required.

In the case of the memory for writing 16-value data in this reference example , the data storage circuit 2 has four dynamic data latches DDCA, DDCB, DDCC, and DDCD as shown in FIG. For this reason, when data is moved by the above operation, eight refresh operations are required. However, in the first reference example , the refresh operation can be speeded up.

  FIG. 23 shows an example of the refresh operation. As shown in FIG. 23, for example, the data held in DDCA, DDCB, DDCC, DDCD, and PDC before refreshing is, for example, LDDC0, LDDC1, LDDC2, LDDCQ, and LDDCP (representing logical cache names, respectively). Consider the assumption. When these data are moved from DDCA to DDCD, PDC as shown in FIG. 23 (in FIG. 5, LDDC0, LDDC1, LDDC2, LDDCQ, LDDCP are simply indicated by 0, 1, 2, P, Q) All data is moved by the fifth data movement. Data is refreshed by moving once. For this reason, all the data is refreshed by the fifth data movement. However, after the fifth data movement, LDDC0, LDDC1, LDDC2, LDDCQ, and LDCCP are stored in DDCA, DDCB, DDCC, DDCD, and PDC. That is, the data cache in which LDDC0 is stored is DDCA before refreshing, but becomes DDCB after refreshing. Therefore, the positional relationship of DDCA, DDCB, DDCC, DDCD, and PDC data is different before and after refresh. However, by performing the refresh operation using the DDC control circuit 7 shown in FIGS. 20, 21, and 22, the correspondence relationship between the data stored in DDCA, DDCB, DDCC, DDCD, and PDC and the page address is always matched. be able to.

  That is, it is assumed that the data stored in the registers of the converters 7a to 7e shown in FIG. 20 are LDDC0, LDDC1, LDDC2, LDDCQ, and LDCCP as before the refresh shown in FIG.

  In this state, when the mode switching signal MEXC shown in FIGS. 20 and 21 is set in an active state and, for example, LDDC0 is selected by the selection signal SLDDC (0: 3), the input condition of the comparison circuit 7a-6 of the converter 7a is satisfied. . For this reason, the signal DDCASL is output from the converter 7a. At this time, signals REG and DTG shown in FIG. 20 are set to H level, and signals REGA and DTGA are set to H level.

  On the other hand, before transferring the data of DDCA, the signal BLPRE shown in FIG. 1 is set to the H level, the signal VPRE is set to the L level, for example, Vss (ground potential), and the node N3 is reset to the ground potential. Thereafter, the signal VPRE is set to the H level, for example, Vdd. When the signal REGA is set to H level, the transistor 61qA is turned on, and DDCA data is transferred to the TDC. That is, when the gate of the transistor 61rA is at H level, the node N3 is at H level, and when the gate of the transistor 61rA is at L level, the node N3 is kept at L level.

  Further, in accordance with the signal DTGA shown in FIG. 20, the transistor 61sA is turned on, and the data of the PDC is transferred to DDCA. Thereafter, the signal BLC1 is set to the H level, and the TDC data is transferred to the PDC via the transistor 61h.

  At this time, data LDCCP corresponding to the PDC of converter 7e shown in FIG. 20 is transferred to converter 7a, and data LDDC0 corresponding to DDCA stored in converter 7a is transferred to converter 7e.

  As described above, when the first transfer operation is executed, it is as shown after one time in FIG. By sequentially performing such an operation on LDDC1, LDDC2, LDDCQ, and LDCCP, the data of DDCA to DDCD can be refreshed by five transfer operations. In addition, since the position of the refreshed data is held by the converters 7a to 7e, the data can be accurately controlled.

(Write sequence, data load, program)
24 shows a write sequence. FIGS. 25A, 25B, 25C, 25D, and 25E show input data in 16-value, 8-value, 4-value, and 2-value accompanying the write sequence shown in FIG. And the write level relationship.

As shown in FIG. 24, data of an arbitrary page (for example, 2 kB) is input from the outside to the SDC of the data storage circuit 10 by 80h (data load command) -Add (address) -D (data) (S1 FIG. 25 (a)). In the case of data input for only one page, a write command 10h or a cache write command 15h is input (S2). When multiple pages of data are input, a 1Ah command is input. In the case of 1Ah, SDC data is transferred to DDCA to DDCD via PDC. As described above, in this reference example , when the first time is 1 Ah, the SDC data is transferred to LDDC2 (DDCC) (S3), and when the second time is 1 Ah, the SDC data is LDDC1 (DDCB). (S4), and in the case of the first 1Ah, the SDC data is transferred to LDDC0 (DDCA) (S5). Thereafter, when the write command 10h or the write command 15h with a cache function is input (S6), the SDC data is transferred to the LDDCQ (DDCD) and is in a busy state (see FIG. 18). When data is transferred to the SDC, PDC, DDCA to DDCD, it is determined whether the write level is 16-value, 8-value, 4-value, or 2-value (16LV / 8LV / 4LV / 2LV).

  The data storage circuit 10 shown in FIG. 1 transfers SDC data to the PDC and DDCA to DDCD according to the output signal of the DDC control circuit 7-1. Hereinafter, data stored in DDCA to DDCD and PDC will be described as LDDC0, LDDC1, LDDC2, LDDCP, and LDDCQ.

  The SDC data is transferred to the LDDCQ according to the data of the DDC control circuit 7-1 shown in FIG. Thereafter, when the number of data inputs is small with respect to the write level, the internal data is loaded and the data is input to the vacant LDDC (S7). FIG. 25B shows the relationship between the data input from the outside, the data input by the internal data load, and the data stored in the data cache after the input. In FIG. 25 (b), data indicated by L or U indicates that when the number of times of data input is small with respect to the write level, the internal data is loaded and data is input to an empty LDDC. W, X, Y, and Z indicate the order of data input in an arbitrary order for convenience.

  Thereafter, the data caches DDCA to DDCB are defined (S8, FIGS. 25 (c) and 25 (d)).

  That is, as described above, the correspondence relationship between the data stored in DDCA to DDCB and the page address is defined. Specifically, in the case of 16 values, the DDC storing the lower page data is defined as LDDC2, the DDC storing the upper page is defined as LDDC1, and the DDC storing the higher page is defined as LDDC0. And DDC storing the top page is defined as LDDCQ. In the case of eight values, the DDC storing lower page data is defined as LDDC2, the DDC storing upper page data is defined as LDDC0, and the DDC storing higher page data is defined as LDDC0. It is defined as LDDCQ. Further, in the case of four values, a DDC storing lower page data is defined as LDDC1, and a DDC storing upper page data is defined as LDDCQ. Further, in the case of binary, the DDC storing the data of the lower page is defined as LDDC0.

In this reference example , the distinction between writing and non-writing is stored in the PDC. In the case of writing, PDC = L level, and in the case of non-writing, PDC = H level. A method has been proposed in which a lower verify level is set in addition to the original verify level, and when this lower verify level is exceeded, the write distribution is narrowed by decreasing the increment of the subsequent write voltage. The distinction as to whether or not this lower verify level has been exceeded is stored as LDDCQ. When the lower verify level is not exceeded, LDDCQ = L level, and when the lower verify level is exceeded, LDDCQ = H level. In writing 16 values, 4-bit data is necessary to distinguish the 16 values, and these data are stored as LDDC2, LDDC1, LDDC0, and SDC. In the case of 8-level writing, 3-bit data is necessary to distinguish the 8-level values, and these data are stored as LDDC2, LDDC1, and LDDC0. In the case of four-value writing, 2-bit data is necessary to distinguish the four values, and these data are stored as LDDC1 and LDDC0.

  FIG. 25E shows the write level and the data set in the data cache. Data at each threshold voltage is rearranged by the operations of the data caches DDCA and DDCB shown in FIG. 24, step S9, and FIG. In this way, by setting data for each threshold voltage, it becomes possible to release SDC, LDDC2, and the like from sequential write operations as data write progresses. Therefore, since the next data can be set in the opened SDC, LDDC2, etc., the writing speed can be increased. In order to obtain such an effect, data is set as shown in FIG.

  In FIG. 25E, the threshold voltage is defined as 0-level to f-level from the low side to the high side. By the erase operation, the threshold voltage of the cell becomes 0-level, and is raised from the 1-level to the f-level by the write operation.

  During data writing, writing to the lower threshold is completed faster than writing to the higher threshold. For this reason, when the write command 15h with a cache function is input, in the 16-value write, when the write from the 0-level to the 7-level is completed, the data data of the SDC becomes unnecessary. Therefore, the ready state is indicated outside the chip, and the next write data is input. After that, a “1Ah / 10h / 15h” command is input to enter a busy state.

  Further, in the case of the 1Ah command, when the writing from the 8-level to the b-level is completed, the data data of the LDDC 2 becomes unnecessary. Therefore, after the data input to the SDC is moved to the LDDC 2, the ready state is indicated outside the chip, and the next write data can be input. After that, a “1Ah / 10h / 15h” command is input to enter a busy state.

  In the case of the 1Ah command, when the writing to the c-level and the d-level is completed, the data data of the LDDC 1 becomes unnecessary. For this reason, after the data input to the SDC is moved to the LDDC1, the ready state is indicated outside the chip, and the next write data can be input. After that, a “1Ah / 10h / 15h” command is input to enter a busy state.

  In the case of the 1Ah command, when the writing to the e-level is completed, the data data of LDDC0 becomes unnecessary. For this reason, after the data input to the SDC is moved to the LDDC0, the ready state is indicated outside the chip, and the next write data can be input. Thereafter, a busy state is entered by a 15h command or a 10h command, which is a write command, and after the previous page has been written, the next page write operation is started.

  In the case of 8-level writing, since the SDC is not used originally, after the data cache operation, the ready state is shown outside the chip, and the next write data can be input. After that, a “1Ah / 10h / 15h” command is input to enter a busy state.

  In the case of the 1Ah command, when the writing from the 0-level to the 3-level is completed, the data in the LDDC 2 becomes unnecessary. For this reason, after the data input to the SDC is moved to the LDDC 2, the ready state is indicated outside the chip, and the next write data can be input. After that, a “1Ah / 10h / 15h” command is input to enter a busy state.

  In the case of the 1Ah command, when the writing to the 4-level and the 5-level is completed, the data of the LDDC1 becomes unnecessary. For this reason, after the data input to the SDC is moved to the LDDC1, the ready state is indicated outside the chip, and the next write data can be input. After that, a “1Ah / 10h / 15h” command is input to enter a busy state.

  In the case of the 1Ah command, when the writing to the 6th level is completed, the data data of LDDC0 becomes unnecessary, so after the data input to SDC is moved to LDDC0, the ready state is indicated outside the chip and the next writing is performed. Allows data entry. Thereafter, a busy state is entered by a 15h command or a 10h command, which is a write command, and after the previous page has been written, the next page write operation is started.

  In the case of writing four values, SDC is not used originally. For this reason, after the data cache operation, the ready state is indicated outside the chip, and the next write data can be input. After that, a “1Ah / 10h / 15h” command is input to enter a busy state.

  In the case of a 1Ah command, the LDDC2 is not used for writing four values. For this reason, after the data input to the SDC is moved to the LDDC 2, the ready state is indicated outside the chip, and the next write data can be input. Thereafter, a busy state is entered by inputting a 1 Ah command.

  In the case of the 1Ah command, when writing to the 1-level is completed, the data data of the LDDC 1 becomes unnecessary. For this reason, after the data input to the SDC is moved to the LDDC1, the ready state is indicated outside the chip, and the next write data can be input. After that, a “1Ah / 10h / 15h” command is input to enter a busy state.

  In the case of the 1Ah command, the data data of the LDDC 1 becomes unnecessary when the writing to the 2-level is completed. For this reason, after the data input to the SDC is moved to the LDDC1, the ready state is indicated outside the chip, and the next write data can be input. Thereafter, a busy state is entered by a 15h command or a 10h command, which is a write command, and after the previous page has been written, the next page write operation is started.

  In the case of binary writing, SDC is not used originally. For this reason, after the data cache operation, the ready state is indicated outside the chip, and the next write data can be input. After that, a “1Ah / 10h / 15h” command is input to enter a busy state.

  In the case of a 1Ah command, LDDC2 is not used in binary writing. For this reason, after the data input to the SDC is moved to the LDDC 2, the ready state is indicated outside the chip, and the next write data can be input. Thereafter, a busy state is entered by inputting a 1 Ah command.

  In the case of a 1Ah command, LDDC1 is not used for binary writing. For this reason, after the data input to the SDC is moved to the LDDC1, the ready state is indicated outside the chip, and the next write data can be input. Thereafter, a busy state is entered by inputting a 1 Ah command.

  In the case of a 1Ah command, LDDC0 is not used in binary writing. For this reason, after the data input to the SDC is moved to the LDDC0, the ready state is indicated outside the chip, and the next write data can be input. Thereafter, a busy state is entered by a 15h command or a 10h command, which is a write command, and after the previous page has been written, the next page write operation is started.

  According to such an operation, it can be used even when the 1Ah transfer command continues three times, that is, when the next write data has 4 pages and 16 values. However, for example, when the next writing is binary, 10h / 15h which is a writing command is input after data of one page is input. However, for example, another write command 16h is prepared, and after the command 16h is input, the data input to the SDC is transferred to the LDDC. Thereafter, the next data can be input from the outside. Since LDDC has 2, 1, 0 and SDC, it is possible to load data up to four pages ahead.

  Similarly, not only the next write data but also the next write data or even the next write data can be loaded in the case of 4-value and 8-value.

(Program operation)
After the operation of the data cache and the definition of the data cache, a program operation is performed (S10).

  In FIG. 1, when the signal BLC1 is set to Vdd + Vth (transistor threshold voltage) and data “1” (not written) is stored in the PDC, the bit line becomes Vdd, and data “0” (write is written). The bit line is at Vss. In addition, the cell in the non-selected page (bit line is not selected) connected to the selected word line must not be written. Therefore, the voltage Vdd is also supplied to the bit lines connected to these cells.

  Next, after setting the signal BLC1 = Vss, the DDC storing the data LDDCQ is selected. That is, the DDC control circuit 7-1 shown in FIG. 20 sets one of the signals REGA to REGD corresponding to the DDC storing LDDCQ among the DDCA to DDCE to the H level. When the lower verify level is passed, the bit line is set to an intermediate potential. However, since the verify operation is not performed once in the first program verify loop, the bit line is not set to the intermediate potential.

  Here, the select line SG1 of the selected block is supplied with Vdd, the selected word line is supplied with Vpgm (24V), and the non-selected word line is supplied with Vpass (10V). Then, when the bit line is Vss, the cell channel is Vss and the word line is Vpgm, so that writing is performed. On the other hand, when the bit line is Vdd, the cell channel rises Vpgm instead of Vss, and becomes approximately Vpgm / 2 due to coupling. For this reason, it is not programmed. Further, when the bit line is at an intermediate potential, writing is performed only slightly.

(Program operation, write data detection)
The signal line COMi shown in FIG. 1 is commonly connected to all the data storage circuits 10. During the write operation, the signal line COMi is temporarily charged to set the signal CHK2n = H level and the signal CHK1 = H level. Since the node N1a of the PDC of the data storage circuit 10 being written is at the L level, the transistor 61l is turned on and the potential of the signal line COMi becomes the L level. On the other hand, when the node N1a of the PDCs of all the data storage circuits is at the H level, the potential of the signal line COMi remains at the H level. Therefore, it can be seen that all writing has been completed.

  Further, the number of data storage circuits that are turned on can be counted by connecting a current detection circuit to the signal line COMi. For example, when the number of data storage circuits that are not yet completed is small, the writing speed can be improved by leaving the writing of the few cells and ending the writing. These cells cause errors when data is read, but can be corrected by an error correction circuit.

(Program operation, refresh)
Since DDCA to DDCD are capacitances as described above, a refresh operation is required during writing and during writing recovery. As described above, the refresh operation is the same as the refresh operation after 1 Ah input.

As shown in FIG. 26 (a), (distinction of writing or non-writing) data LPDC in PDC, (distinction whether it exceeds the lower verify level) LDDCQ to DDCA, the DDCB to LDDC0, DDCC LDDC1, DDCD Assume that LDDC2 is stored in each. With the fifth refresh operation, LPDC is stored in PDC, LDDC2 is stored in DDCA, LDDCQ is stored in DDCB, LDDC0 is stored in DDCC, and LDDC1 is stored in DDCD.

(Program and program verify read)
27, 28, and 29 show an example of the relationship between the program and the verify in the write sequence.

  FIG. 36 shows the potentials of the word line and the bit line at one level in the program verify. FIG. 36 shows that verification is performed by two sequences of verification at a level (VL) lower than the original verification level and verification at the original verification level (V).

  FIG. 27 shows an example in which 3 levels are written in the first stage, FIG. 28 shows 16 levels in the second stage, and FIG. 29 shows 15 levels in the third stage.

  For example, in the third stage write sequence shown in FIG. 29, after the first write (program (P) with a loop count of 1), the write is performed from a level with a lower threshold value, so verify is performed at level 1. After this, after performing the second write (loop 2 program (P)), level 1 verify, third write, level 1 verify, after the fourth write, level 1 verify is performed. And level 2 verify. As the number of write loops increases in this way, high level verification is started.

  Further, after the 22nd writing, verify from level 1 to level 8 is performed. Next, after the 23rd write, verify from level 2 to level 8 is performed, and verify at level 1 is omitted. That is, even when there is a write bit to level 1 and writing is incomplete, level 1 verification may not be performed after the 23rd time. As described above, when the maximum number of times of verification is provided for each level of verification, a cell in which writing is not completed even when the maximum number of times has been reached naturally causes an error in reading. However, this error can be corrected by an error correction circuit. In this way, the number of verifications can be reduced, and the writing time can be increased. Further, since it is possible to open SDC and DDC, it is also possible to input next write data.

  After the 61st write, after the level E and level F verify, the 62nd write and the level F only verify are performed, and the 63rd, 64th write, and the level F only verify are performed. To finish. When writing to all the data storage circuits 10 is completed and the signal line COMi becomes H level by writing data detection performed during writing, that is, when there is no writing cell, or the writing cell is defined. When the number is less than the number, subsequent writing and verification are not performed.

  Further, the verify at each level is not performed thereafter when there is no write bit to this level. Whether there is a write bit for each level is detected during verification of each level.

  FIG. 30 is performed in parallel with the program and the program verify operation during the program (write) or program verify, and determines whether to perform the next program or verify. Further, when performing program verification, it is determined which level is executed.

  PC is a program counter that counts the number of program loops, and PCV is a register that stores the number of program verify starts. PCV = PCV + DPCV + DDPCV (VL) (VL is a verify level). DPCV, DDPCV (0) to DDPCV (F) are values stored in a ROM (not shown) in the chip. For example, in FIG. 29, DPCV = 3, DDPCV (0) to DDPCV (F) = 0, 28, DPCV = 2, DDPCV (0) = 1, DDPCV (1) to DDPCV (F) = 0, and in FIG. 27, DPCV = 4 and DDPCV (1) to DDPCV (3) = 0.

  In step S21, first, VL (next verify level) = 0 and PCV = 0 are set. In step S22, it is determined whether the PC is equal to or higher than PCV. If this result is not reached, the program voltage is stepped up and the program is executed again.

  If PC is equal to or higher than PCV, it is determined in step 23 whether or not the next verify level is write completion. If writing at the next verify level has not been completed, COMP (0) = L. For this reason, program verify is executed. At this time, since the verify level is VL = 0, level 0 verification is executed.

  When the writing of the next verify level is completed, COMP (0) = H. Therefore, in step S25, VL = VL + 1 is executed, and it is determined whether or not the next program verify is performed (S26). For example, when verify of level 0 is performed, first, in step S24, VL is moved to VLX (indicating the current verify level), and VLX is moved to VLXX (indicating the previous verify level).

  That is, if VL = 0, VLX = 0. Here, it is determined whether or not the PC has reached the maximum number of loops set for each verification (PC ≧ DPCVMAX + PCV). If it has reached, this level of COMP (VL) = H is set. For example, the maximum number of loops is 8 in FIG. 27, 11 in FIG. 28, and 22 in FIG. Thereafter, in step S25, VL = VL + 1 is set. In step S26, VL = 0 in the case of 16-value writing, VL = 8 in the case of 8-value writing, VL = 4 in the case of quaternary writing, VL = 4, and VL = 2 in the case of binary writing. If these conditions are satisfied, the program voltage is stepped up and the program is executed again. If the condition is not satisfied, the process proceeds to step S22, and it is determined whether or not to perform the next program verify.

(Program verify: Bit line precharge)
FIGS. 31A, 31B, and 31C show level 1 and level 2 verification of the third stage shown in FIG. 29, and FIGS. 32A and 32B show the level B verification of the third stage. The write level and the data SDC, LDDC2 to LDDC0, and PDC stored in each data cache are shown. After the first write operation, the data cache is as shown in FIGS. 31 (a) and 32 (a).

  For example, as shown in FIGS. 31A, 31B, and 31C, when performing a level 1 verify operation, control is performed to the well of the selected cell, the source line, the non-selected bit line, and the select gate of the non-selected block. A voltage Vfix (for example, 1.6 V) is supplied from the signal and control voltage generation circuit 7. A potential level 1 'slightly higher than the potential level 1 at the time of reading is supplied to the selected word line. Hereinafter, “′” represents a verify potential slightly higher than the read potential. Therefore, at the time of reading and verifying, if the potential supplied to the selected word line is lower than Vfix, it appears that a negative potential is supplied to the gate of the cell. At the same time, Vread (reading potential) is supplied to the unselected word lines of the selected block, and a predetermined potential is supplied to the select gate SGD of the selected block.

  Next, the signal VPRE of the data storage circuit 10 shown in FIG. 1 is set to Vdd (for example, 2.5 V), the signal BLPRE is set to Vsg (Vdd + Vth), and the signal BLCLAMP is temporarily set to a potential of (0.6 V + Vth) + Vfix, for example. The bit line is precharged to 0.6V + Vfix = 2.2V, for example. Thereafter, after setting the signal BLPRE = Vss and the signal BLCLAMP = Vss, a predetermined potential is supplied to the select gate SGS.

  When the threshold value of the cell is higher than the verify level 1 ', the cell is turned off. For this reason, the bit line remains at the H level (eg, 2.2 V). If the verify level is lower than 1 ', the cell is turned on. For this reason, the bit line is discharged to the same potential as the source, that is, Vfix (for example, 1.6 V).

(Program verify: data inversion, forward refresh)
During the bit line discharge time, the data cache is refreshed as shown in FIG. At this time, for example, as shown in FIG. 31 (b), the refresh operation is executed so that only the data of LDDC0 is inverted so that the data of the data storage circuit written in level 1 becomes 0 in the verify of level 1. Is done. Further, when level 2 verification shown in FIG. 31C is performed after level 1 shown in FIG. 31B, LDDC1 and LDDC0 are set so that the data in the data storage circuit written in level 2 becomes 0. A refresh operation is performed so that the data is inverted. Therefore, as shown in FIG. 26B, LDDC (k) is refreshed by an inversion operation when XOR (exclusive OR) of the previous verify VLXX (k) and the current verify VLX (k) = 1. Perform the action.

  Here, when the verification is performed at a lower verification level, the operation is performed so that the data LPDC is stored in the PDC and the data LDDCQ is stored in the DDC. When verifying at the original verify level, the operation is performed so that the data LDDCQ is stored in the PDC and the data LPDC is stored in the DDC.

(Program verify: Read bit line potential)
As shown in FIG. 26 (c), at the time of verifying 0 to 7 levels, SDC = H, and the node N3 of the TDC of the data storage circuit written in the levels 0 to 7 is precharged to Vdd. When verifying level 8 to F, the signal BLPRE is once set to Vsg (Vdd + Vth), and the node N3 of the TDC is precharged to Vdd. After setting the signal BOOST from the L level to the H level, the signal BLCLAMP is set to, for example, (0.45 V + Vth) + Vfix. The node N3 of the TDC is precharged to Vdd at the beginning of the TDC. When the potential of the bit line is lower than 0.45V + Vfix, the node N3 becomes L level (Vfix (for example, 1.6V)), and the potential of the bit line is from 0.45V. When it is high, it remains H (αVdd (eg, 4.25 V)). After setting the signal BLCLAMP = Vtr (for example, 0.1 V + Vth), the signal BOOST is set from the H level to the L level.

  Thereafter, the signal VPRE is set to Vss, and the signal REG corresponding to LDDC2 and LDDC1 is set to the H level in the verification of level 1 (VLX = 1, 0001) shown in FIG. The data in each data storage circuit is as shown in FIG. For this reason, in the data storage circuit written in level 1, TDC becomes H level only when the verify level is reached. If the verify level has not been reached, the TDC remains at the L level. In addition, when data is written in levels 8 to F, the SDC data is 0. For this reason, TDC is Vss from the beginning. Further, when writing to levels 2 to 7, the signal REG is set to the H level to force TDC = Vss. For example, in the verification of level B (VLX = B, 1011) shown in FIGS. 32A and 32B, the signal REG corresponding to the data LDDC2 is set to H level. The data in each data storage circuit is as shown in FIG. For this reason, in the data storage circuit written in level B, only when the verify level is reached, TDC becomes H level. If the verify level has not been reached, the TDC remains at the L level. When writing to a level lower than level B, the cell is turned on. For this reason, TDC is L level. For this reason, in the data storage circuit written at level B, the TDC becomes H level only when the verify level is reached. If the verify level has not been reached, the TDC remains at the L level. Further, when writing to levels C to F, TDC is forcibly set to Vss by setting the signal REG to the H level.

  That is, when level n (VLX = VLX (3), VLX (2), VLX (1), VLX (0)) is set, verify at level n is performed when SDC is changed to TDC when VLX (3) = 0. When precharge is performed and VLX (3) = 1, the signal BLPRE is once set to Vsg (Vdd + Vth), and the node N3 of the TDC is precharged to Vdd. VLX (2), VLX (1), and VLX (0) correspond to LDDC2, LDDC1, and LDDC0, and an LDDC signal REG with VLX (2) = 0, VLX (1) = 0, and VLX (0) = 0. Is set to H level and TDC = Vss is forcibly set.

  Here, when the signal VREG = H and verification is performed at a low level, the signal REG corresponding to LDDCQ is set to H level, and when verification is performed at the original level, the signal REG corresponding to LPDC is forced to be H level. TDC is set to Vdd. Thereafter, the signal BLC1 is set to Vsg (Vdd + Vth), and the potential of the TDC is read into the PDC. As a result, when verification is performed at a lower level, LDDCQ data is stored in the PDC, and when verification is passed, the PDC becomes H level. In addition, when the verify level has not been reached, the PDC is L level, when verifying at the original verify level, the LPDC data is stored in the PDC, and when verifying is passed, the PDC is not at the H level and verify level. In the case of arrival, the PDC becomes L level.

(Program verify: Comp)
Thereafter, it is verified whether or not the writing by the verify level is completed. This operation is executed during recovery of the verify sequence at the original verify level. The presence or absence of verify data is detected by this verification.

  FIG. 26D shows the sequence of the verification operation. That is, the signal BLC2 is set to the H level during the verification of the levels 0 to 7, the signal VPRE is set to the Vdd during the verification of the levels 8 to F, and in this state, the signal BLPRE is set to the H level and the TDC is charged. To do. The TDC is at the H level only in the data storage circuits that are written in the levels 0 to 7 at the time of verifying the levels 8 to F and at the time of verifying the levels 0 to 7. Thereafter, the signal VPRE is set to L level, and the signals REG corresponding to LDDC0, LDDC1, and LDDC2 are set to H level. Then, for example, in the level 1 verify shown in FIG. 31B, the TDC of the data storage circuit written in the levels 8 to F is originally at the L level, and the data storage circuit written in the levels 0 and 2 to 7 Since any of LDDC2 to LDDC0 is at the H level, TDC is at the L level. Further, only the TDC of the data storage circuit written in level 1 becomes H level.

  For example, in the case of level B verification shown in FIG. 32B, any one of LDDC2 to LDDC0 of the data storage circuit written in level 3 and level B is at the H level. For this reason, TDC becomes L level, and only the TDC of the data storage circuit written in level 3 and level B becomes H level.

  Thereafter, similarly to the data detection during writing, the signal line COMi commonly connected to all the data storage circuits is temporarily charged, and the signal CHK2n is set to L level and the signal CHK1 is set to H level. Then, the PDC of the data storage circuit being written is at the L level and the transistor 61l is turned on only when the TDC is at the H level, and the potential of the signal line COMi is lowered. Therefore, it is possible to determine whether or not there is an incompletely written cell when this level is written.

  However, in the case shown in FIG. 32 (b), if there is an insufficiently written data storage circuit at level 3 during level B verification, data detection at level B will not pass.

(Data cache setting)
As shown in FIGS. 27, 28, and 29, when the program and the program verify are repeated several times, the low level writing should be completed. However, if there is a cell with a slow write of several bits, the verify is repeated until the writing of this cell is completed. For this reason, verification is not performed more than a certain number of times. However, in the case of the example shown in FIG. 32B, for example, if there is an insufficiently written data storage circuit at level 3 at the time of level B verification, data detection at level B will not be a pass. . Therefore, in the case of 16-value writing, when the writing of levels 0 to 7 is completed or the predetermined maximum number of loops is reached, the SDC is released. However, the SDC is released after the data storage circuit at levels 0 to 7 is written at level F before this.

  Further, in the case of 16-value writing, level 8 to B, and in the case of 8-value writing, when the writing of level 0 to 3 is completed or the predetermined maximum number of loops is reached, the state is released. However, before this, the data storage circuit in the writing state is set to the level F (16 value) and level 7 (8 value) writing, and then the LDDC 2 is released.

  Further, in the case of 16-level writing, level C and level D, in the case of 8-level writing, level 4 and level 5, in the case of 4-level writing, the level 1 writing is completed or a predetermined maximum number of loops If achieved, LDDC1 is opened. However, before this, the data storage circuit in the writing state is written at level F (16 values), level 7 (8 values), and level 3 (4 values), and then the LDDC 1 is released.

  In the case of 16-level writing, level E, 8-level writing, level 6, 4-level writing, level 2 writing is completed, or when the predetermined maximum number of loops is reached, LDDC0 Is released. However, before this, the data storage circuit in the writing state is written at level 15 (16 values), level 7 (8 values), and level 3 (4 values), and then LDDC0 is released.

  On the other hand, level 0 writing is performed only by reducing the deep threshold voltage of the erase cell. For this reason, whether level 0 writing is completed, or after the predetermined maximum number of loops has been reached, the PDC is forcibly set to H level (non-writing), and the above-mentioned incomplete data storage circuit is small. It can also be made not to be the target of the number. In this case (OMITOPPASS = H level: OMITOPPASS is a parameter for forcibly setting the PDC to the H level after reaching the predetermined maximum number of loops). After reaching the maximum number of loops, the PDC is forced to H level.

  FIGS. 33A, 33B, and 33C show a data setting sequence for the data cache. First, as shown in FIG. 33 (a), the data of LDDCs 0, 1, and 2 may be inverted, so all the data of LDDCs 0, 1, and 2 are restored. However, when the LDDC2 is opened, the data of the LDDC2 is inverted, and when the LDDC1 is opened, the data of the LDDC1 is inverted.

  Next, as shown in FIG. 33B, during the normal refresh operation, first, VPRE = Vss, BLPRE = H level, and TDC = Vss. However, when the SDC is released, the TDC is charged with BLC2 = H level, and the LDDC0, LDDC1, and LDDC2 are refreshed. Then, SDC = H level, that is, LDDC0, LDDC1, and LDDC2 of the data storage circuit in which data is written to levels 0 to 7 are set to “1”. That is, level F writing can be performed.

  When the LDDC2 is opened, the LDDC2 is “1”. Therefore, after setting the signal VPRE = Vss, the signal BLPRE = H level and TDC = Vss, the signal VPRE = Vdd, the LDDC2 signal REG = H level To do. In this way, when the TDC is charged and the LDDC0 and LDDC1 are refreshed, level 15 (16 values) and level 7 (8 values) can be written.

  When the LDDC 1 is opened, the LDDC 1 is “1”. For this reason, after setting the signal VPRE = Vss, the signal BLPRE = H level and TDC = Vss, the signal VPRE = Vdd and the signal REG of the LDDC1 are set to H level. In this way, when the TDC is charged and the LDDC0 is refreshed, writing of level 15 (16 values), level 7 (8 values), and level 3 (4 values) can be performed.

  After that, as shown in FIG. 33C, when OMITOPPASS is at the H level and is at the 16 level, the signal BLC2 is set to the H level, and the SDC data is copied to the TDC. Thereafter, the signal VPRE is set to the L level, all the signals REG are set to the H level, and the TDC is set to the H level only when writing to the level 0.

  If OMITOPPASS is at H level, if it is at level 8, signal VPRE is set to H level, signal BLPRE is set to H level, TDC is once precharged to Vdd, signal VPRE is set to L level, and all signals REG are set to H level. The TDC is set to the H level only when writing to the level 0. Thereafter, LDDCQ is copied to TDC, PDC is transferred to DDC, and then TDC is transferred to PDC. Again, in the same manner, the TDC is set to H level, the LDCCP is copied to the TDC, the PDC is transferred to the DDC, and then the TDC is transferred to the PDC.

  In this way, the PDC of the data storage circuit to be written to level 0 is forcibly set to the H level where writing is not selected. In FIG. 26C, after the verify bit line data is taken out to the TDC, the signal REG is set to the H level. As a result, data storage circuits other than the level to be verified are forced to fail. However, after the LDDC2 is released, the write data of the next page should be input to the LDDC2, and therefore the LDDC2 does not move. Similarly, after opening LDDC1, LDDC1 does not move, and after opening LDDC0, LDDC0 does not move.

  When the PDC is at the L level, the write operation is performed again, and this program operation and verify operation are repeated until the data in all the data storage circuits become the H level.

  In this example, writing to level 0 was performed in the second stage, and writing to level 0 was not performed in the third stage. That is, as shown in FIGS. 27, 28, and 29, level 3 was written in the first stage, level 16 was written in the second stage, and level 15 was written in the third stage. However, it is also possible to write to level 0 in the third stage without writing to level 0 in the second stage. In this case, in the first stage, writing is performed at a ternary level, writing is performed in a 15-level level in the second stage, and writing is performed in a 16-level level in the third stage. It is also possible to write to level 0 in the first stage.

  For verification at each level, a verification level lower than each verification level is set, and when this lower level is exceeded, writing is performed at a lower threshold voltage by writing at a lower writing speed. Is possible.

  In FIG. 13, FIG. 15, and FIG. 17, the verify at which the voltage of the word line is the lowest is the verify of level 0, and the verify at the level 0 of the lower verify is the lowest voltage, that is, 0V. However, only level 0 verification is performed at other verification levels. Without providing a lower verify level, if the verify of level 0 is set to 0V and the lower level is exceeded, writing can be stopped by slowing down the writing speed. As a result, the verify level of level 0 can be lowered. Further, since the lower level verify operation is eliminated, the writing speed can be increased.

  Of course, when not only level 0 but only a few arbitrary levels exceed a lower verify level, it is possible to slow down the write speed and stop the write operation.

  When the lower verify level is exceeded, the operation of slowing down the write operation by slowing down the write speed is performed at a high level (for example, level F, level F and level E, level F and level E, level D and level C). Stop when writing. Then, writing speed does not slow down. For this reason, the loop of program and program verify is reduced, and the write voltage can be lowered. Therefore, erroneous writing due to a high write voltage can be prevented.

  Further, as shown in FIG. 26B, after the refresh operation of PDCＤＣLDDC0, PDC⇔LDDC1, and PDC⇔LDDC2, the refresh operation of PDC⇔LDDCQ or PDC⇔LDDCP is always performed, and the data of PDC is converted to LDDCQ. Or LDDCP. This is because the read potential of the bit line is manipulated by data stored in DDCA to DDCD and SDC. That is, at the time of verifying a certain level, in order to prevent a cell written to a level higher than this level from being completely written, the signals REGA to REGD are set to the H level and the bit line read to the TDC is read. This is because it is necessary to forcibly set the potential at L level, that is, write incomplete.

  On the other hand, the number of refreshes can be reduced by connecting a TDC discharge circuit as shown by a broken line in FIG. This discharge circuit is composed of N-channel MOS transistors 62a and 62b connected in series between a node supplied with power supply VPRE or Vss and a node N3, for example. The gate of the transistor 62a is connected to the node N1a, and the signal REGP is supplied to the gate of the transistor 62b. When the node N1a of the PDC is at a high level and the signal REGP is at a high level, the charge of the TDC can be discharged.

  With such a configuration, even if the data of LDDC0, LDDC1, and LDDC2 is in the PDC, the TDC can be discharged by setting the signal REGP to the H level. Thereafter, the signal VPRE is set to H level, and the LPDC or LDDCQ signal REG is set to H level. Thus, in the case of non-writing originally, the TDC is forcibly set to “H level”, the PDC data is transferred to any one of DDCA to B, and then the TDC data is transferred to the PDC. For this reason, in the case of non-writing originally, the PDC becomes “H level”. In the case of writing, when writing is performed at a level higher than the verify level, the PDC becomes “L level”, and verification can be prevented from being forcibly completed. Therefore, the PDC can be set in a state where the verification is not forcibly completed by setting the signal REGP to the high level even if the data of the PDC is not LDDCQ or LDCCP. For this reason, the number of refreshes can be reduced.

  In the write operation, when a lower verify level is not used, one of DDCA to DDCD can be deleted.

Furthermore, this reference example, FIG. 12, FIG. 14, while writing the adjacent cell in the write sequence shown in FIG. 16, is written first stage, second stage, the data input of the third stage and 3 times. However, when the coupling capacity between the floating gates of the adjacent cells is small, it is possible to continue writing in the first stage, the second stage, and the third stage to the selected cell without writing the adjacent cells. . In this case, in order to continue writing, for example, the 16-level level is written lower than the original verify level in the second stage. All the PDCs are in the write completion state, but if the data of DDC0, DDC1, DDC2, and SDC are left, the next third stage write data can be reproduced. In this way, the third stage data load can be omitted. Furthermore, writing in the first stage or the second stage can be omitted, or writing in the first stage and the second stage can be omitted and only writing in the third stage can be performed.

  FIG. 46 shows the differences between the verify levels shown in FIG. 13 (f), FIG. 15, and FIG. As shown in FIG. 47, the necessary data retention margin increases as the distance from the neutral threshold voltage increases. For this reason, the difference shown in FIG. 46 increases as the distance from the neutral threshold voltage increases. The difference between the level 0 and the level 1 is wider than the difference between the other levels. This is because the distribution of the level 0 is, for example, the second stage having a large step size of dvpgm 0.3V shown in FIG. This is because the writing is performed at. In addition, a margin is set so that the distribution of the threshold voltage of level 0 does not reach the distribution of the threshold voltage of level 1 even when the distribution of the threshold voltage of the level 0 is widened due to erroneous writing while another level is being written.

  However, in a normal write sequence, the lower threshold level write is completed prior to the upper threshold level write. For this reason, while writing the upper threshold level, the threshold distribution of the lower threshold level that has already been written may spread due to erroneous writing. When the threshold distribution is greatly expanded, as shown in FIG. 46, a correction value is added to the difference to obtain a corrected difference. Further, since the lower threshold level is more likely to be erroneously written, the correction value corresponding to the lower threshold level can be set to a larger value.

In addition, in order to suppress this problem, in this reference example , 16th to 15th levels were written simultaneously. However, it is also possible to write only the upper level 8 to F, or the level C to F, or the level E, F, or level F among the 16 levels to 15 levels, and then write the remaining levels. .

In this reference example, FIG. 12, FIG. 14, as shown in FIG. 16 was written from the source side of the cell in a NAND cell in the order of the drain-side cells. However, as shown by the solid line (a) in FIG. 48 (a), when the drain side cells (WL1 to 31) are written after writing to the source side cell (for example, the cell connected to WL0) verify level, the drain side A side cell (for example, a cell connected to WL31, indicated by a solid line (c) in FIG. 48A) is written to the verify level. However, the threshold distribution of the source side cell (for example, a cell connected to WL0, indicated by a broken line (b) in FIG. 48A) becomes high. For this reason, there is a problem that the read level becomes close to the next level and cannot be read correctly.

  Therefore, when writing a cell on the source side, as shown by a solid line (a) in FIG. 48 (b), the verify level is slightly lowered in advance from the verify level shown in FIG. 48 (a). After this, when the drain side cells (WL1 to 31) are written, the threshold distribution of the source side cell (for example, a cell connected to WL0, shown by a broken line (b) in FIG. 48B) is the next level. Lower than the lead level.

  By doing so, the threshold distribution of the source side cell (shown by a broken line (b) in FIG. 48B) and the threshold distribution of the drain side cell (shown by a solid line (c) in FIG. 48A) are obtained. Can be set to almost the same level. The shift amount at which the threshold value of the source side cell shifts high gradually decreases from the source side cell toward the drain side cell. For this reason, the magnitude for lowering the verify level may be gradually reduced from the source side toward the drain side. If it is difficult to reduce the size gradually, for example, WL0-7 may be set as one set, WL8-15 may be set as one set, WL16-23 may be set as one set, and WL24-31 may be set as one set (the verify level is not lowered). Is possible.

(Erase operation)
The erase operation is performed in units of blocks indicated by broken lines in FIG. Further, two bit lines (BLie, BLio) connected to the data storage circuit are performed simultaneously. After erasing, the threshold value of the cell becomes level 0 (negative potential) as shown in FIGS. In the case of an EASB (Erased Area Self Boost) writing method, it is necessary to make the threshold voltage of the erase cell shallow.

  FIG. 34A shows an EASB writing method. In this writing method, writing is always performed from the memory cell on the source side. First, the bit line is set to Vss for writing and Vdd for non-writing. Next, for example, when writing a cell connected to the word line WL7, the word lines WL0 to WL4 are Vpass, the word line WL5 is Vss, the word line WL6 is Vdd, an intermediate potential or Vpass, and the word line WL7 is Vpgm. WL8 to 31 are set to Vpass, respectively. At this time, in the case of writing, the gate of the word line WL7 becomes Vpgm and the channel becomes Vss, and writing is performed.

  However, in general, in the case of non-writing, the channel is boosted to, for example, Vpass / 2. However, if the number of written cells is large, the channel is hardly boosted. For this reason, erroneous writing is likely to occur. However, in the case of the EASB writing method, writing is always performed from the source side. Therefore, when the word line WL5 is boosted to 0V, the cells connected to the word lines WL4 to WL31 are erased, so that the channel is boosted and cannot be written.

  As described above, it is necessary to prevent the boosted charge from moving to the already written cell. However, when the cell connected to the word line WL5 is in the erased state and the threshold voltage is deep, it is not turned off. . Therefore, it is necessary to make the threshold voltage of the erase cell shallow.

In this reference example , at the time of writing in the second stage, writing is performed on a cell of level 0 to reduce the threshold voltage. For this reason, as will be described below, after erasing, it is not necessary to perform writing in which a cell having a deep threshold voltage is shallowed in units of blocks. However, when the threshold voltage of the adjacent cell moves from a low level to a high level in the first stage writing or the like, the threshold voltage greatly fluctuates. For this reason, there is a problem that the threshold voltage of the already written memory cell fluctuates due to the coupling capacitance. Therefore, after the erase operation, all word lines in the block can be selected, and program and program verify read can be performed to write the threshold voltage after erasing each cell to a certain level as shown in FIG. The program and program verify read operations at this time may be performed in exactly the same manner as normal program and program verify read with all word lines selected.

  FIG. 34 (b) is a modification of FIG. 34 (a). The word lines WL6 and WL5 of the two memory cells on the source side from the selected word line WL7 are set to Vdd, intermediate potential, or Vpass, and the third word line WL4 is set to Vss and turned off. Other word lines are set to Vpass or intermediate potential. In this case, in the second stage, writing is not performed on the level 0 cell, and writing is performed on the level 0 cell at the time of writing in the third stage.

(Read operation)
FIG. 35 shows the threshold voltage distribution after 16-level writing and the data allocation in each page.

  When reading the data of the lower page, the read operation is performed at level 8 of the read and verify level (R & V Level). Then, when the cell is turned on and the bit line potential becomes L level, the output data is H level (“1”). When the cell is turned off and the bit line potential becomes H level, the output data is L level (“0”).

  When reading the data of the upper page, the read operation is performed at level C and level 4. Therefore, two sequences need to be read.

  When reading the data of the higher page, the read operation may be performed at level E, level A, level 6 and level 2. Therefore, it is necessary to read four sequences.

  When reading the top page data, the read operation is performed at level F, level D, level B, level 9, level 7, level 5, level 3, and level 1. Therefore, it is necessary to read out 8 sequences.

  FIG. 37 shows the waveforms of the word lines and bit lines in one sequence of read operations, and FIG. 38 shows the read algorithm.

  The first read operation will be described. When a read address and a read command are input (S31), the control signal and control voltage generation circuit 7 supplies the voltage Vfix () to the well, source line, unselected bit line, and select gate of the unselected block of the selected memory cell. For example, 1.6V) is supplied (S32). A potential of level 8 is supplied to the selected word line in the case of the lower page, a potential of level C is supplied in the case of the upper page, a potential of level E is supplied in the case of the higher page, and level F in the case of the top page. Is supplied (S33). When the potential of these word lines is lower than the potential Vfix of the well and source lines, a negative potential is apparently applied to the gate of the cell. At the same time, Vread is supplied to the non-selected word lines of the selected block, and a predetermined voltage is supplied to the select gate SGD of the selected block.

  Next, the signal VPRE of the data storage circuit 10 shown in FIG. 1 is set to Vdd (for example, 2.5 V), the signal BLPRE is set to Vsg (Vdd + Vth), and the signal BLCLAMP is temporarily set to, for example, (0.6 V + Vth) + Vfix. Then, the bit line is precharged to 0.6V + Vfix = 2.2V, for example. Next, a predetermined voltage is supplied to the select line SGS on the source side of the cell. Since the well and the source are at Vfix, when the cell is turned off, the potential of the bit line remains at H level (eg, 2.2 V). When the cell is turned on, the potential of the bit line is discharged and the source And the same potential, that is, Vfix (for example, 1.6 V).

  Thereafter, Vsg (Vdd + Vth) is once supplied to the signal BLPRE, and the node N3 of the TDC is precharged to Vdd. Thereafter, the signal BOOST is changed from L level to H level, and the potential of the node N3 of TDC is set to αVdd (for example, α = 1.7, αVdd = 4.25V).

  Here, the signal BLCLAMP is set to, for example, (0.45 V + Vth) + Vfix. When the bit line potential is lower than 0.45V + Vfix, the node N3 of the TDC becomes L level (Vfix (eg, 1.6V)), and when the bit line potential is higher than 0.45V, it remains at H level (αVdd ( For example, 4.25V)). Next, after the signal BLCLAMP is set to Vtr (for example, 0.1 V + Vth), the signal BOOST is changed from H level to L level. Here, when the TDC is at the L level, the potential of the node N3 falls from Vfix (eg, 1.6 V), but since the signal BLCLAMP is set to Vtr (eg, 0.1 V + Vth), it does not fall below 0.1 V. . When TDC is at the H level, the potential of the node N3 changes from (αVdd (eg, 4.25 V)) to Vdd.

  Here, the signal BLC1 is set to Vsg (Vdd + Vth), and the potential of the TDC is read into the PDC. Therefore, when the threshold voltage of the cell is lower than 8 levels, PDC is at L level, and when it is higher, PDC is at H level and reading is performed.

  The lower page is read (S33) only once. Therefore, after the read sequence, the process proceeds to step S41 (dt_p2s sequence). In this step 41, the data of the PDC is moved to the SDC, and the data of the SDC is transferred near the output buffer.

  Reading the upper page (S34) requires two read sequences, and reading the higher page requires four read sequences (S33 to S36). Further, the read of the top page requires eight read sequences (S33 to S40). For this reason, after the read sequence, the sequence is executed once for the upper page, three times for the higher page, and seven times (read add described later) for the top page (S34 to S40). Thereafter, the process proceeds to step S41. In step S41, the PDC data is transferred to the SDC, and the SDC data is transferred near the output buffer.

(Read Add)
The second and subsequent read operations are the same as the first read operation, and the following potential is supplied to the selected word line.

2nd upper page: Level 4 potential,
Second higher page: level A potential,
Third page of higher page: level 6 potential,
4th higher page: level 2 potential,
Second time on top page: Level D potential,
Third time on top page: Level B potential,
Top page 4th: Level 9 potential,
Top page 5th: Level 7 potential,
6th top page: Level 5 potential
Top page 7th: Level 3 potential,
Top page 8th: Level 1 potential.

  After the potential of the selected word line is set as described above, the bit line is precharged and discharged, and the bit line potential is transferred to the TDC. In the first read, the signal BLC1 is set to Vsg (Vdd + Vth), and the potential of the TDC is read into the PDC. On the other hand, in the case of the second read, before reading into the PDC, one of the signals DTGA to DTGD is set to the H level and the signal VPRE is set to the L level. When the PDC data is at the H level, the TDC is forcibly set to the L level, the signal BLC1 is set to Vsg (Vdd + Vth), and the potential of the TDC is read into the PDC. In the read add, the higher page performs the same operation three times, and the top page performs the same operation seven times. The data shown in FIG. 35 indicates data read into the PDC.

According to the first reference example , when 4-bit, 16-value data is stored in a memory cell, DDCA, DDCB, DDCC, DDCD configured by four dynamic data caches in a data storage circuit, and a static data cache By providing the PDC and SDC configured as described above, these data can be written into the memory cell. Therefore, 16-value data can be written by a latch circuit that is smaller than the number of threshold voltages set in the memory cell. Therefore, the area of the data storage circuit can be reduced.

  Moreover, the four data are stored by four DDCA to DDCD. Since each of DDCA to DDCD is composed of three transistors, the circuit configuration is simpler than SDC and PDC composed of flip-flop circuits. Therefore, it is possible to reduce the area of the data storage circuit by using many dynamic data caches.

  Further, in the middle of writing, writing with a low threshold voltage is completed. In this case, any one of the PDC, SDC, DDCA to DDCD is sequentially opened so that the next data can be input. Therefore, since input data can be prefetched, high speed writing becomes possible.

In addition, when a plurality of DDCs are used, it is necessary to refresh the data stored in these DDCs. In general, the number of refreshes is required by the number of DDCs. In addition, the refresh operation for one DDC requires two operations of DDC → PDC and PDC → DDC. In the case of a data storage circuit using four DDCs, normally, eight refresh operations are required. However, in the case of the first reference example , the DDC control circuit 7-1 is provided, and each time the DDC is refreshed, the definition of the data stored in each DDC is changed, so that the refresh operation is suppressed to five times. Yes. Therefore, according to the first reference example , the writing time can be shortened.

  Further, the DDC control circuit 7-1 transfers data input in an arbitrary order to DDCA to DDCD in a preset order, and then defines the data of DDCA to DDCD according to the input page address. Has changed. For this reason, it is possible to reliably control the relationship between the data input in an arbitrary order and DDCA to DDCD and PDC.

(Second reference example )
In the first reference example , as shown in FIGS. 36 and 37, one level of verify operation is performed by two reads. However, it is not limited to this.

Figure 39 shows a second embodiment. As shown in FIG. 39, after precharging the bit line BL, a lower verify voltage VL is set to the word line WL, and the first verify operation is performed. Subsequently, the original verify voltage V is set to the word line WL, and a second verify operation is performed.

According to the second reference example , the bit line BL is precharged once, and in this state, the first verify operation by the lower verify voltage and the second verify operation by the original verify voltage are continuously performed. Yes. Therefore, the charging time of the bit line can be shortened, and the program operation can be speeded up as compared with the case where the bit line is precharged for each of the first and second verify operations.

FIG. 40 shows an example of the read operation according to the second reference example . As shown in FIG. 40, after precharging the bit line BL, a lower read voltage RL is supplied to the word line WL, and a first read operation as a dummy read is performed. Subsequently, the original read voltage R may be supplied to the word line WL, and the second read operation with the original read voltage R may be performed. The dummy read is performed for the same operation as the verify operation.

(Third reference example )
FIG. 41 shows a third reference example . FIG. 41 shows an example in which, for example, four levels are continuously read after the bit line is precharged. That is, after the bit line BL is precharged, a plurality of different lower verify voltages AVL, BVL, CVL, and DVL are sequentially supplied to the word line WL, and are continuously decreased by these verify voltages AVL, BVL, CVL, and DVL. First to fourth verify operations are performed. After that, after precharging the bit line BL again, a plurality of different original verify voltages AV, BV, CV, DV are sequentially supplied to the word line WL, and the original verify voltages AV, BV, CV, DV are supplied. The original first to fourth verify operations are performed.

According to the third reference example , verification is performed four times for one bit line precharge. Therefore, the number of times of precharging the bit line can be reduced, and the writing speed of quaternary data can be increased.

FIG. 42 shows an example of the read operation according to the third reference example . The read operation is summarized at the same level as the level summarized in verification. That is, the second stage performs 16-level verification of levels 0 to F, and the third stage performs 15-level verification of levels 1 to F. Therefore, for example, level 0 is only 1 level, and verify and read are performed as shown in FIG. 39, and levels 1 to 3 are verified and read continuously for 3 levels. Further, levels 4 to 7 are verified and read continuously for 3 levels, and levels 8 to B are verified and read continuously for 4 levels. Further, the levels C to F are verified and read continuously for four levels.

  Thus, by verifying and reading a plurality of levels collectively, it is possible to speed up the verifying and reading operations.

(Fourth reference example )
In the first to third reference examples , the signal BLC1 = Vsg is set to the non-write bit line and the bit line is charged to Vdd by setting the signal BLCRL = Vdd to the unselected bit line at the time of programming. However, it is also possible to set the signal BIASo (or BIASe) to VLIMIT (VLIMIT ≦ Vdd + Vth), set the signal BLSo (or BLSe) to VLIMIT, and set the bit line potential to be lower than Vdd.

  Thus, by setting the potential of the non-selected bit line lower than Vdd at the time of programming, the amount of charge of the bit line at the time of programming can be suppressed, the peak current at the time of charging can be suppressed, and the current consumption is reduced Is possible.

(Fifth embodiment)
In the case of the first embodiment, as shown in FIG. 25E, 16 levels of writing require a total of six data caches in one data storage circuit. That is, a necessary SDC, LDDC2, LDDC1, LDDC0 for distinguishing LDDCQ, 16-bit data for distinguishing PDC for distinguishing the write / non-write, whether it exceeds a lower verify level It was. However, the level 0 is the originally erased cell, if the program is not required for this level 0, whether beyond the lower verify level is distinguished by PDC, the 15-bit data SDC, LDDC2, LDDC1, LDDC0 Differentiate by. Further, at the time of non-writing, all of SDC, LDDC2, LDDC1, and LDDC0 are set to “0”.

FIG. 43 shows the relationship between the data cache and the data according to the first embodiment.

  As shown in FIG. 43, data is set, and at the time of programming, the signal BIASo (or BIASe) corresponding to the unselected bit line is set to Vdd + Vth (or <Vdd + Vth), and Vdd is supplied to the bit line. In this state, when only the selected bit line is in a floating state and any of LDDC2, LDDC1, and LDDC0 is “1”, the signal VPRE is set to Vss, the signal REG is set to Vdd, Assume that SDC is at L level. Then, the bit lines corresponding to other than the non-write bit lines become Vss and are in a write state.

On the other hand, when SDC is at the H level and all of LDDC2, LDDC1, and LDDC0 are “0”, the bit line remains floating. However, by charging the non-selected bit line to Vdd, the potential of the bit line becomes close to Vdd by coupling, and writing is not selected. Thereafter, after setting the signal BLCLAMP to Vss, the signal VPRE is set to Vss, the signal BLPRE is set to Vdd, the signal TDC is set to Vss, the signal VPRE is set to Vdd, the signal REGi is set to H level, and LDDCi (i is 0 to 2). move data from any) to TDC of copies signal DTGi H level, the data stored in the PDC (indicating the distinction whether it exceeds the lower verify level) in LDDCi. In this state, after the signal BLC1 is set to the H level and the TDC data is moved to the PDC, the signal VPRE is set to Vdd and the signal REGi is set to the intermediate potential. Then, when a lower verify is passed, an intermediate potential is supplied to the bit line and writing is performed only slightly.

According to the first embodiment, if the program of level 0 is not required, whether beyond the lower verify level is distinguished by PDC, the 15 bits of data and distinguished by SDC, LDDC2, LDDC1, LDDC0 Yes. For this reason, the number of data caches can be reduced by one.

FIG. 44 shows a modification of the first embodiment and shows a case of writing at 7 levels. For 7 levels, 4 data caches are required. That is, whether or not the lower verify level is exceeded is distinguished by PDC, and 7-bit data is distinguished by SDC, LDDC1, and LDDC0. At the time of non-writing, SDC is H level, LDDC1 and LDDC0 are all set to “0”, and PDC is set to 1.

FIG. 45 shows another modification of the first embodiment and shows a case of three-level writing. For 3 levels, 3 data caches are required. That is, whether more than the lower verify level is distinguished by PDC, the data of 3 bits distinguishes the SDC, LDDC0. At the time of non-writing, SDC is H level, LDDC1 and LDDC0 are all set to “0”, and PDC is set to 1.

Furthermore, after passing the lower verification, the intermediate potential is supplied to the bit line if not written to perform a little seen write, need to store data for distinguishing whether it exceeds a lower verify level There is no. In this case, it is possible to further reduce the data cache one by one from the examples shown in FIGS. 43, 44, and 45.

In addition, the present invention is not limited to the above you facilities embodiment, various modifications may be a range not changing the gist of the invention is a matter of course.

1 is a circuit diagram showing an example of a data storage circuit according to the present invention. 1 is a diagram showing a schematic configuration of a NAND flash memory according to the present invention. FIG. 3 is a circuit diagram showing a configuration of a memory cell array and a bit line control circuit shown in FIG. 2. 4A is a cross-sectional view showing a memory cell, and FIG. 4B is a cross-sectional view showing a selection transistor. Sectional drawing which shows NAND type flash memory. The figure which shows the example of the voltage supplied to each area | region shown in FIG. FIG. 3 is a timing chart showing an address input cycle of the memory shown in FIG. 2. The figure which shows assignment of an input cycle and an address. The schematic block diagram which shows the relationship between a memory cell array (plane 0, 1) and a block. The figure which shows the relationship between the memory cell data and the threshold value of a memory cell. The figure which shows the relationship between the memory cell data and the threshold value of a memory cell. The figure which shows the write-in order with respect to the memory cell in a 1st reference example . FIG. 13 is a diagram showing transition of the threshold voltage of the memory cell accompanying the write operation. The figure which shows the 1st modification of FIG. The figure which shows the 1st modification of FIG. The figure which shows the 2nd modification of FIG. The figure which shows the 2nd modification of FIG. FIG. 9 is a timing chart showing a write operation in a third stage. FIG. 19A to FIG. 19K are diagrams showing the relationship between commands and data in the first stage to the third stage. FIG. 3 is a circuit diagram showing an example of a DDC control circuit shown in FIG. 2. The block diagram which shows an example of the converter shown in FIG. The block diagram which shows an example of the other converter shown in FIG. The figure which shows an example of refresh operation. The figure which shows a write-in sequence. FIGS. 25A to 25E are diagrams showing the relationship between input data and write levels in 16-value, 8-value, 4-value, and 2-value associated with the write sequence shown in FIG. FIGS. 26A to 26D are diagrams for explaining a program operation and a refresh operation. The figure which shows the program verify operation | movement of a 1st stage. The figure which shows the program verify operation | movement of a 2nd stage. The figure which shows the program verify operation | movement of a 3rd stage. The figure which shows the subroutine for detecting whether the write bit to each level exists. 31 (a) to 31 (c) are diagrams showing level 1 and level 2 verification in the third stage shown in FIG. FIGS. 32A and 32B are diagrams showing the relationship between the write level at the time of verifying level B in the third stage and the data stored in each data cache. FIGS. 33A to 33C are diagrams showing a data setting sequence for the data cache. FIG. 34 (a) is a diagram showing an EASB writing method, and FIG. 34 (b) is a diagram showing a modification of FIG. 34 (a). The figure which shows distribution of the threshold voltage after 16 level writing, and allocation of the data in each page. The wave form diagram which shows the electric potential of the word line in one level in a program verify, and a bit line. FIG. 6 is a waveform diagram showing potentials of word lines and bit lines in one sequence read operation. The figure which shows the algorithm of read-out operation | movement. FIG. 10 is a waveform diagram showing a potential of a verify operation according to a second reference example . The wave form diagram which shows the electric potential of the read operation concerning the 2nd reference example . FIG. 10 is a waveform diagram showing a potential of a verify operation according to a third reference example . The wave form diagram which shows the electric potential of the read operation concerning a 4th reference example . The figure which concerns on 1st Embodiment and shows the relationship between the data cache and data for reducing a data cache. The figure which concerns on the modification of 1st Embodiment, and shows the relationship between the data cache and data for reducing a data cache. The figure which concerns on another modification of 1st Embodiment, and shows the relationship between the data cache and data for reducing a data cache. The figure which concerns on the 1st reference example and shows the difference of a verify level. The figure which shows the relationship between a neutral threshold voltage and a required data retention margin concerning a 1st reference example . 48A and 48B are diagrams showing a modification of the first reference example . The schematic block diagram which shows the modification of a memory cell array.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Bit line control circuit, 5 ... Data input / output terminal, 7 ... Control signal and control voltage generation circuit, 8 ... Control signal input terminal, 7-1 ... Dynamic data cache (DDC) control circuit, 7a ˜7e... Converter, 7a-1 to 7a-4... Flip-flop circuit, 7a-6.

Claims (7)

A memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix;
A first control circuit for controlling the potential of the word line and the bit line;
A data storage circuit for storing write data for a write operation that is connected to the bit line and sets a threshold of 2 ^k (k is a natural number of 3 or more) in the memory cells in the memory cell array; The data storage circuit is composed of k latch circuits each storing at least 1-bit data,
The data storage circuit includes at least one static latch circuit;
Having a plurality of dynamic latch circuits;
The at least one static latch circuit is externally connected, and the at least one static latch circuit and the plurality of dynamic latch circuits receive externally input write data and receive internal write data corresponding to a write operation. A semiconductor memory device characterized by latching. Move one data among the plurality of the dynamic latch circuit to said static latch circuit, a second control for refreshing the data by moving the data of the static latch circuit to one of said plurality of dynamic latch circuits The semiconductor memory device according to claim 1, further comprising a circuit.   2. The semiconductor memory device according to claim 1, wherein the at least one static latch circuit is connected to the outside. The data storage circuit includes at least first and second static latch circuits;
Having a plurality of dynamic latch circuits;
Move one data among the plurality of the dynamic latch circuit in the first static latch circuit, data by moving the data of the first static latch circuit in one of the plurality of dynamic latch circuits A second control circuit for refreshing;
2. The semiconductor memory device according to claim 1, wherein the second static latch circuit is connected to the outside. By the write operation, the threshold voltage of the memory cell, the first threshold voltage is set to the threshold voltage of the second threshold voltage to the second ^k, wherein at least one static latch circuit and the plurality of dynamic latch circuit , Constituting a first latch circuit, a second latch circuit to a k-th latch circuit each storing 1-bit data,
The first latch circuit distinguishes between ^{first to} second ^(k−1) threshold voltages or second ^(k−1) +1 to second ^k threshold voltages;
The second latch circuit has a second ^(k−1) +1 to a second ^(k−1) +2 ^(k−2) threshold voltage or a second ^(k−1) +2 ^(k−2) +1 threshold. Distinguish voltage,
2. The semiconductor memory device according to claim 1, wherein the k-th latch circuit stores data for distinguishing a 2 ^k −1 threshold voltage or a 2 ^k threshold voltage. The at least one static latch circuit and the plurality of dynamic latch circuits constitute a first latch circuit, a second latch circuit to a kth latch circuit, each storing 1-bit data,
In the middle of the write operation, when writing to the first to second ^(k−1) threshold voltages is completed, the first latch circuit stores the next write data, and the second ^{(k− 1) When} writing to the threshold voltages from +1 to the second ^(k−1) +2 ^(k−2) is completed, the second latch circuit stores the next write data, and the second ^k −1 2. The semiconductor memory device according to claim 1, wherein when the writing to the threshold voltage is completed, the kth latch circuit stores the next write data. 2. The semiconductor memory according to claim 1, wherein when a plurality of bits of data are stored as the first page to the k-th page, if the address inputted from the outside is the address of the k-page, 2 ^k level writing is performed. apparatus.

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