JP3201838B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundant structure including a spare memory cell array for relieving a defective bit line of a real memory cell array.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a conventional semiconductor memory device. In this figure, 1 is a row address buffer, 2 is a row decoder, 3 is a real memory cell array, 4 is a first spare memory cell array, 5 is a second spare memory cell array, 6 is an mth spare memory cell array, 7 Is a column address buffer, 8 is a column decoder, 9 is a real cell Y gate, 10 is a first spare cell Y gate, 11 is a second spare cell Y gate, 12 is an mth spare cell Y gate, 13 is a spare decoder, 1
4 is a sense amplifier. (Normal Read Operation) In a read operation when spare replacement is not performed, first, a row address signal fetched from the row address buffer 1 is decoded by a row decoder 2, and the real memory cell array 3, the first spare The word lines of the memory cell array 4, the second spare memory cell array 5, and the m-th spare memory cell array 6 are selected. Next, the column address signal fetched from the column address buffer 7 is decoded by the column decoder 8, and a real selection signal SR _SEL for selecting one of the real cell Y gates 9 is output according to the decoding result. As a result, one gate in the real cell Y gate 9 is opened, and one bit line of the real memory cell array 3 and the sense amplifier 14 are opened.
Is connected, the data of one memory cell (one memory cell in the real memory cell array 3) located at the intersection of the selected word line and the selected bit line is read from the sense amplifier 14. (Read Operation for Spare Replacement) Spare Decoder 1
Reference numeral 3 has a function of determining whether the column address signal matches a preset redundant address. In the case of a non-coincidence determination, the operation of the column decoder 8 is permitted to perform the above-described normal read operation.
A signal S _INH for inhibiting the operation of the column decoder 8 is output, and at the same time, a signal SS _SEL for selecting any one of the Y gate 10 for the first spare cell, the Y gate 11 for the second spare cell, and the Y gate 12 for the m-th spare cell is output. Output.

[0003] Thereby, the real memory cell array 3
Of the first spare memory cell array 4, the second spare memory cell array 5, or the m-th spare memory cell array 6 as a result of being connected to the sense amplifier 14, Data of one of the memory cells is read from the sense amplifier 14.

[0004]

However, in such a conventional semiconductor memory device, the Y gate 9 for the real cell and the Y gates 10 to 12 for the first to m-th spare cells are provided.
, A dedicated selection signal (SR _SEL , SS
_SEL ), for example, when a large number of spare memory cell arrays are mounted, the signal wiring around the Y gate becomes congested in proportion to the number of mounted spare memory cell arrays.
There was a problem that the chip layout became difficult. [Object] Therefore, the present invention simplifies the signal wiring for selecting the Y gate, thereby avoiding the congestion of the signal wiring around the Y gate even when a large number of spare memory cell arrays are mounted, and simplifying the chip layout. It is an object of the present invention to provide a simple semiconductor memory device.

[0005]

Means for Solving the Problems The present invention, the principle diagram to achieve the above object, as shown in FIG. 1, a plurality corresponding to the plurality of address <br/> less signal (B ₀ ~B _n) have a bit line
A spare memory having a real memory cell array 22 and at least one bit line corresponding to a specific address signal (for example, _Bn ) overlapping with any one of the plurality of address signals. A cell array 23 , 24 , 25 ; a judging means 32 for judging a match between a column address signal and a preset redundant address signal; and if the judging results of the judging means 32 do not match, according to the decoding result of the column address signal. While generating a signal designating one of the bit lines of the real memory cell array 22 ,
Signal generation means 27 for generating a signal for designating the bit lines of spare memory cell arrays 23 , 24 , 25 ; real memory cell array 22 and spare memory cell array 2
Bit line selecting means 2 for selecting a bit line designated by signal generating means 27 among all bit lines 3, 24 and 25
8 , 29 , 30, 31 and the determination result of the determination means 32 do not match, the selected bit line of the real memory cell array 22 is connected to the sense amplifier 34; Connection means 3 for connecting selected bit lines 23 , 24 , 25 to sense amplifier 34
3, includes a bit output from the signal generating means 27
Of the line designation signals SB _SEL ,
The corresponding bit line designation signal is selected by the common wiring.
Input to selection means 28, 29, 30, 31
It is characterized by the following.

[0006]

According to the present invention, a common signal is used for each of the Y gates (bit line selecting means) of the real memory cell array and the spare memory cell array. That is, for the Y gate of the real memory cell array, B ₀ to B
A plurality of signals corresponding to each address signal up to _n are supplied, and one signal corresponding to a specific address signal (B _{n in} FIG. 1) is supplied to the Y gate of the spare memory cell array. In this case, the signal corresponding to B _n is shared.

Therefore, one set of signal wiring is laid between the signal generating means and the bit line selecting means, and the signal wiring for Y gate selection can be simplified. As a result, many spares
Even when a memory cell array is mounted, congestion of signal wiring around the Y gate can be avoided, and a semiconductor memory device with an easy chip layout can be provided.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 6 are views showing one embodiment of the semiconductor memory device according to the present invention. First, the configuration will be described. In FIG. 2, reference numeral 20 denotes a row address buffer for receiving a row address signal supplied from the outside, and reference numeral 21 denotes a word line selection signal SW _SEL for decoding the received row address signal.
A row decoder for generating, 22 a number of word lines (representatively WL _i) a number of the bit lines B ₀ .about.B _n as well as arranged in a cross shape, a memory cell at each intersection (representatively M _i)
, A real memory cell array 23, a first spare memory cell array, a second spare memory cell array 24, and an m-th spare memory cell array.

Here, the first spare memory cell array 2
3. The second spare memory cell array 24 and the m-th spare memory cell array 25 each have one bit line, and each bit line has a bit line identification number (B) of the real memory cell array 22. _{0 to} B _n ). For example, the first
“B ₀ ” is applied to the bit line of the spare memory cell array 23.
However, the bit line of the second spare memory cell array 24 has “B ₁ ”,..., The m-th spare memory cell array 25.
_Are given “B _n ”. Hereinafter, the suffix S is added to the identification number of the bit line of the spare memory cell array to distinguish it from the identification number of the bit line of the real memory cell array.

Reference numeral 26 denotes an externally applied column address.
Column address buffer to capture signals, 27 to capture
Decoded column address signal
(B ₀From B_nUp to) are included.
Bit line selection signal SB_SELColumn decoder that generates
(Signal generating means), 28 is the identification number (B₀From B _n
Up to) the rear including n switching gates
Y gate for cell (bit line selection means), 29
Fixed identification number (B₀One switching gate corresponding to)
Y gate for the first spare cell including the bit (bit line selection
, 30 are the specific identification numbers (B₁1) corresponding to
Y gate for second spare cell including switching gates
(Bit line selecting means), 31 is the specific identification number
(B_n) Including one switching gate corresponding to
It is a Y gate for m spare cells (bit line selecting means).

Here, the real cell Y gate 28, the first
Spare cells for Y gate 29, the second spare cell for Y gate 30 and the m spare cell for Y gate 31, the bit line selection signal SB _SEL from column decoder 27 is input. More specifically, all of the n signals included in the bit line selection signal SB _SEL are input to the real cell Y gate 28 and 1 corresponding to the identification number B ₀ in the real cell Y gate 28.
This signal is supplied to the first spare cell Y gate 29, and one signal corresponding to the identification number B ₁ is supplied to the second spare cell Y gate.
The gate 30 and one signal corresponding to the identification number _Bn are input to the m-th spare cell Y gate 31.

Reference numeral 32 denotes a spare decoder having a function as a judging means for comparing a redundant address as a predetermined value and a column address signal and judging coincidence / mismatch between the two. The output of the real Y gate (any one of the bit lines B _{0 to} B _n ) and the output of the spare Y gate (any one of the bit lines B _0S , B _1S , B _nS ) according to the / mismatch signal S _COMP A real / spare switching circuit (connecting means) for selecting alternatively, 34
Is a sense amplifier for reading data on the bit line selected by the real / spare switching circuit 33.

FIG. 3 shows a part of a column decoder 27 and a real cell Y gate 28, a first spare cell Y gate 29, a second spare cell Y gate 30, a spare decoder 32, a real / spare switching circuit 33 and a sense amplifier. FIG. 3 is a configuration diagram of a main part including a key 34; In this figure,
Ta~Tf the N-channel MOS transistor, INV is first decoding unit for 0th decoding portion for an inverter gate, DC ₀ is to specify the identification number B _0, DC ₁ is to specify the identification number B _1. The DC ₀ and DC ₁ using a NAND type decoder shown in FIG. That is, a plurality of N-channel MOS transistors Tg to Ti are connected in series, and an appropriate bit of a column address signal is applied to the gate of each transistor. If all the bits are at the H level, the node N between the load transistors Tj goes to the L level, and the output stage of the CMOS
Level signal (signal SB _{SE L (B0} corresponding to the identification number B ₀ if DC _0), the signal corresponding to the identification number B ₁ if DC ₁ SB _{SEL (B1))} is taken out. Here, the node N and N-channel MOS transistor Tk interposed between the ground G is (if S _B0, DC ₁ if DC ₀ S _B1) forced decode signal input from the spare decoder 32 is H level Is turned on at the time of (1) and the signal taken out from the output stage is forcibly set to the H level.

When the preset redundant address and the column address match, one of the forced decode signals S _B0 and S _B1 becomes H level in accordance with the column address signal at that time. In FIG. 3, for example, when the redundant address and the column address signal coincide with each other with the identification number B ₀ , S _B0 goes to H level and SB _{SEL (0)} goes to H level. T
a and the transistor Tc of the Y gate for the first spare cell is turned on, and the bit line B ₀ of the real memory cell array is turned on.
And the bit line B _{0S of} the first spare memory cell array is selected. At this time, the signal S from the spare decoder 32
_{Since COMP} is at the H level, the transistor Te of the real / spare switching circuit 33 is turned off, and the transistor T
As a result, the data on the bit line _{B0S of} the first spare memory cell array is read from the sense amplifier 34.

That is, according to the present embodiment, the column decoder 27, the real cell Y gate 28, and the first to m-th
Spare cells for can use a common selection signal SB _SEL between the Y gate 29 to 31, it is possible to greatly simplify the signal lines Y gate around. Therefore, even when the number of spare memory cell arrays mounted is increased, chip layout is easy, design flexibility can be improved, and design cost can be reduced.

FIG. 5 shows an example of application to a semiconductor memory device having a plurality of real memory cell arrays. Note that the same reference numerals are given to circuit elements common to the above-described embodiment. In FIG. 5, 40 is the Y gate of the first real memory cell array 41, 42 is the Y gate of the second real memory cell array 43, 44 is the Y gate of the first spare memory cell array 45, and 46 is the second spare memory. The Y gate of the cell array 47, 48 is a column decoder, 49 is a spare decoder, 50 is an upper decoder, and 51 is a selector.

In this example, a selection signal SB _SEL (n number of signal lines) from a column decoder 48 is commonly supplied to two Y decoders 40 and 42 for real memory cells, and a selection signal SR _SEL from a spare decoder 49 is provided. (1 signal line
Y) 4 for two spare memory cell arrays
4 and 46 are given in common. When the spare decoder 49 determines that the redundant address matches the column address, the signal S for inhibiting the column decoder 48 from performing a decoding operation is provided.
Outputs _INH and activates SR _SEL at the same time.
As a result, the bit lines of the spare memory cells 45 and 47 are connected to the selector 51 via the two spare memory cell array Y gates 44 and 46, and the data on one of the bit lines is read from the sense amplifier 34.

FIG. 6 shows an example of the upper decoder 50.
This is an example in which two NOR gates 50a to 50c and two inverter gates 50d and 50e are used. According to this example, the most significant bit A _MSB of the column address signal and the first spare memory cell selection signal S
Select signal SEL (and its inverted signal SELx) corresponding to the combination of R ₁ and second spare memory cell select signal SR ₂ is generated. That is, SEL is SR ₁
And SR ₂ are both at L level (that is, when the operation is not redundant), the most significant bit A of the column address signal
It becomes the _MSB and the logic goes to H level fixed when SR ₁ is at H level, an L level fixed when SR ₂ is at H level. Therefore, the selector 51 outputs the signal SEL
According to the logic of (and SELx), the outputs of the two real memory cell array Y gates 40 and 42 and the two spare memory cell array Y gates 44 and 46 are selectively switched to the sense amplifier. Connecting.

According to the configuration example shown in FIG.
Select signal SR for Y gates 44 and 46 for memory cell array
_{The SEL} can be shared, and the wiring layout around the Y gate can be simplified.

[0020]

According to the present invention, the signal wiring for selecting the Y gate can be simplified, and even when a large number of spare memory cell arrays are mounted, congestion of the signal wiring around the Y gate can be avoided. A semiconductor memory device having an easy layout can be provided.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is an overall configuration diagram of one embodiment.

FIG. 3 is a configuration diagram of a main part of one embodiment.

FIG. 4 is a configuration diagram of a decoder unit according to one embodiment.

FIG. 5 is another overall configuration diagram of the embodiment.

FIG. 6 is a configuration diagram of an upper decoder of FIG. 5;

FIG. 7 is an overall configuration diagram of a conventional example.

[Explanation of symbols]

22: Real memory cell array 23: First spare memory cell array (spare memory cell array) 24: Second spare memory cell array (spare memory cell array) 25: m-th spare memory cell array (spare memory cell array) 27: Column decoder (signal generation means) 28: Y gate for real cell (bit line selection means) 29: Y gate for first spare cell (bit line selection means) 30: Y gate for second spare cell (bit line selection means) 31: Y gate for m spare cell (bit line selection means) 32: spare decoder (judgment means) 33: real / spare switching circuit (connection means)

Claims (3)

(57) [Claims] 1. A real memory cell array having a plurality of bit lines corresponding to a plurality of address signals (B _{0 to} B _n ), and a specific address signal (eg, B _n ) overlapping any one of the plurality of address signals A spare memory cell array having at least one bit line corresponding to the above, a judgment means for judging a match between a column address signal and a preset redundant address signal, and a judgment result of the judgment means not matching In the case of (1), a signal designating one of the bit lines of the real memory cell array is generated in accordance with the decoding result of the column address signal. On the other hand, in the case of a match, a signal designating the bit line of the spare memory cell array is generated. a signal generating means for generating, in all the bit lines of the said real memory cell array spare memory cell array, the signal generation A bit line selection means for selecting a specified bit line by means, if the determination result of said determining means do not coincide, while connecting the selected bit line of the rear <br/> Le memory cell array to the sense amplifier , in the case of matching, and a connecting means for connecting the selected bit lines of the spare memory cell array to the sense amplifier, the bit line specifying signal output from said signal generating means
The bit line designation signal corresponding to the overlapping address signal
Are input to the bit line selecting means by a common wiring . 2. The method according to claim 1, wherein said bit line selecting means includes:
Each output of bit line selection transistor of memory cell array
And a first common node for connecting the spare memory cells.
Connect each output of the bit line selection transistor of the memory array
A second common node, and the first common node
Connecting the second common node via a separate transistor
A third common node, and when the judgment result of the judgment means does not match, the first common node
Connect between the common node and the third common node.
One of the individual transistors is turned on,
In the case of a match, the second common node and the third common node
Of the individual transistors to connect between
2. The device according to claim 1, wherein the other is turned on.
Semiconductor storage device. 3. A plurality of real memory cell arrays;
Multiple corresponding to each of multiple real memory cell arrays
Characterized by having a spare memory cell array of
The semiconductor memory device according to claim 2.