JP3199603B2 - Code size reduction microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor which executes data processing according to a program, and more particularly to a microprocessor which supports a reduction in the code size of a program.

[0002]

2. Description of the Related Art In recent years, products using microprocessors have been required to have higher and more advanced functions, and programs have become larger in scale. However, in products with a built-in microprocessor, the program is
Since it is necessary to implement M, the increase in the code size causes an increase in the capacity and the number of ROMs to be implemented, which hinders the development of low-cost products. Therefore, in the development of such products, it is desirable to reduce the code size as much as possible.

As a conventional technique for compressing the code size, there is a method of reducing the word length of each instruction executed by a microprocessor (for example, NEC V800).
Series, SH7000 series manufactured by Hitachi, Ltd.). These microprocessors have a data length handled at a time, that is, a data bus, an internal arithmetic unit, and a bit width of a register (hereinafter, referred to as a bit width).
It is called "calculation width". ) Has a set of instructions with word lengths smaller than. More specifically, it has an instruction consisting of 16 bits despite the fact that the operation width is 32 bits.

[0004] Such a technique makes it possible to configure an instruction that does not necessarily require 32 bits with 16 bits, or to configure a frequently used instruction with 16 bits, thereby eliminating useless bits constituting the instruction. As a result, even if the programs have the same contents, the entire code size is efficiently compressed.

[0005]

However, the above-mentioned prior art has the following problems. That is, even if an instruction having a word length smaller than the operation width is provided, the word length is the same as or an integer multiple of the bit width of the instruction decoder included in the microprocessor. For example,
If the bit width of the instruction decoder is 8 bits, the word length of the instruction is any of 8, 16, 24, 32,. For this reason, even if the word length of the instruction is reduced, it cannot be reduced in units smaller than 8 bits. For example, even when a numerical value that does not require 8 bits is specified, using 8 bits There was still a waste in code size because it had to be specified.

FIG. 10 is a diagram for explaining a bit configuration of an instruction in a conventional microprocessor.
Now, consider an instruction "add # 4, d0" of "add immediate value 4 to the value stored in register d0". The word length of this instruction is 8 bits for specifying the operation code "add # n, d0" and 8 bits for specifying the immediate value #n, that is, a total of 16 bits. Here, the immediate value “4” is specified using 8 bits, but for example, if an integer in the range of −8 to +7 is specified, 4 bits are sufficient.
That is, according to the conventional microprocessor, even if an instruction can be specified with a total of 12 bits, the instruction is constituted by 16 bits, so that there is still a waste in code size.

Accordingly, the present invention has been made in view of such a problem, and is not limited to an integral multiple of the bit width of an instruction decoder included in a microprocessor, and an instruction whose word length is efficiently reduced. It is an object of the present invention to provide a microprocessor having a set, thereby enabling creation of a program having the same content and a reduced code size.

[0008]

According to another aspect of the present invention, there is provided a microprocessor for decoding a coded instruction one by one, and a data processor based on a result of the decoding by the decoder. And an execution means for executing the instruction.
If the word length of the code that the decoder decodes at a time is a and the word length smaller than a is b, w = a + n
b (where, n is a positive integer including 0 and 1) is represented by the execution means, characterized by executing the instructions is an instruction and word length at least word length is a is (a + b) And

The microprocessor according to claim 2 is the microprocessor according to claim 1, wherein b is:
When a is one word, it is a half word. The microprocessor according to claim 3 is a contractor.
The microprocessor of claim 2, further comprising:
An instruction buffer that holds the read instruction and the
One word code to be read is divided into half words and stored.
The upper and lower decryption registers
Then, based on the result of decoding by the decoder,
The word length of the code to be transferred to the read register is halfword.
First determining means for determining whether there is a word or one word;
Half word is judged by the first judgment means
If the code stored in the lower decoding register is
Transfer to the upper decoding register and the instruction
Code of the next halfword to be transferred
To the lower decoding register.
It is characterized by that. The microprocessor according to claim 4 , further comprising: an instruction buffer for holding a prefetched instruction; a storage unit for storing a storage state of the instruction in a halfword unit in the instruction buffer; First determining means for determining whether the word length of the code to be decoded next is half word or one word based on the result of decoding by the decoder; Control means for controlling the instruction buffer so as to take in the code stored in the instruction buffer into the decoder and updating the storage state.

[0010] The microprocessor according to claim 5 is a contractor.
The microprocessor of claim 2, further comprising:
An instruction buffer for holding the read instruction and the instruction buffer
Stores the storage state of instructions in halfword units
Storage means for decoding, and a one-word code to be decoded by the decoder.
Upper-side decryption register that divides and stores the word in halfwords
And the lower-side decryption register, based on the storage state.
And decodes the code stored in the instruction buffer
Controlling the instruction buffer so that it takes in the register
Control means for updating the storage state to the
Next, based on the decryption result,
Whether the word length of the code to be transferred is halfword or one word
First judging means for judging whether or not the first
If the disconnection means determines that the word is a halfword,
Decoding the code stored in the high-order decoding register
The data is transferred to the register and stored in the instruction buffer.
The half-word code to be transferred next
Selecting means for transferring to the decoding register.
And The microprocessor according to claim 6 has the following features.
In 5 microprocessor described before Symbol instruction buffer, a second register Toka Rannahli holding a first register for holding the code of one word fetched to date, the code of one word fetched immediately before, the first One register is composed of an upper first register and a lower first register that hold a code of one word divided by half word, and the second register divides a code of one word by half word. And a lower register. The selecting means includes at least one register selected from the upper second register, the lower second register, and the lower decoding register. Upper-side selecting means for transferring the code held in the lower-side decoding register to at least the lower-side first register; Lower-side selection means for transferring a code held in one register selected from the upper-side second register and the lower-side second register to the lower-side decryption register; Second
A first state in which neither a register nor the lower second register holds a code, and a code is stored in the upper second register but a code is stored in the lower second register. A second state that is not stored and a storage state of one of a third state in which a code is held in the upper second register and the lower second register are stored.

According to a seventh aspect of the present invention, in the microprocessor according to the sixth aspect , the control means is configured such that a state stored in the storage means is a second state, and the first determination means Determines that the code length to be decoded next is one word,
The upper-side selecting means transfers the code held in the upper-side second register to the upper-side decoding register, and the lower-side selecting means transfers the code held in the lower-side first register to the lower-side first register. The selection means is controlled to transfer the data to a decoding register.

According to an eighth aspect of the present invention, in the microprocessor according to the sixth aspect , the control means is configured so that the state stored in the storage means is a third state and the first determination means If it is determined that the word length of the code to be decoded next is a halfword, the upper-side selecting means transfers the code held in the lower-side decoding register to the upper-side decoding register, The lower-side selector controls the selector to transfer the code held in the lower-side second register to the lower-side decryption register, and updates a state stored in the storage to a second state. It is characterized by doing.

According to a ninth aspect of the present invention, in the microprocessor according to the sixth aspect, the control means is configured so that a state stored in the storage means is a second state and the first determination means If it is determined that the word length of the code to be decoded next is a halfword, the upper-side selecting means transfers the code held in the lower-side decoding register to the upper-side decoding register, The lower-order selector controls the selector to transfer the code held in the upper-side second register to the lower-side decryption register, and updates a state stored in the storage to a third state. It is characterized by doing.

[0014] The microprocessor according to claim 10 is:
5. The microprocessor according to claim 4 , further comprising: a position on a memory where an instruction decoded by the decoder ends in a halfword based on a storage state stored in the storage means and a result of decoding by the decoder. To determine if it is a subroutine branch instruction placed in
When it is determined that the instruction is a subroutine branch instruction located at a memory location ending with a halfword, the execution unit stores a half address at a memory address corresponding to the location. The memory address obtained by adding the address corresponding to the word code is regarded as the return address from the subroutine, and branch processing to the subroutine is executed. The microprocessor according to claim 11.
Is the instruction buffer that holds the prefetched instruction, and the code
A decryptor for decrypting the converted instructions word by word,
One word code that is decoded by a reader is divided into half words
Upper and lower decoding registers that are divided and held
Based on the decryption result by the decryptor
The word length of the code to be transferred to the decoding register is half
First judgment to determine whether it is a word or one word
Means and a half word in the first determination means.
In the case of a disconnection, the code stored in the lower
Code to the upper decoding register, and
Halfword to be transferred next stored in the instruction buffer
Selecting means for transferring the code of
And characterized in that:

[0015]

According to the microprocessor of the first and second aspects of the present invention, the word length of the instruction to be decoded by the decoder is equal to the word length a of the code to be decoded by the decoder at one time. It is not limited to an integral multiple. Therefore, the word length of an instruction can be extended and defined in units of a word length b smaller than the word length a.

According to the microprocessor of the third aspect, in the microprocessor of the second aspect , b =
a / 2. Therefore, the word length w of the instruction is a,
1.5a, 2a, 2.5a, 3a,... That is, the word length of the instruction is a value added to the minimum word length a in units of half the word length a of the code decoded by the decoder at a time. This is compared with the instruction extended in units of the word length a, and the amount of information when specifying the code is the number of bits for specifying the upper half or the lower half of the word length a, that is, 1 Only an increase in bits is required.

According to the microprocessor of the third , fourth and eleventh aspects, the prefetched instruction is held in the instruction buffer, and the storage state of the instruction in the instruction buffer in half word units is recorded and updated. Further, it is determined whether the word length of the code to be decoded next is half word or one word. As a result, the position and word length of the code to be fetched next from the instruction buffer and to be decoded are determined.

According to the microprocessor of the fifth and sixth aspects, the fetched one-word code is divided in half word units and held in the instruction buffer, and the code selected from them is: The data is independently transferred to the decoding register in halfword units. The storage means stores the code storage state in the instruction buffer immediately before being transferred to the decoding register. As a result, the necessary codes held in the instruction buffer are transferred to the decoding register in half word units and decoded.

According to the microprocessor of claim 7, held over the first register and the second register 1
The word length code is transferred to the decoding register and executed. According to the microprocessor of claim 8, only the lower side halfword code held in the second register is transferred to the decode register and already decoded with the code of the decrypted halfword executed.

According to the microprocessor of the ninth aspect, only the half-word code held in the upper second register is transferred to the decoding register, and is decoded and executed together with the already decoded half-word code. Claim
According to the microprocessor described in 10, it is determined whether or not the instruction decoded by the decoder is a subroutine branch instruction placed at a memory position ending with a half word, and is determined to be the instruction. In this case, the branching process to the subroutine is executed by regarding the memory address obtained by adding the address corresponding to the half-word code to the memory address corresponding to the position as the return address from the subroutine.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. (Configuration of Microprocessor) FIG. 1 is a block diagram showing a configuration of a microprocessor according to the first embodiment of the present invention. This microprocessor is roughly composed of a data path block 200 and an instruction decoding block 100, and has a 16-bit external address bus 212 and an 8-bit external data bus 213. An external memory in which instructions to be executed are stored is connected to the microprocessor through these buses, though not shown.

The data path block 200 is a block for performing data transfer and calculation, and is a selector (SEL) 2.
01, register group 202, internal A bus 203, internal B bus 204, decoding counter (DECPC) 205, prefetch counter (PFC) 206, incrementer (INC) 207, arithmetic unit (ALU) 208, address buffer (ADB) 209, store data buffer (S
TB) 210 and load data buffer (LDB) 21
1 and their functions are not different from ordinary microprocessors.

The stack pointer (SP) 202a,
Decryption counter (DECPC) 205, prefetch counter (PFC) 206, incrementer (INC) 2
07 and an address buffer (ADB) 209 are components for holding address information, and have a 16-bit width.
On the other hand, the general-purpose register (REG) 202b, the store data buffer (STB) 210, and the load data buffer (LDB) 211 are components that hold data information, and have an 8-bit width. The data path block 200 and the instruction decoding block 100 are connected by an internal B bus 204.

FIG. 2 is a block diagram showing a detailed configuration of the instruction decoding block 100. Instruction decoding block 100
Is a block for decoding an instruction fetched from an external memory, and includes an instruction fetch buffer (IFB) 101, an instruction buffer (IB) 102, and an instruction selector (SI) 10.
3. Consists of an instruction register (IR) 104, a decoding unit 105, an execution unit 108, a control unit 109, and a storage unit 110.

The IFB 101 is a register for storing a one-word code fetched from an external memory through an external data bus. Here, the word refers to a unit for decoding an instruction, and is 8 words in the present microprocessor.
Bits, one byte. Therefore, in this embodiment,
At one address of the external memory specified by the 16-bit address bus, a code of one word, that is, one byte is placed.

An instruction refers to a logical group of instructions to the microprocessor, for example, "
add # 4, d0 "etc. On the other hand, the code refers to the whole or a part of the bit sequence in which the instruction is coded, for example, the bit sequence" 0c2 () corresponding to the instruction "add # 4, d0". hex) ”and its part“ 0 ”
c "and the like.

The IFB 101 stores an upper instruction fetch buffer (IFB) for storing upper 4 bits of a fetched code (hereinafter, a unit of 4 bits is referred to as “nibble”).
H) comprises a lower instruction fetch buffer (IFBL) 101b for storing one lower nibble 101a. The prefetch counter (PF) of the data path block 200
C) 206 holds the address of the external memory where the code fetched in the IFB 101 is located.

The IB 102 is a register for storing the code output from the IFB 101 and, like the IFB 101, comprises an upper instruction buffer (IBH) 102a and a lower instruction buffer (IBL) 102b. In addition, IFB1
01 and the code held in the IB 102 are output to the internal B bus 204 via a selector (not shown) and transferred to the data path block 200 in accordance with an instruction from the execution unit 108 described later.

An IR 104 is a register for storing a one-byte code to be decoded, and is an upper instruction register (IRH) 104 for storing a code for the upper one nibble.
a and a lower instruction register (IRL) 104b for storing the code of the lower 1 nibble. The decoding counter (DECPC) 205 of the data path block 200 includes
The address of the external memory where the code fetched in the IR 104 is stored.

The above IFB101, IB102 and IR
104 form a three-stage instruction pipeline;
A total of three bytes of code, including the two-byte code read ahead and the one-byte code decoded, are stored in this instruction pipeline. The SI 103 receives the IBH 102a, IBL
102b and one nibble code stored in one register selected from IRL 104b
An upper instruction selector (SIH) 103a for transferring to
IFBL101b, IBH102a and IBL102b
And a lower instruction selector (SIL) 103b for transferring the code of one nibble stored in one register selected from the IRL 104b to the IRL 104b, and these operate independently.

The storage unit 110 stores the storage states of the codes stored in the IB 102 in association with the numerical values. Specifically, one of the three states shown in FIG. 3 is stored. State S0 is IBH102a
And IBL 102b indicate a state in which no code is stored, state S1 indicates a state in which a code is stored in the IBH 102a but no code is stored in the IBL 102b, and state S2 indicates a state in which the IBH 102a and the IB
This shows a state where a code is stored in L102b.

The decoding unit 105 refers to the state stored in the storage unit 110, decodes the one-byte code stored in the IR 104, and outputs the result to the execution unit 10.
8 and the control unit 109 are notified. The decoding unit 105 has a code size judging unit 107 and a word alignment judging unit 106 for making a specific judgment, in addition to having a general function of decoding a code.

The code size determining unit 107 determines whether the word length of the code to be decoded next is 1 nibble or 1 byte, and notifies the control unit 109 of the result. The control unit 109 controls the SI 103 based on the notification from the code size determination unit 107 and the state stored in the storage unit 110.
And the state stored in the storage unit 110 is updated.

The word alignment judging section 106 judges whether or not the decoded instruction is a subroutine branch instruction placed on a half-byte boundary in the external memory, and notifies the execution section 108 of the result. Here, the half-byte boundary is a term for a byte boundary, and indicates a storage area corresponding to one address on an external memory, that is, a central position of a 1-byte storage area, that is, a boundary between an upper nibble and a lower nibble. Say. On the other hand, a byte boundary refers to a boundary between a 1-byte storage area corresponding to one address on the external memory and a 1-byte storage area corresponding to an address next to the storage area.

The execution unit 108 controls each component of the instruction decoding block 100 and the data path block 200 according to the decoding result of the decoding unit 105, and performs data transfer and calculation. The control signal output from the execution unit 108 is sent to each component, but the connection is not shown in FIGS. 1 and 2. All components including the execution unit 108 operate in synchronization with a clock signal (not shown), and the operation changes in units of a clock cycle. (Instruction Format) Next, the instruction format of the microprocessor configured as described above will be described. FIG. 4 is a configuration diagram of bits for explaining the instruction format. All instructions that can be decoded and executed by the microprocessor are in Format 1 (FIG. 4).
(A)) or format 2 (FIG. 4 (b)).

The instructions classified into the format 1 have a variable length configuration in which an extension word is added in units of 1 nibble to a basic instruction word of 1 byte length. All instructions consist of a basic instruction word followed by an expansion word, but may have no expansion word. Here, the basic command word is an operation code that specifies the type of command, and is a target to be decoded by the decoding unit 105. The extension word refers to data (displacement, immediate value, or the like) to be subjected to an operation such as an operation by a basic instruction word, and is not to be decoded by the decoding unit 105.

For example, the instruction "add # 2, d0" to "add immediate 2 to the value stored in register d0"
Is expressed by a code “0c2 (hex)” including a basic instruction word “0c (hex)” and an expansion word “2”.
The basic instruction word “0c” means an arithmetic operation of “adding the value of the extended word of the next one nibble to the value of the register d0”. According to the present microprocessor, as in this example,
In the case of an instruction instructing an operation of a numerical value that can be represented by one nibble and a register value, a total of three nibbles, that is, 12 bits is sufficient. However, in the case of a conventional microprocessor in which one byte is an extension unit of an instruction, even if the instruction has the same content as described above, the extension word is forced to be "02" (hex) ". A bit is needed.

Therefore, in the case of the instruction shown in the format 1, useless information is eliminated, so that even an instruction instructing the same contents can be configured with a smaller number of bits. On the other hand, instructions classified into format 2 have a variable length configuration in which an extension word is added in units of 1 nibble to a basic instruction word of 3 nibbles length. For example, "the exclusive OR of the immediate value ff (hex) and the value stored in the register d0 is taken."
The instruction “XOR # ff, d0” is a basic instruction word “2
08 (hex) "and an extension word" ff (hex) ", and is expressed by a code" 208ff (hex). "The basic instruction word" 208 "is" the value of the following 1-byte extension word and the register d0. In the case of this instruction, the three nibbles of the basic instruction word are decrypted by the decryption unit 105.

The format 2 basic instruction word is the first
The nibble code is defined as "2" or "3". That is, the code of the basic instruction word is “2xx (hex)” or “2xx (hex)”.
3xx (hex) ".
This is for discriminating which of the two types of instruction format the instruction is based on only the value of the first nibble.

As is clear from the above description, the instruction set of this microprocessor is 8, 12, 16, 20,
The minimum is an 8-bit length, such as 24,..., And the word length is extended in 4-bit units. That is, the word length of each instruction is defined as a value extended in units of bits (4 bits) smaller than the bit width (8 bits) of the instruction decoder. Therefore, by using these instruction sets, the bit width of the instruction decoder (8
Bit), compared to using the extended instruction
Even for programs having the same contents, useless codes can be eliminated, so that the entire code size can be compressed. (Operation of Microprocessor) Next, the operation of the microprocessor having the instruction set defined as described above will be described.

The present microprocessor is characterized in that the word length of an instruction is extended in units of a word length (4 bits) smaller than the word length (8 bits) of the input of the decoding unit 105. Therefore, a characteristic operation resulting from this point will be described, and a description of an operation that is not different from a conventional microprocessor having an instruction set extended in 8-bit units will be omitted. The operation of the data path block 200 is the same as that of the conventional microprocessor, so that the description thereof will be omitted, and the operation of the instruction decoding block 100 will be mainly described. (Decryption Example 1) First, the operation of the instruction decoding block 100 when the instruction is located at a byte boundary of the external memory will be described.

FIG. 5 is a diagram for explaining the operation when an instruction having a length of 5 nibbles is decoded and executed by the microprocessor. FIG. 5A shows the format of the instruction, which is composed of a basic instruction word of 3 nibbles and an extended word of 2 nibbles. Here, for convenience of explanation, codes constituting instructions are represented as A, B, C, D, and E in nibble units. FIG. 5B is a diagram showing the arrangement of each code when this instruction is stored in an external memory. still,
The basic instruction word and the expansion word differ in the arrangement order of each code when they are stored in the external memory.

FIG. 5C shows an instruction pipeline in each clock cycle, that is, IFB 101 and IB 10 when this instruction is read into the instruction decoding block 100.
2 is a table showing 1-byte codes stored in the IR 104 and states stored in the storage unit 110. FIG.
The symbol "-" written in the table (c) indicates that it is not related to the execution of this instruction.

In clock cycle 1, the first one-byte code "BA" of the instruction is fetched into IFB101. Subsequently, in clock cycle 2, the following 1
The byte code “EC” is fetched into the IFB 101 and the code “BA” stored in the IFB 101
Is transferred to the IB 102. Note that code fetch and transfer in the instruction pipeline are performed in accordance with an instruction from the execution unit 108 sent every clock cycle. In clock cycle 2, since the decoding of the instruction immediately before this instruction has been completed, the state is S2.

When the clock cycle 3 is started, first, the control unit 109 knows that the state stored in the storage unit 110 is S2, and the code size determination unit 107 determines "the code to be decoded next". Is 1 byte long. " As a result, the control unit 109
1-byte code stored in IB102 is converted to IR
A selection signal is output to the SI 103 so as to be transferred to the S 104, and the state S 2 is written to the storage unit 110. Based on the selection signal, the SIH 103a transfers the code “A” stored in the IBL 102b to the IRH 104a, and the SIL 103b transfers the code “B” stored in the IBH 102a to the IRL 104b.

As a result, the code “AB” transferred to the IR 104 is decoded by the decoding unit 105. The code size determination unit 107, by decoding the code “A” of the first nibble of this instruction, knows that this instruction is in format 2, that is, the basic instruction word is 3 nibbles long, and The word length of the code is determined to be the word length of the remaining basic instruction word, that is, one nibble.

In clock cycle 4, control unit 1
09 determines that the state stored in the storage unit 110 is S2, and the code size determination unit 107
The control unit 109 receives the notification that the word length of the code to be decoded next is 1 nibble.
b, and outputs a selection signal to the SI 103 to transfer the code stored in the IRL 104b to the IRL 104b.
Is written into the storage unit 110. Based on the selection signal,
The SIH 103a transfers the code “B” stored in the IRL 104b to the IRH 104a, and
Replaces the code “C” stored in the IBL 102b with the I
Transfer to RL 104b.

As a result, the code “BC” transferred to the IR 104 is decoded by the decoding unit 105. The execution unit 108 executes I based on the result of decryption by the decryption unit 105
The expansion word "D" stored in the FB101 and the IB102
E ″ to the data path block 2 via the internal B bus 204
00 and perform the necessary data processing to terminate the execution of the 5-nibble length instruction.

Here, the first nibble "A" of the basic instruction word is used.
Has only information that this instruction is three nibbles long, and the following instruction "BC" has the substantial content of this instruction (eg, "add register value to immediate value"). Is defined. Therefore, when executing based on the result of decoding the code “BC”, the execution unit 108 does not need the result of decoding the code “AB” already performed.

As described above, the basic instruction word having a length of 3 nibbles is correctly decoded and executed by the decoding unit 105 even though the word length is 1.5 times the input word length of the decoding unit 105. You. (Decoding Example 2) Next, the instruction decoding block 100 in the case where the instruction is located at a half byte boundary of the external memory.
Will be described.

The format of this instruction is the same as the format in the first decryption example shown in FIG.
FIG. 6A is a diagram showing an arrangement in a case where the instruction is stored in the external memory in units of nibbles. The instruction is different from the case of the decoding example 1 shown in FIG. 5B in that the instruction is not placed on a byte boundary but on a half-byte boundary. Hereinafter, points different from the decoding example 1 will be mainly described.

FIG. 6B is a table showing the flow of the instruction pipeline, and corresponds to FIG. 5C in the first decoding example. In the clock cycle 1, the code “A” of the first nibble is fetched into the IFB 101, and in the following clock cycle 2, the 1-byte code “BC” is
Fetched to B101. In clock cycle 2, the state is S1 because the last nibble of the instruction immediately before this instruction was located on a half-byte boundary.

When the clock cycle 3 is started, first, the control unit 109 knows that the state stored in the storage unit 110 is S1, and the control unit 109 determines from the code size determination unit 107 that "the code to be decoded next" is "1". Is 1 byte long. " As a result, the control unit 109
1 stored across IFB 101 and IB 102
SI 103 to transfer the byte code to IR 104
And outputs the state signal S1 to the storage unit 110.
Write to. Based on the selection signal, SIH103a
Replaces the code “A” stored in the IBH 102a with the I
The transfer to the RH 104a, the SIL 103b
01b stored in the IRL 104b
Transfer to

As a result, the code “AB” transferred to the IR 104 is decoded by the decoding unit 105. The code size determination unit 107, by decoding the code “A” of the first nibble of this instruction, knows that this instruction is in format 2, that is, the basic instruction word is 3 nibbles long, and The word length of the code is determined to be the word length of the remaining basic instruction word, that is, one nibble.

In clock cycle 4, control unit 1
09 knows that the state stored in the storage unit 110 is S1, and the code size determination unit 107
The control unit 109 receives the notification that the word length of the code to be decoded next is 1 nibble.
a, and outputs a selection signal to the SI 103 to transfer the code stored in the IRL 104b to the IRL 104b.
Is written into the storage unit 110. Based on the selection signal,
The SIH 103a transfers the code “B” stored in the IRL 104b to the IRH 104a, and
Converts the code “C” stored in the IBH 102a into an I
Transfer to RL 104b.

As a result, the code “BC” transferred to the IR 104 is decoded by the decoding unit 105. The execution unit 108 executes I based on the result of decryption by the decryption unit 105
The extended word "DE" stored in B102 is transferred to the data path block 200 via the internal B bus 204, and the necessary data processing is performed to terminate the execution of the 5-nibble length instruction.

As described above, even the instruction located at the half-byte boundary of the external memory is correctly decoded and executed by the microprocessor. (Branch Example 1) Next, the format of a branch instruction and the operation of the present processor for branching to a program starting from a half-byte boundary will be described.

FIG. 7 shows the format of the unconditional branch instruction jmp. This instruction consists of an 8-bit basic instruction word and 16
It consists of a 6 nibble length code combined with bit extension words.
By the way, in the present microprocessor, since an instruction may be placed at a position starting from a half-byte boundary of an external memory, 16 bits are not enough to specify a memory address of a branch destination. That is, even for a memory address specified by 16 bits, it is necessary to specify whether to branch to an instruction located in the upper nibble or the lower nibble of the address. Therefore, an 8-bit basic instruction word for specifying an unconditional branch instruction and a word length obtained by adding an expansion word of 17 bits or more for specifying a branch destination address, that is, an instruction having a length of 7 nibbles, You can also.

However, using a 7 nibble length code, jm
When the p instruction is defined, this code includes a wasteful code of 3 bits that is not substantially used, which hinders a reduction in code size. Therefore, as shown in FIG. 7, the least significant bit of the basic instruction word of the jmp instruction is defined as information for indicating whether or not the branch destination instruction is located at a half-byte boundary on the external memory. I have. That is, the code of the jmp instruction is defined so that the memory address of the branch destination is specified by a total of 17 bits including the least significant bit of the basic instruction word and the two bytes of the expansion word. Thereby, the unconditional branch instruction jmp becomes 7
Since the code is defined by being compressed to a code having a length of 6 nibbles instead of the nibble length, generation of useless codes is avoided.

Next, the operation of the present microprocessor when the jmp instruction is executed will be described. Now, it is assumed that the 3-byte length jmp instruction is fetched from the external memory and held in the IFB 101, IB 102, and IR 104. The decoding unit 105 sends only the information of the least significant bit of the basic instruction stored in the IR 104 to the control unit 109. The control unit 109 determines that the transmitted information is "
If it is "1", the state S1 is written to the storage unit 110, and if it is "0", the state S2 is written.

At the same time, the decoding unit 105 notifies the execution unit 108 that this instruction is an unconditional branch instruction by decoding the upper 7 bits of the code of the basic instruction word stored in the IR 104. Upon receiving this notification, the execution unit 108 sets the 16-bit branch destination address stored in the IFB 101 and the IB 102 to the data path block 2.
00 and output to the external address bus 212. As a result, the instruction on the external memory starting from the memory address designated by the external address bus 212 is 1
The instruction is read into the instruction decoding block 100 in byte units.

The code for the first byte of the branch destination is IB
Once transferred to 102, the control unit 109 determines the code to be decoded in the next clock cycle by:
SI 103 according to the state stored in storage unit 110
Control. Specifically, when the state S2 is stored in the storage unit 110, the control unit 109 controls the SI 103 to transfer the one-byte code held in the IB 102 to the IR 104. This control is similar to the control in clock cycle 3 of the above-described decoding example 1, and corresponds to decoding an instruction starting from a byte boundary placed on the external memory. That is, this case corresponds to the branch processing to the byte boundary.

On the other hand, when the state S1 has been stored in the storage unit 110, the control unit 109
The SI 103 is controlled so as to transfer a one-byte code extending to the IR 102 to the IR 104. This control is the same as the control in clock cycle 3 in the above-described decoding example 2, and corresponds to decoding an instruction starting from a half-byte boundary placed on the external memory. That is, this case corresponds to the branch processing to the half-byte boundary.

With the above operation, the branch processing to the byte boundary or the half-byte boundary by the 3-byte unconditional branch instruction jmp is completed. (Branch Example 2) Next, the operation of the present processor that has executed a subroutine branch instruction (hereinafter, referred to as "jsr instruction") when the memory address to be returned after the branch is a half-byte boundary will be described.

Here, the jsr instruction is a storage area indicated by the stack pointer (SP) 202a with the return address next to the memory address where this instruction is located, prior to the branch processing to the specified memory address. (Hereinafter, simply referred to as a “stack”). This instruction is used in combination with a return instruction instructing the end of the subroutine. When the return instruction is executed, a process of reading the return address saved on the stack and returning to the address is performed.

By the way, considering the return to the half-byte boundary on the external memory, 17 bits are required to specify the return address as described in the first branch example. Therefore, the return address code saved on the stack is
Two bytes are not enough and three bytes are needed. That is, j
Each time an sr instruction or a return instruction is executed, it is necessary to access the stack three times.

However, even if the programs have the same contents, if the frequency of accessing the stack increases, the throughput of the microprocessor decreases by the time required for the processing. In particular, in a program written in the C language, the stack is generally used frequently, and the throughput is strongly affected by the number of times the stack is accessed.

Therefore, in the present microprocessor, even if the return address is on a half-byte boundary, it is devised that saving to the stack requires only 2 bytes. The details will be described below. The format of the jsr instruction is the same as the unconditional branch instruction shown in FIG.
That is, this instruction is composed of a total of 3 bytes obtained by adding a 2-byte extension word to a 1-byte basic instruction word, and the branch destination address is a total of 17 bytes including the least significant bit of the basic instruction word and 16 bits of the extension word. Specified by bit. Therefore, whether the branch destination is a byte boundary or a half-byte boundary of the external memory is executed in the same manner as in the case of the first branch example.

Next, the operation of the microprocessor when the jsr instruction is executed will be described with reference to the flowchart shown in FIG. When the basic instruction word of this instruction is stored in the IR 104, the word alignment judging unit 106 recognizes that this instruction is a jsr instruction and, at the same time, refers to the state stored in the storage unit 110, It is determined whether the instruction is located on a byte boundary or a half-byte boundary on the external memory, and the result is notified to the execution unit 108 (step S81).

The execution unit 108, which has been notified that this instruction is located at a byte boundary on the external memory, recognizes that the word length of this instruction itself is 6 nibbles as defined above (step S82). The memory address of the instruction placed immediately after this instruction, that is, the memory address indicating a byte boundary represented by 16 bits, is saved on the stack (step S84). FIG. 9A is a diagram showing a relationship between a jsr instruction located at a byte boundary on an external memory and a return address.

On the other hand, when the execution unit 108 is notified that this instruction has been placed on a half-byte boundary in the external memory,
Assumes that the word length of this instruction itself is 7 nibbles instead of 6 nibbles (step S83), and the memory address of the instruction placed immediately after this 7 nibble length instruction, that is, 16
The memory address indicating the byte boundary represented by the bit is saved on the stack (step S84). Specifically, the execution unit 108 reads the memory address where the instruction is located from the decryption counter (DECPC) 205 and sends it to the arithmetic unit (ALU) 208, and determines that the instruction itself has a length of 7 nibbles. A return address in the case is calculated, and each component is controlled to write the return address to the stack. FIG. 9B is a diagram showing the relationship between the jsr instruction located at the half-byte boundary on the external memory and the return address.

The operation after saving the return address on the stack is the same as the operation in the first example of branching, and the execution unit 108 performs processing for branching to the head address of the subroutine specified by the lower 17 bits of this instruction. Is performed (step S85).
As described above, even if the jsr instruction is located on a byte boundary or a half-byte boundary on the external memory, the return address saved on the stack is only 2 bytes.

When the return instruction is executed after the processing of the subroutine, the execution unit 108 reads the 2-byte return address saved on the stack and stores it in the address buffer (ADB) 209. Each component is controlled to execute the instruction starting from that address. By the way, assuming that the jsr instruction is executed as described above,
The jsr instruction and the next instruction need to be arranged on the external memory consistent with the above operation. That is, jsr
When an instruction is arranged at a half-byte boundary on the external memory, the next instruction is arranged on the external memory, assuming that the jsr instruction is not a 6 nibble length instruction but a 7 nibble length instruction. Needless to say, it is necessary. This processing is realized by a memory address allocation program generally called a linker, and is not directly related to the operation of the present microprocessor.

As is apparent from the above description, in the present microprocessor, when the jsr instruction is executed, the return address of 2 bytes is always set regardless of the boundary of the memory address where the instruction is located. Just evacuate. Therefore, the processing time of the program is reduced as compared with the case where the return address of 3 bytes is saved. As described above, the microprocessor according to the present invention has been described based on the embodiments. However, it goes without saying that the present invention is not limited to these embodiments. That is, (1) In the present embodiment, the unit for decoding the instruction, that is,
Although one word has eight bits, the number of bits is not limited. For example, one word may be 12 bits. In that case, in the instruction decoding block 100 and the data path block 200, the bit width of all the constituent parts composed of 8 bits is set to 12 bits, and the code arranged in the external memory is set to 12 bits. Good. (2) In the present embodiment, the storage state of the code in the IB 102 is stored in the storage unit 110, but the present invention is not limited to the IB 102. For example, IFB101 and IB10
2 may be stored. This enables flexible control based on the presence or absence of a code in the IFB 101 as well as the IB 102. (3) The instruction pipeline in this embodiment is IFB1
01, the IB 102 and the SI 103, but the number of stages is not limited.

[0075]

As is apparent from the above description, according to the microprocessors of the first and second aspects, the word length of the instruction is one word, that is, an integer of the word length of the code that the decoder decodes at one time. It is not limited to double. Therefore, it is possible to reduce the ratio of useless bits that are not used in the code constituting the instruction.

As a result, even if the programs have the same contents, it is possible to create a program with a reduced code size. According to the microprocessor of the third aspect , the word length of the instruction is a value extended in units of half words. Therefore, it is possible to finely define an instruction or specify data in units of a half word.

According to the microprocessor of the fourth aspect, it is possible to determine, in half word units, how the code to be decoded next is arranged in the instruction buffer. According to the microprocessor of the fifth aspect, the code held in the instruction buffer can be independently transferred to the decoding register in half word units and decoded.

[0078] According to the microprocessor of claim 6, also correctly decrypted run a 1 word length code placed over two addresses on the external memory. According to the microprocessor of the seventh aspect , even a half-word length code placed at a lower position on the external memory can be correctly decoded and executed. According to the microprocessor of the eighth aspect , even a half-word length code placed at a higher position on the external memory can be correctly decoded and executed.

According to the microprocessor of the ninth aspect , even when a subroutine branch instruction placed on a halfword boundary on an external memory is executed, it is the same as when the instruction is placed on a word boundary. It is only necessary to save the return address consisting of the number of bits. Therefore, the frequency of access to the stack is reduced, and wasteful consumption of the stack can be avoided.

As a result, even when programs having the same contents are executed, there is an effect that the throughput can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of an instruction decoding block 100 of the microprocessor according to the embodiment.

FIG. 3 is an IB10 of the microprocessor according to the embodiment.
FIG. 4 is a diagram illustrating a storage state of codes in FIG.

FIG. 4 is a diagram showing two types of formats of instructions executed by the microprocessor according to the embodiment.

FIG. 5A is a diagram showing a format of a 5-nibble-length instruction in the embodiment. FIG. 5B is a diagram showing an arrangement of each code when the instruction shown in FIG. 5A is located at a byte boundary on the external memory. FIG. 5C is a diagram showing the flow of the instruction pipeline in each clock cycle when the instruction shown in FIG. 5A is read into the instruction decoding block 100.

FIG. 6A is a diagram showing an arrangement of each code when the instruction shown in FIG. 5A is located at a half-byte boundary on an external memory. FIG. 6B shows FIG.
FIG. 3 is a diagram showing a flow of an instruction pipeline in each clock cycle when the instruction shown in FIG.

FIG. 7 is a diagram showing a format of an unconditional branch instruction jmp in the embodiment.

FIG. 8 is a flowchart showing the operation of the microprocessor when a jsr instruction is executed in the embodiment.

FIG. 9A is a diagram showing a relationship between a jsr instruction located at a byte boundary on an external memory and a return address in the embodiment. FIG. 9 (b) shows the j that is located at the half-byte boundary on the external memory in the embodiment.
FIG. 4 is a diagram illustrating a relationship between an sr instruction and a return address.

FIG. 10 is a diagram showing a bit configuration of an instruction in a conventional microprocessor.

[Explanation of symbols]

 101a IFBH 101b IFBL 102a IBH 102b IBL 103a SIH 103b SIL 104a IRH 104b IRL 105 Decryption unit 106 Word alignment determination unit 107 Code size determination unit 108 Execution unit 109 Control unit 110 Storage unit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-97031 (JP, A) JP-A-54-124343 (JP, A) JP-A-4-101230 (JP, A) JP-A-3-103 33931 (JP, A) JP-A-61-33545 (JP, A) JP-A-63-244233 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9 / 30-9 / 355 G06F 9/40-9/42

Claims (11)

(57) [Claims] 1. A microprocessor comprising: a decoder for decoding coded instructions one by one; and execution means for executing data processing based on a result of decoding by the decoder. Where a is the minimum word length of the code that the decoder decodes at a time and b is a word length smaller than a, where w is a + nb (where n is a positive integer including 0 and 1 ) ) is represented by the execution unit, microprocessor and executes instructions and word length at least word length is a is an instruction is (a + b). 2. The microprocessor according to claim 1, wherein said b is a half word when said a is one word. 3. The microprocessor further comprises : an instruction buffer for holding a pre-read instruction; an upper-side decoding register and a lower-side decoding register for holding a one-word code to be decoded by the decoder in half-word units. First determining means for determining whether a word length of a code to be newly transferred to the decoding register is half word or 1 word based on a decoding result by the decoding device; When the determination means determines that the code is a half word, the code stored in the lower decoding register is transferred to the upper decoding register, and the code of the next half word to be transferred stored in the instruction buffer is transferred. 3. The microprocessor according to claim 2, further comprising selection means for transferring the data to the lower decoding register. 4. The microprocessor according to claim 1, further comprising : an instruction buffer configured to store a pre-read instruction; a storage unit configured to store a storage state of the instruction in the instruction buffer in a unit of half word; First determining means for determining whether the word length of a code to be decoded next is half word or one word; and storing the code in the instruction buffer based on the determined word length and the storage state. 3. The microprocessor according to claim 2, further comprising: control means for controlling the instruction buffer so as to take in the decoded code into the decoder and updating the storage state. 5. The microprocessor further comprises : an instruction buffer for holding prefetched instructions; storage means for storing a storage state of instructions in the instruction buffer in halfword units; An upper-side decoding register and a lower-side decoding register that divide and hold a code by half words, and, based on the storage state, control the instruction buffer so as to take in the code stored in the instruction buffer into the decoding register. Control means for updating the storage state; and determining whether the word length of a code to be newly transferred to the decoding register is half word or one word based on a decoding result by the decoding unit. And a lower-order decryption register when the first determination means determines that the word is a halfword. Selecting means for transferring the stored code to the upper decoding register and transferring the halfword code to be transferred next stored in the instruction buffer to the lower decoding register. The microprocessor according to claim 2. 6. The instruction buffer comprises : a first register for holding a code of the most recently fetched one word; and a second register for holding a code of a one word fetched immediately before the first register. Consists of an upper first register and a lower first register that hold a one-word code in half-word units, and the second register holds the one-word code in half-word units. An upper second register and a lower second register; and the selection means is held in at least one register selected from the upper second register, the lower second register, and the lower decoding register. Upper-side selection means for transferring a code to the upper-side decoding register; and at least the lower-side first register and the upper-side second register. And lower-order selecting means for transferring a code held in one register selected from the lower-order second register to the lower-order decoding register. The storage means includes the upper-side second register and the lower-order register. A first state in which no code is held in any of the second side registers, and a first state in which a code is held in the upper second register but no code is held in the lower second register. 6. The microprocessor according to claim 5, wherein a state stored in any one of a second state and a third state in which a code is held in the upper second register and the lower second register is stored. . 7. The control means determines that the state stored in the storage means is a second state and the word length of a code to be decoded next by the first determination means is one word. If it is determined, the upper-side selecting means transfers the code held in the upper-side second register to the upper-side decoding register, and the lower-side selecting means holds the code held in the lower-side first register. 7. The microprocessor according to claim 6, wherein said selection means is controlled so as to transfer a code to said lower decoding register. Wherein said control means state stored in said storage means is a third state, and when the word length of the code to be deciphered in the following by the first determination means is a halfword When it is determined, the upper-side selection means transfers the code held in the lower-side decoding register to the upper-side decoding register, and the lower-side selection means is held in the lower-side second register. 7. The microprocessor according to claim 6, wherein the control means controls the selection means so as to transfer the stored code to the lower decoding register, and updates a state stored in the storage means to a second state. 9. The control means determines that the state stored in the storage means is a second state and the word length of a code to be decoded next by the first determination means is a half word. If it is determined, the upper-side selection means transfers the code held in the lower-side decoding register to the upper-side decoding register, and the lower-side selection means is held in the upper-side second register. 7. The microprocessor according to claim 6, wherein the control means controls the selection means so as to transfer the stored code to the lower decoding register, and updates a state stored in the storage means to a third state. Wherein said processor is further based on the result of decoding by the decoder and stored stored state in the storage means, location in memory where the instruction is decoded by the decoder is terminated halfword Second determining means for determining whether or not the instruction is a subroutine branch instruction which has been placed in the memory. The execution means is a subroutine branch instruction which has been placed in a memory where the instruction ends in a halfword. When it is determined that a memory address obtained by adding an address corresponding to a halfword code to a memory address corresponding to the position is regarded as a return address from the subroutine, branch processing to the subroutine is executed. The microprocessor according to claim 4, wherein 11. An instruction buffer for holding a pre-read instruction, a decoder for decoding a coded instruction one word at a time, and a high-order part for holding a one-word code to be decoded by the decoder in half-word units. A side decoding register, a lower side decoding register, and a second determining unit that determines whether the word length of a code to be newly transferred to the decoding register is a half word or a single word based on a result of decoding by the decoder. When the first determining means determines that the code is a half word, the code stored in the lower decoding register is transferred to the upper decoding register, and the next code stored in the instruction buffer is transferred. Selecting means for transferring a half-word code to be transferred to the lower decoding register.