JP3159168B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method for forming a resist pattern for patterning at an accurate position by using a mark for overlay measurement provided on the resist pattern. Superimpose on the mark formed on the top, measure the positional relationship between the mark formed on the semiconductor device and the mark formed on the resist,
The present invention relates to a semiconductor device in which a resist is patterned at an accurate position based on the measurement result, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been miniaturized. This miniaturization not only reduces the gate width and the like of the transistor, but also reduces the overlap margin. For example, in a 16 Mb DRAM, ± 0.1
Although an overlap margin of about 2 μm has been ensured, it has become difficult to secure an overlay margin of about ± 0.04 μm in a 256 Mb DRAM about two generations ahead. For this reason, as the generation progresses, a method of obtaining overlay accuracy and a method of measuring and evaluating overlay have been studied.

Next, COB (Capacitor Ov)
A conventional technique of an overlay measurement mark for positioning a resist pattern for forming a capacitor lower electrode at a predetermined position on a capacitor contact will be described by taking a DRAM having an er Bitline structure as an example. FIG. 6 shows a cross-sectional view and a layout diagram of the overlay measurement mark. 6 is formed simultaneously with the capacitor contact hole 27, and a region surrounded by a square is etched at the same time as the capacitor contact hole 27 is etched to form a concave shape. The upper ground mark 101 is formed simultaneously with the resist pattern 29 for the capacitor lower electrode, and the area surrounded by the square becomes convex.

FIG. 6A shows a state in which a resist pattern 30 for measurement is formed simultaneously with a resist pattern 29 for patterning in a region surrounded by a square.
As shown in (b), while measuring the distances X1, X2, Y1, Y2, X1-X2 <εx and Y1-Y2 <
When εy (εx, εy are predetermined values), etching of the lower electrode by the resist pattern 29 is started.

FIG. 6A shows a cross-sectional structure of a memory cell region, and also shows a cross-section taken along line AB of a simultaneously formed overlap mark. Since this figure shows the structure at the time of overlay measurement, the capacitor lower electrode has not been formed yet. As shown in FIG. 6A, a gate electrode 24 forming a word line exists on a semiconductor substrate 21 having an element isolation oxide film 22 and a diffusion layer region 23 in a memory cell region.
Further, a bit line 26 is provided via a contact plug 25.
Are electrically connected to the diffusion layer region 23, a phosphorus-doped polysilicon film 28 is formed on the entire surface including the inside of the capacitor contact hole 27, and a resist pattern 29 for forming a capacitor lower electrode exists thereon. It has a structure to do. On the other hand, the overlay measurement mark is used for measurement, the upper mark used for measurement is formed by the resist pattern 30 formed simultaneously with the capacitor lower electrode resist pattern 29, and the base mark 31 is formed simultaneously with the capacitor contact hole 27. And a pattern 31 reaching the silicon substrate 21.

As shown in FIG. 6A, the underlying mark pattern 31 formed simultaneously with the contact hole 27 penetrates the second and first interlayer insulating films 34 and 33 and reaches the silicon substrate 21. Here, the base mark 31 has a rather gentle tapered shape in a wide pattern such as a box mark under a contact etching condition that provides high selectivity with the silicon substrate. When viewed from the top, the edge has a wide width as shown in FIG. 6C, so that the peak of the edge waveform in the automatic misalignment measurement becomes gentle and a measurement error easily occurs. Also, the upper mark 30 formed simultaneously with the resist pattern 29 for the capacitor lower electrode is formed with a considerably large step and taper, so that it deviates greatly from the best focus during exposure.

Therefore, when viewed from the top, the edges 101a and 102a are wide, so that the peak of the edge waveform in the automatic misalignment measurement becomes gentle and a measurement error easily occurs.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art, and in particular, to form a mark and a resist formed on a semiconductor in order to form a resist pattern for patterning at an accurate position. It is intended to provide a novel semiconductor device and a method for manufacturing the same, which reduce the measurement error when measuring the positional relationship with the mark formed by the method and improve the production efficiency of the semiconductor device.

[0009]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, the first aspect of the semiconductor device according to the present invention is that a first interlayer insulating film is formed on a semiconductor substrate.
Forming a film, and forming a wiring layer on the first interlayer insulating film
To cover the first interlayer insulating film and the wiring layer.
In a semiconductor device having a second interlayer insulating film formed thereon and provided with an overlay measurement mark, the first interlayer insulation film is provided.
An etching stopper is formed on the same layer as the wiring layer on the edge film.
And forming the second interlayer insulation on the etching stopper.
Forming an opening pattern with a concave cross section by etching the edge film
The mark is placed on the etching stopper and in front of the etching stopper.
The second aspect is characterized in that the first layer is formed on the semiconductor substrate so as to include the opening pattern.
Forming an interlayer insulating film, and forming a wiring layer on the first interlayer insulating film.
And cover the first interlayer insulating film and the wiring layer.
A semiconductor device having a second interlayer insulating film formed thereon,
To form a resist pattern for patterning at an accurate position, the first marks formed by the resist pattern superimposed on the second mark formed on the semiconductor device, the first and second mark In the semiconductor device for performing overlay measurement by using the first interlayer insulation,
An etching stopper formed on the film in the same layer as the wiring layer, and the etching stopper formed by etching a second interlayer insulating film on the etching stopper
And opening pattern to the base portion, forming a second mark at film formed on the entire surface formed on the opening pattern containing the opening pattern, in the resist pattern on said second mark said first mark and, in which is characterized by being configured, also, the third aspect, the etching stopper, which is characterized in that formed in the wiring layer, and, In a fourth aspect, the mark is a mark having a box-in-box structure, and in a fifth aspect, the mark is a mark having a vernier caliper structure. Is what you do.

In a first aspect of the method for manufacturing a semiconductor device according to the present invention, a first interlayer insulating film is formed on a semiconductor substrate.
Forming a wiring layer on the first interlayer insulating film;
A second interlayer insulating film covering the first interlayer insulating film and the wiring layer;
A semiconductor device forming an insulating film to form a resist pattern for patterning at an accurate position, to form a first mark formed by the resist pattern on the semiconductor <br/> body apparatus on superimposed on the second mark, in the manufacturing method of a semiconductor device for performing measurements overlay using the first and second mark, the first interlayer insulating film
A first step of forming an etching stopper in the same layer as the wiring layer, and forming the first interlayer insulating film and the wiring layer
A second step of forming the second interlayer insulating film so as to cover the second insulating film, and etching the second interlayer insulating film ,
The etching stopper to expose the, a third step of forming an opening pattern of a concave cross section over the etching stopper, at Rukoto entire surface to the third film was a <br/> deposition of including the opening pattern a fourth step of forming the second mark, and forming the resist pattern on the third layer, superimposed the first marks formed by the resist pattern on the second mark a fifth step of combining, which is characterized in that it comprises, also, the second aspect, the etching stopper, and is characterized in that <br/> formed in the wiring layer.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, in order to form a resist pattern for patterning at an accurate position, a second mark formed with the resist pattern on a semiconductor device is formed. In a semiconductor device that is superimposed on a mark and performs overlay measurement using the first and second marks, the etching stopper provided in the semiconductor device and the first film on the etching stopper are etched. The second mark formed on the opening pattern by the second film, the second mark formed on the entire surface including the opening pattern, and the second mark formed on the entire surface including the opening pattern. And the first mark formed by the resist pattern formed on the mark, when the second mark is viewed from above, Optically clear waveform 2 of mark edge is thin can be obtained. Also,
Since the height of the first mark on the second mark is also reduced,
A sharp edge waveform is obtained. For this reason, the measurement error is reduced, and the resist pattern can be arranged at an accurate position.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a semiconductor device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a view showing the structure of a specific example of a semiconductor device according to the present invention. In these figures, in a semiconductor device having marks 101 and 102 for overlay measurement, the mark 102 has a concave section. The semiconductor device in which the mark 102 is formed on the etching stopper 12 is shown.

A resist pattern 9 for patterning is used.
A first mark 101 formed by the resist pattern 9 is superimposed on a second mark 102 formed on the semiconductor device, and a predetermined etching is performed by the resist pattern 9 In the apparatus, the etching stopper 12 provided on the semiconductor device and the first film 1 on the etching stopper 12 are formed.
4, an opening pattern 11 formed by etching, a second film 8 formed on the entire surface including the opening pattern 11,
The second mark 102 formed on the opening pattern 11 by the second film 8 and the first mark formed by the resist pattern formed on the second mark 102
And a semiconductor device constituted by the mark 101 of FIG.

FIGS. 1 to 3 show a first step of forming the wiring layer 6 on the first film 13 and forming the etching stopper 12, and a second film 14 on the wiring layer 6. A second step of forming the first and second films 13 and 14
And the etching stopper 12
A third step of forming an opening pattern 11 thereon, a fourth step of depositing a third film 8 on the entire surface including the opening pattern 11 and forming the second mark 102,
Forming a resist pattern 9 on the film 8 and overlapping the first mark 101 formed with the resist pattern on the second mark 102. It is shown.

Next, the present invention will be described in more detail. In this specific example, COB (Capacitor Over B)
An overlay measurement mark for positioning a resist pattern for forming a capacitor lower electrode at a predetermined position on a capacitor contact will be described using a DRAM having an inline structure as an example.

FIG. 1B is a layout diagram of an overlay measurement mark according to the present embodiment. The innermost square is an upper mark 101. In this embodiment, a lower electrode of a memory cell and a lower electrode are connected. The second square from the inside is laid out on the same layer and the ground mark 102 is
The base mark is laid out on the wiring layer on which the bit line is formed. The third square 103 from the inside is the etching stopper 12 when forming the base mark, and is laid out in the same layer as the bit line. FIG. 1A is a cross-sectional structure diagram showing a cross-sectional structure of a memory cell region and an AB cross-section of a mark portion. In this figure, since the structure at the time of overlay measurement is shown, the capacitor lower electrode is not formed, and a resist pattern for forming the capacitor lower electrode is provided.

As shown in FIG. 1, a semiconductor substrate 1 having an element isolation oxide film 2 and a diffusion layer region 3 in a memory cell region.
A gate electrode 4 forming a word line is present thereon, and a bit line 6 is further connected to a diffusion layer region 3 through a contact plug 5.
And a phosphorus-doped polysilicon film 8 over the entire surface including the inside of the capacitor contact hole 7.
Is formed, and a resist pattern 9 for forming a capacitor lower electrode is present thereon.
On the other hand, the overlay measurement mark is constituted by an upper mark resist pattern 10 in which an upper mark 101 used for measurement is formed simultaneously with a resist pattern 9 for a capacitor lower electrode. At the same time, the base mark opening pattern 11 is opened, and the opening pattern 11 is formed on an etching stopper 12 provided so as not to reach the semiconductor substrate 1.

FIG. 2 and FIG. 3 are cross-sectional views for each step for explaining the present embodiment. As shown in FIG.
A gate electrode 4 and a diffusion layer region 3 are formed on a semiconductor substrate 1 having an element isolation oxide film 2. After the interlayer insulating film 13 is formed, as shown in FIGS. 2B and 3A, a bit contact reaching the diffusion layer region 3 is opened by using a photolithography technique, and then a contact plug 5 is formed. I do. Then, as shown in FIG. 3A, simultaneously with the formation of the bit line 6, an etching stopper 12 is formed in a region where a capacitor contact-capacitor lower electrode overlay measurement mark is to be formed. Further, after forming the interlayer insulating film 14, the interlayer insulating film 1 is formed by using a photolithography technique.
4 and 13 are etched to open a capacitor contact hole 7 reaching the diffusion layer region 3 and, at the same time, an overlay measurement underlying mark 11 is formed on the etching stopper 12.

At this time, the base mark opening pattern 11 is
Etching stop pad 1 formed on interlayer insulating film 13
2, the etching stops, the interlayer insulating film 13 is not etched, and the base mark opening pattern 1 is located at a shallow position.
1 is formed. Thereafter, a phosphorus-doped polysilicon film 8 is formed on the entire surface, and then a resist pattern 9 for forming a capacitor lower electrode is formed in the memory cell region by photolithography, and an upper surface is formed on the overlay measurement underlying mark 11. A cross-sectional structure as shown in FIG. 1 is obtained by forming the mark resist patterns 10 respectively.

FIG. 1C shows a state of the mark according to the present invention as viewed from above. The base mark edge 102A is thinner and the upper mark 10
1 is thinner, and an optically clear waveform is obtained. As a method of further reducing the position of the base mark, as shown in FIG. 4A, when forming a word line, a pattern 15 is formed below the base mark, and an etching stopper is further formed thereon. By forming 12, the position of the base mark can be formed higher.

By doing so, the height relationship between the memory area and the mark portion becomes the same, so that a more accurate mark can be formed. In the above specific example, the bit line layer immediately below was used as the etching stopper.
As shown in (b), the pattern 15 formed simultaneously with the word line layer may be used as an etching stopper.

FIG. 5 is a view showing another overlay mark of the present invention. A mark having a vernier caliper structure shown in FIG. 5 (hereinafter referred to as a vernier caliper mark) is used not for automatic measurement by a machine but for measurement by human eyes, and is basically a mark having the box-in-box structure described above. Used in the same way. In the case of the vernier caliper, the edge (bottom) of the resist pattern is difficult to be distinguished because the depth of focus of the microscope is small, so that a greater effect can be obtained by employing the present invention.

As described above, in the present invention, the box mark in FIG. 1 and the caliper mark in FIG. 5 have been described as examples, but the present invention can be applied to any mark as long as it is a measurement mark for overlay. .

[0024]

According to the present invention, although the underlying mark has a slightly tapered shape depending on the etching conditions, the taper is less noticeable because the depth is smaller than that of the conventional mark. Therefore, since the undermark mark edge is thinner and optically clear as compared with the conventional technique, a measurement error is less likely to occur during misalignment measurement than in the related art.

Also, the upper mark has a vertical shape because it is formed under exposure conditions better than that of the prior art, and the mark edge is thinner than that of the prior art, and an optically clear waveform is obtained, similarly to the background mark. Therefore, a measurement error is less likely to occur during misalignment measurement than the conventional one.

[Brief description of the drawings]

FIG. 1A is a sectional view of a semiconductor device according to the present invention,
(B) is a diagram showing a mark layout, and (c) is a diagram of the mark viewed from above.

FIG. 2 is a view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 3 is a view showing a manufacturing process following FIG. 2;

FIG. 4 is a diagram showing another specific example of the present invention.

FIG. 5 is a diagram showing another alignment mark.

FIG. 6A is a cross-sectional view of a conventional semiconductor device, and FIG.
Is a view showing the mark layout, and (c) is a view of the mark as viewed from above.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation oxide film 3 Diffusion layer region 4 Gate electrode 5 Contact plug 6 Bit line 7 Capacitor contact hole 8 Phosphorus-doped polysilicon film 9 Capacitor lower electrode forming resist pattern 10 Top mark resist pattern 11 Base mark pattern 12 Etching stopper (bit line same layer) 13, 14 Interlayer insulating film 15 Etching stop pattern (gate electrode same layer) 101 Upper mark 102 Lower mark

Claims (7)

(57) [Claims] 1. A first interlayer insulating film is formed on a semiconductor substrate.
Forming a wiring layer on the first interlayer insulating film;
A second interlayer insulating film covering the first interlayer insulating film and the wiring layer;
In a semiconductor device having an insulating film formed thereon and provided with a mark for overlay measurement, an edge is formed on the same layer as the wiring layer on the first interlayer insulating film.
Forming a chucking stopper on the etching stopper.
An opening having a concave cross section obtained by etching the second interlayer insulating film.
A pattern is formed, and the mark is
A semiconductor device formed on a pad and including the opening pattern . 2. A first interlayer insulating film is formed on a semiconductor substrate.
Forming a wiring layer on the first interlayer insulating film;
A second interlayer insulating film covering the first interlayer insulating film and the wiring layer;
A semiconductor device forming an insulating film to form a resist pattern for patterning at an accurate position, to form a first mark formed by the resist pattern on the semiconductor <br/> body apparatus on In a semiconductor device which is superimposed on a second mark and performs overlay measurement using the first and second marks, the semiconductor device is formed on the same layer as the wiring layer on the first interlayer insulating film.
And an etching stopper formed by etching a second interlayer insulating film on the etching stopper.
And aperture pattern, the said second mark formed on the opening pattern at film formed on the entire surface including the opening pattern, the formed by the resist pattern on said second mark A semiconductor device, comprising: a first mark; 3. The semiconductor device according to claim 1, wherein said etching stopper is formed of said wiring layer. 4. The semiconductor device according to claim 1, wherein the mark is a mark having a box-in-box structure. 5. The semiconductor device according to claim 1, wherein said mark is a mark having a vernier caliper structure. 6. A first interlayer insulating film is formed on a semiconductor substrate.
Forming a wiring layer on the first interlayer insulating film;
A second interlayer insulating film covering the first interlayer insulating film and the wiring layer;
A semiconductor device forming an insulating film to form a resist pattern for patterning at an accurate position, to form a first mark formed by the resist pattern on the semiconductor <br/> body apparatus on In the method of manufacturing a semiconductor device , which is superimposed on a second mark and performs overlay measurement using the first and second marks , etching is performed on the same layer as the wiring layer on the first interlayer insulating film. A first step of forming a stopper, and the step of covering the first interlayer insulating film and the wiring layer.
By etching a second step of forming a second interlayer insulating film, the second interlayer insulating film, wherein d
Exposing the Tsu quenching stopper, a third step of forming an opening pattern of a concave cross section over the etching stopper, depositing a third layer on the entire surface including the opening pattern Turkey
And in a fourth step of forming the second mark, said third and forming the resist pattern on the membrane, the resist pattern is formed by said first mark to the second mark on A method of manufacturing a semiconductor device, comprising: 7. the etching stopper, a method of manufacturing a semiconductor device according to claim 6, characterized in that formed in the wiring layer.