JP3133877B2 - Board test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a board test apparatus for inspecting an image output function of a controller board built in an image forming apparatus such as a laser printer.

[0002]

2. Description of the Related Art In a conventionally known board test apparatus of this type, when testing an image signal output from a controller board, a high-level image signal and a low-level image signal are output from the controller board, respectively. The quality of the image signal is tested by detecting the level of the signal.

[0003]

However, in the test procedure performed by the above-mentioned conventional board test apparatus, since data is not stored in the FIFO memory of the image signal output stage in the controller board, a part of the FIFO memory fails. However, there is a disadvantage that the failure cannot be detected.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a board test apparatus capable of quickly and without error diagnosing an image output function of a controller board built in an image forming apparatus.

[0005]

In order to achieve the above object, a board test apparatus according to the present invention has a predetermined configuration which is transmitted via an external memory provided on a controller board of an image forming apparatus. Image signal input means for inputting a test image signal, measurement means for measuring the number of times the test image signal input to the image signal input means falls during main scanning, and First reference storage means for storing in advance the correct number of times the test image signal has fallen, and the test image inputted to the image signal input means after a BD signal indicating the start timing of main scanning is generated Clock storage means for storing the count number of the clock generated by the clock generation unit corresponding to the time until the signal finally rises, and generation of the BD signal Second reference storage means for storing in advance the correct count number of the clock corresponding to the time until the last rise of the test image signal is measured, and the number of times measured by the measurement means. Comparing the count number stored in the first reference storage means and comparing the count number stored in the clock storage means with the count number stored in the second reference storage means. And determining means for determining whether there is an error in the controller board. Here, when comparing the number of times measured by the measuring means with the number of times stored in the first reference storage means, it is determined that an error occurs when the two numbers do not match, and the clock storage means When comparing the count number stored in the second storage unit with the count number stored in the second reference storage unit, it can be determined that an error occurs when both count numbers are significantly different.

[0006]

According to the present invention having the above-described structure, for a predetermined test image, the number of times of fall of the test image signal supplied from the outside and the rise of the last test image signal after the generation of the BD signal are obtained. Both the count of the clock corresponding to the measurement and the count are measured and stored. Then, by comparing the measurement result using the test image signal with each predetermined value stored in advance, it is determined whether the test image signal actually transmitted from the outside is appropriate or not, that is, whether or not there is an error. Can be.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating the use of a board test apparatus according to an embodiment of the present invention. In the figure, reference numeral 102 denotes a controller circuit board constituting a controller circuit, and 101 denotes a board test apparatus according to the present embodiment for testing the controller circuit board 102.

In the controller circuit board 102, 1
Numeral 03 denotes a bidirectional interface for receiving text data sent from a host computer (not shown) when the controller circuit board 102 is incorporated in the printer. Numeral 104 denotes a controller circuit board 102 incorporated in the printer. An extended ROM interface section for communicating with the extended ROM board sometimes, an engine interface section 105 for communicating with a printing section in the printer when the controller circuit board 102 is incorporated in the printer, and a reference numeral 112 for the controller circuit board 102 Main control unit for controlling each electronic device, 114
Is a font ROM which is referred to when generating bit image data when the controller circuit board 102 is incorporated in the printer, 113A is a RAM for storing the generated bit image data, and 115 is a main control unit 11
Reference numeral 2 denotes a FIFO memory through which the image signal passes when the bit image data stored in the RAM 113A is output to the printing unit as an image signal.

In the board test apparatus 101, 106
, A main control unit for controlling each block of the board test apparatus 101; 107, a bidirectional interface test circuit; 108, a ROM in which a program to be executed by the main control unit 112 during board test is described; 105 and FIFO memory 115
, An error printer 111 for outputting an error status when the test of the controller circuit board 102 becomes NG, and an error 110 for driving the error printer 111 under the control of the main control unit 106 A printer driver 113B is a RAM.

FIG. 2 is a diagram for explaining the image signal test circuit 109 included in the board test apparatus 101 in detail. Here, 205 is an image signal sent from the controller circuit board 102, 206 is a BD signal for notifying the start timing of main scanning to the controller circuit board 102, and 204 is a BD for generating a BD signal 206 from the main control unit bus 113. A decoder circuit 207; a clock generator 202 for generating a clock pulse having a fixed period;
Is a counter that is cleared to 0 by the BD signal 206 and counts up at the rising edge of the signal output by the clock generator 207, and 203 is an F / F that latches the output value of the counter 202 at the timing when the image signal 205 rises.
(Flip-flop), 201 is a counter that is cleared to 0 by the BD signal 206 and counts up at the falling timing of the image signal 205, 208 is a main control unit that outputs a command output from the main control unit 112 via the engine interface unit 105. To the main control unit 1
This is an interface circuit for transmitting the status returned from 06 to the main control unit 112 via the engine interface unit 105.

Next, the board test apparatus 1 according to the present embodiment
The operation at the time of testing the controller circuit board 102 will be described with reference to FIG.

First, the controller circuit board 102 is connected to the board test apparatus 101, and the power is turned on. Next, the main controller 112 controls the extended ROM interface 10
4 is connected to the extended ROM interface, and the address of the program to be executed only when the ROM 108 is detected is changed from the program area of the ROM incorporated in the main control unit 112 to the program area of the ROM 108. The ROM 108 stores a program for performing a self-diagnosis test of a corresponding device in accordance with a test instruction of each device transmitted from the board test apparatus 101 via the bidirectional interface circuit 103 and returning a test result to the board test apparatus 101. ing.

Main control unit 106 of board test apparatus 101
Indicates that the controller circuit board 102 waits for a test instruction after the power is turned on.
Confirm via 7. Then, the controller circuit board 1
02, the self-diagnosis of the device is sequentially performed, and when an error status is returned, the content of the error is output to the error printer 111 via the error printer driver 110.

As described above, the controller circuit board 1
02 is tested for overall functionality.

Next, a test procedure of an image signal output according to the present embodiment will be described. First, the main control unit 106 instructs the controller circuit board to execute the image signal output test via the bidirectional interface unit. The main control unit 112 creates a predetermined image for test output, and
Store in A.

Next, the main control unit 112 performs the same operation as printing the printing unit when the controller circuit board 102 is incorporated in the printer. That is,
The main control unit 112 outputs a print start command via the engine interface unit 105, and then outputs image data line by line via the FIFO memory 115 in synchronization with a BD signal sent from the printing unit.

On the other hand, the image signal test circuit 109 emulates the operation of the printing section as follows. First, the main control unit 10
6 recognizes from the contents of the interface circuit 208 that a print operation has been requested, and causes the BD decoder circuit 204 to generate a BD signal.

Next, after generating the BD signal, the main control unit 106 waits a sufficiently long interval to complete the transfer of the image signal for one line, and then sets the counter 201 and the F / F 203.
Read the value of. After the counter 201 is cleared to 0 by the BD signal 206, the counter 201 is counted up every time the image signal falls from the high level to the low level. Here, since the low level of the image signal means black data,
The value of the counter 201 indicates whether there is a number of black data clusters in one line of the image signal. Main control unit 1
Reference numeral 06 preliminarily stores a correct value for each line in an internal ROM area.

The F / F 203 stores the value of the counter 202 when the image signal last rises. Since the value of the counter 202 means the time from the occurrence of the BD signal, the F / F 203 has a value proportional to the time from the occurrence of the BD signal to the end of the output of the last black data. Remaining. The main control unit 106 holds a correct value for each line in an internal ROM area, and the F / F
If the value of 203 greatly deviates, it is regarded as an error.

The main control unit 106 completes the test of the image signal output by performing the above diagnosis on all the lines of the image.

[0022]

As described above, according to the present invention, the failure of the controller board can be detected quickly and reliably before the controller board is incorporated into the image forming apparatus main body, so that the assembly cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a connection state when a controller circuit board is tested using a board test apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing the image signal test circuit 109 shown in FIG. 1 in detail.

[Explanation of symbols]

 101 Board Test Apparatus 102 Controller Circuit Board 106 Main Control Unit 107 Bidirectional Interface Test Circuit 108 ROM 109 Image Signal Test Circuit 110 Error Printer Driver 111 Error Printer 113B RAM

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06T 1/00 B41J 5/30 B41J 29/46

Claims (2)

(57) [Claims] 1. An image signal input means for inputting a predetermined test image signal transmitted via an external memory provided on a controller board of an image forming apparatus, and said image signal during main scanning. Measuring means for measuring the number of times that the test image signal input to the input means falls; and first reference storage means for storing in advance the correct number of times that the test image signal falls during main scanning. A clock generated by a clock generator corresponding to a time from when a BD signal indicating a main scanning start timing is generated to when the test image signal input to the image signal input means finally rises Clock storage means for storing the count number of the test signal, and corresponding to the time from when the BD signal is generated until the last rise of the test image signal is measured. A second reference storage unit for storing in advance a correct count number of the clock, and comparing the number measured by the measurement unit with the number stored in the first reference storage unit, Determining means for comparing the count number stored in the clock storage means with the count number stored in the second reference storage means to determine whether there is an error in the controller board; A board test apparatus characterized in that: 2. The board test apparatus according to claim 1, wherein, when comparing the number of times measured by the measuring means with the number of times stored in the first reference storage means, the two numbers of times are compared. When they do not match, it is determined that there is an error, and when comparing the count number stored in the clock storage unit with the count number stored in the second reference storage unit, these two count numbers are greatly shifted. A board test apparatus characterized in that an error is determined when a test is performed.