JPS6237748A - Triagger signal generating system by firmware - Google Patents

Abstract

PURPOSE:To inform a timing to which an abnormal operation is produced to the outside without providing any special circuit, by utilizing some of the address signals transmitted from a CPU as a trigger signal for the start of investigation of the abnormality when the abnormal operation occurs. CONSTITUTION:The highest order bit ADR15 of an address bus 12 consisting of address signal lines ADR0-15 of 16 bits is sent to a trigger signal buffer 23. Then the output of the buffer 23 can be taken to outside directly as a trigger signal. While the program of a working abnormality detecting part 20 is executed by a CPU 10. The control is shifted to a restoring part 22 by a trigger generating part 21 when the abnormality is detected. The part 22 delivers an instruction for the reset to an original program area. Here the highest order bit of the bus 12 is changed by the address signal transmitted from the CPU 10 for the fetching of the instruction. Thus the trigger signal is delivered from the buffer 23.

Description

[Detailed Description of the Invention] [Summary] ROM in which a CPU and firmware program are written
In a system with fixed control processing contents, when an operational abnormality is detected by the firmware program, control is transferred to a program address area that is not accessed by the program during normal operation, and the specified information on the address bus at that time is transferred. By extracting address bit changes as they are to the outside as a trigger signal, an extremely simple hardware circuit configuration is possible.

It is possible to generate a trigger signal that provides an opportunity for diagnosis.

[Industrial application field]

The present invention relates to a firmware-based trigger signal generation method, particularly to a control system using a microcomputer incorporated in, for example, a channel device or various control devices. This invention relates to a trigger signal generation method using firmware that can be generated at any time.

[Conventional technology and problems]

FIG. 3 shows an example of the conventional method. In the figure, lo is CPU, 1
1 is ROM (Read Only Memory),
12 is an address bus, 13 is a data bus, 14 is an address decoder, and 15 is a flip-flop (FF).

16 represents a not circuit, 17 represents an address decoder, and 18 represents a read buffer.

The system circuit shown in FIG. 3 is a circuit incorporated in, for example, a channel device or various other control devices, and includes
The content of the control processing is fixed. In general purpose computers.

When an abnormality occurs, it is relatively easy to analyze it because the phenomenon of the abnormality is often clearly visible externally, programs can be loaded freely, and input/output devices such as printers are provided. It is possible to collect data.

However, in a system like the one shown in Figure 3, in which the firmware program is stored in the ROM 1l, the control processing contents are closed internally, so it is not easy to investigate the cause of the abnormality when an abnormality occurs. do not have.

For example, suppose that a readable/writable register made up of the flip-flop 15 is periodically operated by a program stored in the CPUI<ROM 11. If writing to the register is not done correctly, the CP
By performing a read check, Ul0 can determine that the written information is incorrect.

However, according to the conventional method, since there is no means for notifying the outside as a hardware signal, there is no opportunity to conduct an investigation such as waveform measurement when an abnormality occurs. Therefore, when investigating such cases,
Conventionally, there has been a problem in that a large-scale system such as a CPU emulator is required, and the cost required for investigation is also large.

[Means for solving problems]

The present invention aims to solve the above-mentioned problems, and focuses on using a part of the address signal sent from the CPU as a trigger signal as it is, so that the timing of abnormal operation can be detected externally without providing any special circuit. Provide a means of notification.

FIG. 1 shows a basic configuration diagram of the present invention.

In FIG. 1, the same reference numerals as in FIG. 3 correspond to those shown in FIG. IIA is a normal access area in ROMII in which a firmware program executed in normal times is stored, and 11B is an abnormality access area in ROMII in which a program to which control is transferred only in an abnormality is stored.

Reference numeral 20 denotes an operation abnormality detection unit that detects an operation abnormality by a program, 21 a trigger generation unit that generates a trigger signal by issuing a command to transfer control to the abnormality access area 11B, and 22 a so-called return command.
A recovery section 23 that returns control to the original program represents a trigger signal buffer.

In the case of the present invention 9, for example, the most significant bit ADR15 of the address bus 12 is connected to the trigger signal buffer 23 and outputs the trigger signal buffer 23.

It is designed so that it can be taken out as is as a trigger signal.

The program of the operational abnormality detection unit 20 is executed by the cpuiO, and when an operational abnormality is detected, the trigger generation unit 21 transfers control to the recovery unit 22. The recovery unit 22 is 1
For example, it is provided in the abnormal access area 11B having an address value larger than address 8000 and issues an instruction to return to the original program area, but at this time, an address signal sent by the CPU I O for instruction fetch is used.

Since the most significant bit of address bus 12 changes.

A trigger signal is output from the trigger signal buffer 23.

[Effect]

The trigger generation section 21 may be something like a subroutine call instruction that simply calls the recovery section 22.

Further, the recovery unit 22 may be a return command or the like.

The circuit for actually outputting the trigger signal to the outside is also the first one.
As can be seen from the figure, it is sufficient to simply extract one of the address signals to m, and as a result, the trigger generation section 21 calls the restoration section 22, and when the address signal changes,
A trigger signal will be issued.

(Embodiment J FIG. 2 does not show a time chart 1 of an embodiment of the present invention. Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

Atoshi Suhas 12 is 1 In this example, 16hi 2.l.
It is composed of address signal lines ADRO-15. C
P U I O sends out an address bus 12 and fetches an instruction from ROM 11 via data bus 13 for execution.

The ROM II is divided into a normal access area 11A starting from address 7FFF (hexadecimal number) and an abnormal access area 11B starting from address 8000. A firmware program that performs normal processing.

Normally, the data is stored in the eye area 11A4. Also.

The firmware program stored here.

An operational abnormality detection section 20 and a trigger generation section 21.

Incorporated.

Flip-flops 15 and 2 are, for example, registers in which output data to a circuit to be controlled is set. CPU 1
0 writes to this register, as shown in FIG. 1.
Raise strobe signal STB. Address decoder 14
is for selecting register writing, and this output a is.

This is the logical product of the address signal from CPUIO, the strobe signal STB, and the read/write signal R/W. By output a, the data is sent to the buffer knob 15.
be done.

For example, after register writing, the operation abnormality detection unit 20
To detect malfunctions, the same registers are read and their contents are compared. For reading, CPU
l0 outputs the address of the address bus 12/\flip-flop 15, and raises a strobe signal ST''B4 indicating that the 5th address is valid with the read/write fz number R/W set to "L".Address decoder 17 is
This selects register reading, and this output C goes to "L5" in synchronization with the slave signal STB.

As a result, the contents of the solinobfrob 15 are sent to the data bus 13 via the read buffer 18 as read data d.

To determine register abnormality, the previously written data, etc.
The read data d is compared with the read data d. If there is a difference in content,
7 The operation abnormality detection unit 20, which indicates that an operation abnormality has occurred,
When an abnormality in operation is detected, the trigger generating section 21 is activated, and the process branches to the recovery section 22 set in advance from address 8000 onwards. Therefore, the iM old section 22 will quickly return to the original program.

At this time, because the recovery unit 22 fetches the instruction, the most significant bit ADR15 of the address bus 12 changes from “L” to “H”.
” and returns to “L” again upon recovery.

Therefore, the trigger signal buffer 23 outputs a trigger signal pulse.

By using this signal as a manual trigger for a measuring instrument such as a synchroscope or logic state analyzer, even if the abnormality occurs only infrequently or only 2, it is possible to observe waveforms related to the abnormality. , etc.

Note that in this embodiment, the operational abnormality detection section 20 is as follows.

By comparing the writing day/evening and the reading day/evening.

Although ζJ is designed to detect an abnormality, the present invention is not limited to this, and various abnormality detection means such as a screwdriver, 6J, etc. can be employed.

(Effects of the Invention) According to the above-mentioned 1↓, uni, misfire 1suj,, 2nd diagnosis trii, i11, an abnormal state occurs due to deep logic or sequential sequence without providing special circuits.

Alternatively, the timing of an abnormal operation that can only be determined by firmware can be easily extracted as a trigger signal. Due to this.

It is now possible to capture hardware and software behavior when a problem occurs using logic state analyzers, synchroscopes, etc., making it easier to investigate faults and reducing the large amount of costs traditionally required for investigation. becomes possible.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention, and FIG. 2 is a time chart of an embodiment of the present invention. FIG. 3 is a diagram showing an example of a conventional system. In the figure, 10 is a CPU, 11 is a ROM, IIA is a normal access area, IIB is an abnormal access area, 12 is an address bus, 13 is a data bus, 14 is an address decoder, and 15 is a flip-flop. 16 is a not circuit, 17 is an address decoder, 18 is a read buffer, and 20 is an operation abnormality detection section. Reference numeral 21 represents a trigger generation section, 22 a recovery section, and 23 a trigger signal buffer.

Claims (1)

[Claims] In a system equipped with a CPU (10) chip, a ROM (11) in which a firmware program is written that is read out by an address signal from the CPU (10), and peripheral circuits controlled by them. , In the process in which the CPU (10) reads and executes a series of firmware programs from the ROM (11),
Means for detecting abnormal operation by the program (20
), and when an abnormality in operation is detected by the detection means (20),
means (21) for issuing an instruction to read a program from a program address area that is not accessed by the program during normal times; A trigger signal generation method using firmware, characterized in that the method is characterized by comprising means (23) for outputting to the outside as a trigger signal.