JP3128829B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a DRA in which a memory cell is formed in an element forming region on a silicon substrate.
The present invention relates to a semiconductor memory device such as an M (dynamic RAM).

[0002]

2. Description of the Related Art In recent years, as semiconductor memory devices such as DRAMs have become more highly integrated, stacked capacitors having a stacked (stacked) capacitor structure for storing information have been used to secure the capacity. Has begun. Also, attention has been focused on an efficient open bit line type cell arrangement in reducing the cell area and integrating the memory device itself.

In a conventional stacked-capacitance type semiconductor memory device having an open bit line structure, as shown in FIG. 12, an impurity diffusion region of a switching element Tr faces a surface of a silicon substrate 42 on which a field insulating layer 41 is formed. A bit line 45 made of, for example, an Al wiring layer is connected to one of the source / drain regions 43 a of the impurity diffusion regions via a contact hole 44.
The capacitor lower electrode 46 of the stacked capacitor C is connected to the other source / drain region 43b.

The capacitor lower electrode 46 is formed by patterning a second polycrystalline silicon layer. Each gate electrode (word line) of the switching element Tr is a first polycrystalline silicon layer. The upper part 47 is formed via an interlayer insulating layer 48. The capacitor lower electrode 46 has a capacitor upper electrode 49 serving as a common electrode on the upper side of the capacitor lower electrode 46 via a dielectric film 50. The capacitor lower electrode 46 has a laminated structure of the capacitor 49, the dielectric film 50, and the capacitor lower electrode 46. A stacked capacitor C is configured. Here, one memory cell MC is constituted by the switching element Tr and the stacked capacitor C formed on the silicon substrate 42.

In this semiconductor memory device, necessary charges are accumulated in the stacked capacitor C, and reading and writing are performed via the bit line 45 while being controlled by the switching element Tr. still,
Reference numeral 51 denotes a shunt (lining) metal wiring for lowering the resistance of the word line 47, and reference numeral 52 denotes an interlayer insulating film made of SiO ₂ or the like.

[0006]

However, in the conventional semiconductor memory device, with the progress of integration,
The following problems occur.

That is, since it is necessary to make contact between the upper bit line 45 and the source / drain region 43a, a capacitor lower electrode 46 and a capacitor upper electrode 49 constituting the stacked capacitor C are formed between the bit line 45 and the silicon substrate 42. Need to be formed avoiding the contact portion. For this reason, the portion occupied by the capacitor in the memory cell MC is squeezed, and it is difficult to secure a sufficient cell capacity.

Since the bit line 45 exists between the capacitor upper electrode 49 and the metal wiring 51, the bit line 45 is connected to the capacitor upper electrode 49 and the word line 47 when the bit line 45 is charged and discharged. Cause interference,
This appears as interference noise, and there is a problem that even when the voltage applied to the word line 47 is at a high level, the interference noise is applied to the bit line 45. These interference noises are generated by being entangled with the bit line 45 and cause a disadvantage of deteriorating data. In particular, the interference noise is remarkable when the open bit line structure targeted at this time is used.

In the case of the conventional semiconductor memory device, since a number of wirings are stacked on the silicon substrate 42, the distance m between the shunt metal wiring 51 and the silicon substrate 42 is increased. Generally, metal wiring for shunt 5
1 is also used for connection to a peripheral circuit, etc., but as described above, when the distance m between the metal wiring 51 and the silicon substrate 42 increases, a low-resistance contact between the metal wiring 51 and the silicon substrate 42 in the peripheral circuit. The formation becomes difficult, and the step coverage of the metal wiring 51 is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. It is an object of the present invention to increase the capacity of a stacked capacitor in an open bit line structure and to reduce interference noise between wirings. It is an object of the present invention to provide a semiconductor memory device capable of suppressing the above and promoting the high integration of the memory device itself.

[0011]

The present invention SUMMARY OF], in a semiconductor memory device A memory cell MC ₁ and MC ₂ in the semiconductor layer 1 on the substrate 15 is formed, the lower portion of the semiconductor layer 1, the first insulating It is formed through the layer 10, and which has a memory cell MC ₁ and MC ₂ and bit line 2 is electrically connected to the lower portion of the bit line 2, the second insulating layer 1
0 (26) through the band-shaped bit line shield conductor 1
The bit line shielding conductor 12 has
And projecting toward the first insulating layer 10 through
A power supply for the bit line shield is supplied to the bit line shield conductor 12 from the back surface of the base 15.
Further, the present invention provides the semiconductor memory device A
15 is formed by bonding the silicon substrates 13 and 15 together.
It is permissible to adopt a different configuration.

[0012]

According to the structure of the present invention described above, the bit line 2 is formed below the semiconductor layer 1 on which the switching elements Tr ₁ and Tr ₂ are formed via the first insulating layer 10. there is no possibility of short circuit between cells MC ₁ and the word lines 4a and 4b and the contact portion 3 of the bit lines of the MC _2, in conjunction with this, alignment margin between them is not necessary, that much memory cells MC ₁ and The area of the MC ₂ can be reduced.

Also, the stacked capacitors C ₁ and C ₂
It is not necessary to avoid the bit line contact portion 3 when forming the semiconductor memory device. Therefore, the occupied portions of the stacked capacitors C ₁ and C _{2 in} the memory cells MC ₁ and MC ₂ can be increased to increase the cell capacitance. can, be reduced the area of the memory cell MC ₁ and MC _2, it is possible to secure a predetermined cell capacity.

Since the bit line 2 is not formed above the memory cells MC ₁ and MC ₂ , the memory cell MC has a thickness corresponding to the thickness of the bit line 2 and the interlayer insulating layer formed between the bit line 2 and the metal wiring 32. The separation distance D between the metal wiring 32 on the ₁ and MC ₂ sides and the silicon substrate 15 is reduced.
As a result, it is possible to promote a reduction in resistance in connecting the metal wiring 32 to the peripheral circuit, and to improve the step coverage of the metal wiring 32.

Further, even if the distance between the bit line 2 and the word lines 4a and 4b is increased, the memory cells MC ₁ and MC ₂
The above-mentioned increase can be achieved because there is no effect on the upper step coverage and the like, and the memory cells MC ₁ and MC
_{2 Since} there is no bit line ₂ above, the bit line 2
From the word lines 4a and 4b and the stacked capacitor C ₁ ,
The interference noise on C ₂ and the interference noise on the bit line 2 due to the potential states of the word lines 4a and 4b and the parasitic capacitance are reduced.

Further, a conductor 12 for shielding a bit line is penetrated between the respective bit lines 2 so as to penetrate between the respective bit lines 2 to form a first insulating layer.
Since it is interposed so as to protrude toward 10, the interference noise between the bit lines 2 can be suppressed, and the deterioration of data can be prevented.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a plan view showing a main part of a semiconductor memory device A, particularly a DRAM, according to the present embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. −
It is sectional drawing on the B line.

As shown in FIG. 1, the memory device A includes:
A bit line (shown by a broken line) extending in the lateral direction at a central portion of the element forming region 1 surrounded by an insulating layer made of SiO ₂ or the like.
2, two word lines 4a and 4b extending in the vertical direction are formed left and right with the contact part 3 with the contact part 3 being symmetrical, and as shown in FIG. by the source and drain regions 5c and on the drawing, the storage node via the insulating layer 6 on the switching element Tr ₁ which is composed of the source and drain regions 5a of the word lines 4a right N-type polycrystalline silicon layer 1 One electrode (hereinafter simply referred to as a storage node electrode) 7a
Is formed, and the storage node electrode 7a is electrically connected to the source / drain region 5a. Further, the other word line 4b, the source / drain region 5c in the contact portion 3, and the N on the left side of the word line 4b in the drawing.
The storage node electrode 7 via the insulating layer 6 on the switching element Tr ₂ composed of the source / drain region 5 b
b is formed, and the storage node electrode 7b and the source
The drain region 5b is electrically connected.

On the upper surface including the storage node electrodes 7a and 7b, a cell plate electrode 9 of a common electrode made of a polycrystalline silicon layer is formed via a thin dielectric film 8 such as SiO ₂ or SiN. plate electrode 9, the dielectric film 8 and the storage node electrode 7a, between 7b, respectively stacked capacitor C ₁ and C ₂ is formed.

The switching elements Tr ₁ ,
Tr ₂ and stacked capacitors C ₁ , C _{2 form} two memory cells MC ₁ , MC ₂ , respectively, and these memory cells MC ₁ , MC ₂ are connected to word lines 4 a, 4 b and bit lines, as shown in FIG. The so-called open bit line type array is formed at all intersections of the line 2.

In this embodiment, as shown in FIG. 2, the bit line 2 is formed under the element forming region 1 via the insulating layer 10, and the bit line 2 and the source / source in the element forming region 1 are formed. The drain region 5c is, for example, poly plug
The contact portions 3 for the bit lines 2 are formed directly under the element forming region 1 by being electrically connected by a polycrystalline silicon layer 11 by technology. As shown in FIG. 3, a shield electrode 12 of a polycrystalline silicon layer is formed between each bit line 2 via an insulating layer 10 along the bit line 2. This shield electrode 12
Is the polycrystalline silicon layer 1 formed under the insulating layer 10
3 and a strip-shaped electrode portion 14 projecting upward from the polycrystalline silicon layer 13 toward the insulating layer 10 between the bit lines 2. The shield electrode 12 is electrically fixed by the potential Vcc or Vss supplied from the back surface of the silicon substrate 15 immediately below the polycrystalline silicon layer 13.

Next, a method of manufacturing the semiconductor memory device A according to the present embodiment will be described with reference to FIGS. 1 and 2 are denoted by the same reference numerals.

Here, the process flow charts shown in FIGS.
The cross section in the same direction as FIG.
The process flow diagram shown in FIG. 11 is directed to a cross section in the same direction as that of FIG. 2. In the description of this manufacturing method, FIGS. 4 to 7 and FIGS. I will explain it.

First, as shown in FIGS. 4A and 8A, the silicon surface of a predetermined portion on the silicon substrate 21, in this example, a portion to be an element isolation region is selectively etched away, for example, by about 2000 ° to form the concave portion 22. After that, thermal oxidation is performed on the entire surface to form a thermal oxide film (corresponding to the thickness from the silicon surface to the broken line in the drawing) 23 on the entire surface. Thereafter, an insulating layer 24 made of SiO ₂ is formed by, for example, a CVD method. Hereinafter, the thermal oxide film 23 and the insulating layer 24 are simply referred to as the insulating layer 10.

Next, as shown in FIGS. 4B and 8B, an opening 25 penetrating through the insulating layer 10 is provided at each central portion of a portion to be the element forming region 1 on the silicon substrate 21. Thereafter, the polycrystalline silicon layer 11 is formed on the entire surface so as to fill the openings 25 by a CVD method or the like, and then etched back to bury the polycrystalline silicon layers 11 in the openings 25 (poly plug technology). After that, a tungsten (W) polycide layer 2 for bit lines and an insulating layer 26 made of SiO ₂ are sequentially laminated on the entire surface, and then cut with the same mask, on the polycrystalline silicon layer 11 embedded in each opening 25. Then, the tungsten (W) polycide layer 2 and the insulating layer 26 are left. At this time, the tungsten (W) polycide layer 2 becomes the bit line 2.

Next, as shown in FIG. 4C, an SiO ₂ film is formed on the entire surface and then etched back to form an SiO ₂ film 27 on the side wall of the bit line 2. That is, the sidewall 27 is formed. At this time, the above-mentioned etch back is performed between overetches so that the concave portion 28 can be formed on the upper surface of the insulating layer 10.

Next, as shown in FIGS. 5A and 9A, after a polycrystalline silicon layer 13 is deposited on the entire surface, the surface of the polycrystalline silicon layer 13 is planarized by a known planarizing technique (for example, polishing or the like). I do. This polycrystalline silicon layer 1
Numerals 3 are also deposited between the side walls 27 of the bit lines 2 to form a shield electrode 12 for suppressing interference noise between the bit lines 2 shown in FIG.

Next, as shown in FIGS. 5B and 9B, another silicon substrate 15 is bonded to the end surface of the flattened polycrystalline silicon layer 13, and selective polishing is performed from the back surface of the other silicon substrate 21. Do. This selective polishing is performed on the insulating layer 1.
Repeat until 0 is exposed. By this selective polishing, an island-shaped thin silicon layer surrounded by the insulating layer 10, that is, the element formation region 1 is formed, and the element isolation region 28 is formed by the insulating layer 10.

Next, as shown in FIGS. 6A and 10A,
After performing thermal oxidation on the entire surface to form a thin thermal oxide film, that is, a gate insulating film 29 on the surface of the element forming region 1, word lines 4a and 4b of a polycrystalline silicon layer are formed by patterning. Thereafter, using the word lines 4a and 4b as masks, for example, N-type impurities are ion-implanted to form three source / drain regions 5a, 5b and 5c in the element forming region 1, respectively. At this time, the switching element Tr ₁
And Tr ₂ are formed.

Next, as shown in FIGS. 6B and 10B,
After an insulating layer 6 made of SiO ₂ or the like is formed on the entire surface, openings 30 penetrating the insulating layer 6 are formed at locations corresponding to the source / drain regions 5a and 5b. After that, a second-layer polycrystalline silicon layer is formed on the entire surface and then patterned to form storage node electrodes 7a and 7b. At this time, the storage node electrodes 7a and 7b are formed relatively wide so that the distance d between them is substantially equal to or slightly larger than the opening width W of the contact portion 3 of the bit line 2.

Next, as shown in FIGS. 7 and 11, a thin dielectric film 8 is formed on the entire surface including the storage node electrodes 7a and 7b.
Is formed by, for example, a low pressure CVD method or the like, and a cell plate electrode 9 of a common electrode made of a polycrystalline silicon layer is formed on the dielectric film 8.

Then, as shown in FIGS. 2 and 3, after an interlayer film 31 made of SiO ₂ or the like is formed on the entire surface, a metal wiring 32 for shunt for lowering the resistance of the word lines 4a and 4b is formed. The semiconductor memory device A according to this embodiment is obtained by patterning. In FIGS. 2 and 3, the insulating films 10, 26, and 27 in FIGS. 7 and 11 are collectively shown as the insulating film 10.

As described above, according to this embodiment, the bit line 2 is
Since it is formed below the element forming region 1 with the insulating layer 10 interposed therebetween, there is no risk of short-circuit between the bit line contact portion 3 and the word lines 4a and 4b. This makes it unnecessary alignment margin between them, can be reduced the area of the memory cell MC ₁ and MC ₂ correspondingly.

The stacked capacitors C ₁ and C ₂
It is not necessary to avoid the contact portion 3 for the bit line when forming the memory cell, so that the occupied portion of each of the stacked capacitors C ₁ and C _{2 in} the memory cells MC ₁ and MC ₂ can be increased, and the cell capacity accompanying this can be reduced. can be increased, even by reducing the area of the memory cell MC ₁ and MC _2, it is possible to secure a predetermined cell capacity.

Since the bit line 2 is not formed above the memory cells MC ₁ and MC ₂ , the bit line 2 and an interlayer insulating layer formed between the bit line 2 and the metal wiring 32 (the interlayer insulating layer 52 in FIG. 12) Metal wiring 32 on the memory cells MC ₁ and MC ₂ side and the silicon substrate 1
5 (see FIG. 2) is reduced. As a result, it is possible to promote a reduction in resistance in connecting the metal wiring 32 to the peripheral circuit, and to improve the step coverage of the metal wiring 32.

Further, even if the distance between the bit line 2 and the word lines 4a and 4b is increased, the memory cells MC ₁ and MC ₂
The above-mentioned increase can be achieved because there is no effect on the upper step coverage and the like, and the memory cells MC ₁ and MC
_{2 Since} there is no bit line ₂ above, the bit line 2
From the word lines 4a and 4b and the stacked capacitor C ₁ ,
The interference noise on C ₂ and the interference noise on the bit line 2 due to the potential states of the word lines 4a and 4b and the parasitic capacitance are reduced.

Further, a conductor 12 for shielding a bit line is penetrated between the respective bit lines 2 so that the insulating layer 10
, The interference noise between the bit lines 2 can be suppressed, and the deterioration of data due to the interference noise can be prevented.

As described above, the semiconductor device A according to this embodiment
According to, reduction of area of the memory cell MC ₁ and MC _2, increase in the cell capacity, Hakare suppression of interference noise between the wires, it is possible to obtain the degree of integration as well as highly reliable semiconductor memory device A .

In the above embodiment, the D of the open bit line structure is
Although an example in which the present invention is applied to a RAM has been described, it is needless to say that the present invention is also applicable to a DRAM having a folded bit line structure.

[0041]

According to the semiconductor memory device of the present invention, in the open bit line structure, the capacity of the stacked capacitor can be increased, interference noise between wirings can be suppressed, and the height of the semiconductor memory device itself can be improved. Integration and high reliability can be achieved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a main part of a semiconductor memory device according to an embodiment.

FIG. 2 is a sectional view taken along line AA in FIG. 1;

FIG. 3 is a sectional view taken along line BB in FIG. 1;

FIG. 4 is a process flow diagram (part 1) showing the method for manufacturing the semiconductor memory device according to the present embodiment in the same sectional direction as in FIG. 3;

FIG. 5 is a process flow diagram (part 2) illustrating the method of manufacturing the semiconductor memory device according to the present embodiment in the same sectional direction as in FIG. 3;

FIG. 6 is a process flow diagram (part 3) illustrating the method for manufacturing the semiconductor memory device according to the present embodiment in the same sectional direction as in FIG. 3;

FIG. 7 is a process flow diagram (part 4) showing the method for manufacturing the semiconductor memory device according to the present embodiment in the same sectional direction as in FIG. 3;

FIG. 8 is a process flow diagram (part 1) showing the method for manufacturing the semiconductor memory device according to the present embodiment in the same sectional direction as in FIG. 2;

FIG. 9 is a process flow diagram (part 2) showing the method for manufacturing the semiconductor memory device according to the present embodiment in the same sectional direction as in FIG. 2;

FIG. 10 is a process flow diagram (part 3) illustrating the method of manufacturing the semiconductor memory device according to the present embodiment in the same cross-sectional direction as in FIG. 2;

FIG. 11 is a process flow diagram (part 4) illustrating the method for manufacturing the semiconductor memory device according to the present embodiment in the same sectional direction as in FIG. 2;

FIG. 12 is a configuration diagram showing a semiconductor memory device according to a conventional example.

[Explanation of symbols]

A Semiconductor memory device MC ₁ and MC ₂ Memory cell Tr ₁ and Tr ₂ Switching element C ₁ and C ₂ Stacked capacitor 1 Element formation area 2 Bit line 3 Contact part 4a and 4b Word line 5a-5c Source / drain area 6 and DESCRIPTION OF SYMBOLS 10 Insulating layer 7a and 7b Storage node electrode 8 Dielectric film 9 Cell plate electrode 11 and 13 Polycrystalline silicon layer 12 Shield electrode 14 Electrode part 15 Silicon substrate

Continuation of the front page (56) References JP-A-64-89559 (JP, A) JP-A-2-35771 (JP, A) JP-A-2-240949 (JP, A) JP-A-63-283157 (JP) JP-A-4-217361 (JP, A) JP-A-4-118967 (JP, A) JP-A-4-94160 (JP, A) JP-A-2-60163 (JP, A) JP-A-1-225353 (JP, A) JP-A-1-179449 (JP, A) JP-A-1-149452 (JP, A) JP-A-64-67956 (JP, A) JP-A-63-269565 (JP, A A) JP-A-63-232459 (JP, A) JP-A-63-232458 (JP, A) JP-A-63-157463 (JP, A) JP-A-61-88554 (JP, A) JP-A-60 -227461 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04 H01L 27/12

Claims (2)

(57) [Claims] 1. A semiconductor memory device in which a memory cell is formed in a semiconductor layer on a substrate, wherein the memory cell is formed below a semiconductor layer with a first insulating layer interposed therebetween.
And a bit line electrically connected to the memory cell, and below the bit line via a second insulating layer.
A strip-shaped bit line shielding conductor ;
The conductor for the shield penetrates between each bit line and forms the first insulating layer.
A semiconductor memory device protruding toward the semiconductor device , wherein a power supply for bit line shielding is supplied to the conductor for bit line shielding from a back surface of the base. 2. A substrate is bonded to a silicon substrate.
2. The half according to claim 1, wherein the half is formed.
Conductive memory device.