JP3127448B2 - Etching control method - Google Patents
Etching control methodInfo
- Publication number
- JP3127448B2 JP3127448B2 JP02130158A JP13015890A JP3127448B2 JP 3127448 B2 JP3127448 B2 JP 3127448B2 JP 02130158 A JP02130158 A JP 02130158A JP 13015890 A JP13015890 A JP 13015890A JP 3127448 B2 JP3127448 B2 JP 3127448B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- epitaxial film
- layer
- type layer
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005530 etching Methods 0.000 title claims description 38
- 238000000034 method Methods 0.000 title claims description 7
- 239000010410 layer Substances 0.000 description 26
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Landscapes
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、ｐ−ｎ接合を有するエピタキシャル膜のエ
ッチング操作を制御する方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for controlling an etching operation of an epitaxial film having a pn junction.
（従来の技術） 従来は、エピタキシャル膜を一定のエッチング条件の
下でエッチング時間のみ変化させてエッチング操作を行
い、得られたエピタキシャル膜を段差計等を用いてエッ
チング深さを測定し、予め、エッチング時間とエッチン
グ深さの関係を調べておき、現実のエッチング操作にお
いては、エッチング時間により、エッチング深さを推測
していた。(Prior art) Conventionally, an etching operation is performed by changing only an etching time of an epitaxial film under a constant etching condition, and an obtained epitaxial film is measured for an etching depth using a step gauge or the like, and The relationship between the etching time and the etching depth was examined, and in an actual etching operation, the etching depth was estimated based on the etching time.
（発明が解決しようとする課題） しかし、上記の方法では、ウエハ面内でエピタキシャ
ル膜の厚さに分布がある場合、エッチング深さを正確に
測定することができても、残留エピタキシャル膜の厚さ
を検知することができず、ｐ層若しくはｎ層を一部残し
たままエッチング操作を終了させたり、次の層を誤って
エッチングすることがしばしばあった。特に、ヘテロバ
イポーラトランジスタのように、第２層目（ベース層）
が非常に薄く、かつ、異種材料で構成されている場合な
どにおいては、エッチング速度が異なることもあり、第
２層目までエッチングしてしまい、所定の特性を得るこ
とができないことがあり、歩留まりを大きく低下させる
原因となっていた。(Problems to be Solved by the Invention) However, in the above method, when the thickness of the epitaxial film has a distribution in the wafer surface, even if the etching depth can be accurately measured, the thickness of the residual epitaxial film can be accurately measured. It was not possible to detect the thickness, and the etching operation was often terminated while leaving a part of the p-layer or the n-layer, or the next layer was often erroneously etched. In particular, the second layer (base layer) like a hetero bipolar transistor
In the case where is very thin and is made of a different material, the etching rate may be different, and etching may be performed up to the second layer, so that predetermined characteristics may not be obtained. Was greatly reduced.
そこで、本発明は、上記の欠点を解消し、エピタキシ
ャル膜のエッチング深さではなく、残留エピタキシャル
膜の厚さを検知して、確実なエッチング制御を可能にす
る方法を提供しようとするものである。Accordingly, the present invention is intended to solve the above-mentioned drawbacks, and to provide a method for detecting the thickness of the residual epitaxial film instead of the etching depth of the epitaxial film and enabling reliable etching control. .
（課題を解決するための手段） 本発明は、ｐ−ｎ接合を有するエピタキシャル膜のう
ち、表面側のエピタキシャル膜のエッチング操作を制御
する方法において、エピタキシャル膜表面に電極を２つ
形成し、該電極間の電流を測定することにより、表面側
のエピタキシャル膜の厚さを検知して、前記電極領域を
除いた前記表面側のエピタキシャル膜をエッチングする
操作を終了することを特徴とするエッチングの制御方法
である。(Means for Solving the Problems) The present invention provides a method for controlling an etching operation of an epitaxial film on a surface side of an epitaxial film having a pn junction, comprising: forming two electrodes on the surface of the epitaxial film; By controlling the current between the electrodes, the thickness of the epitaxial film on the front surface is detected, and the operation of etching the epitaxial film on the front surface excluding the electrode region is completed. Is the way.
（作用） 第１図は、本発明に係る残留エピタキシャル膜厚の測
定原理の説明図であり、第２図は、エッチングがある程
度進行した状態における試料片の斜視図である。第１図
の試料片は、基板の上にｎ型層及びｐ型層を順に積層し
たもので、ｐ型層の上に電極を２つ設けて電極間に電位
を与えると、電流は矢印のように、表面層のｐ型層内を
流れるが、ｎ型層には流れない。ｎ型層を流れようとす
る電流は、ｐ−ｎ−ｐ接合を介して流れることになり、
電界の方向にかかわらず、ｐ−ｎ接合又はｎ−ｐ接合の
一方が逆バイアスになるために電流を流すことができな
いからである。ｎ型層とｐ型層が逆の場合も全く同様の
ことがいえる。そこで、ｐ型層の露出した表面を一定時
間エッチングしてから、取り出し、ｐ型層表面の電極間
に電位を与えて電流を測定する操作を繰り返し、それぞ
れのＩ−Ｖ特性をみると、エッチング前には、当初のｐ
型層の抵抗に相当する傾きを示すが、エッチングの進行
に伴い、この傾きは小さくなり、エッチング領域のｐ型
層が完全に除かれると、傾きがゼロになり、ｐ−ｎ接合
のＩ−Ｖ特性を示すので、エッチングの終了点を正確に
検知することができる。それ故、第２層目のｎ型層まで
エッチングすることはなくなる。(Operation) FIG. 1 is an explanatory view of the principle of measuring the residual epitaxial film thickness according to the present invention, and FIG. 2 is a perspective view of a sample piece in a state where etching has progressed to some extent. The sample piece of FIG. 1 is obtained by sequentially laminating an n-type layer and a p-type layer on a substrate. When two electrodes are provided on the p-type layer and a potential is applied between the electrodes, the current is indicated by an arrow. Thus, it flows in the p-type layer of the surface layer, but does not flow in the n-type layer. The current that is going to flow through the n-type layer will flow through the pnp junction,
This is because, regardless of the direction of the electric field, current cannot flow because one of the pn junction and the np junction is reverse biased. The same can be said for the case where the n-type layer and the p-type layer are reversed. Therefore, the operation of etching the exposed surface of the p-type layer for a certain period of time, taking out the surface, applying a potential between the electrodes on the surface of the p-type layer, and measuring the current is repeated. Before, the original p
It shows a slope corresponding to the resistance of the mold layer, but this slope becomes smaller as the etching proceeds, and the slope becomes zero when the p-type layer in the etched region is completely removed, and the I- Since the V characteristic is shown, the end point of the etching can be accurately detected. Therefore, the second n-type layer is not etched.
このように、本発明は、表面のｐ型層の残留厚さに対
応する電流を測定しているので、単にエッチング深さを
測定する従来法に比べて、仕上がりのデバイスにより近
い形で測定することになり、エッチング制御の精度が向
上するとともに、一定の特性を有するデバイスを歩留ま
り良く製造することができるようになる。As described above, since the present invention measures the current corresponding to the residual thickness of the p-type layer on the surface, the current is measured in a form closer to the finished device than in the conventional method of simply measuring the etching depth. As a result, the accuracy of the etching control is improved, and devices having certain characteristics can be manufactured with high yield.
（実施例） ｐ型GaAs基板の上に厚さ0.5μｍのｐ型GaAs、さらに
その上に厚さ0.5μｍのｎ型GaAsを積層し、底面にAu−Z
n合金のｐ型電極を、上面にAu−Ge−Ni合金のｎ型電極
を２つ形成した試料片を用い、HF:H2O2:H2O＝1:1:15の
組成比を有するエッチング液に第３図の各時間だけ試料
片を浸漬し、その都度エッチング液から取り出して２つ
のｎ型電極間の電流を測定すると、エッチング前には、
第３図（ａ）のＩ−Ｖ特性を示すが、エッチングを開始
すると、ｐ型層の露出した部分が第１図の点線のように
エッチングされ、60秒後、120秒後、180秒後、210秒後
のＩ−Ｖ特性は、同図（ｂ）〜（ｅ）に示すように、エ
ッチングの進行に伴い、ｐ型層の抵抗に相当する傾きが
小さくなり、220秒後には、同図（ｆ）に示すように、
傾きがゼロになり、ｐ−ｎ接合のＩ−Ｖ特性を示す。即
ち、この段階で表面層のｐ型層が完全にエッチングされ
たことが確認されたので、エッチングを終了した。(Example) On a p-type GaAs substrate, a 0.5 μm-thick p-type GaAs and a 0.5 μm-thick n-type GaAs are further stacked, and the Au-Z
Using a sample piece in which two n-type electrodes of Au-Ge-Ni alloy were formed on the p-type electrode of n-alloy, the composition ratio of HF: H 2 O 2 : H 2 O = 1: 1: 15 Each of the sample pieces was immersed in the etching solution for each time shown in FIG. 3, and was taken out of the etching solution each time and the current between the two n-type electrodes was measured.
FIG. 3 (a) shows the IV characteristics. When the etching is started, the exposed portion of the p-type layer is etched as shown by the dotted line in FIG. 1, and after 60 seconds, 120 seconds and 180 seconds And the IV characteristic after 210 seconds, the slope corresponding to the resistance of the p-type layer becomes smaller as the etching progresses, as shown in FIGS. As shown in FIG.
The slope becomes zero, indicating the IV characteristics of the pn junction. That is, since it was confirmed at this stage that the p-type layer of the surface layer was completely etched, the etching was terminated.
（発明の効果） 本発明は、上記の構成を採用することにより、表面層
の残留厚さに対応する抵抗を測定することになるので、
単にエッチング深さを測定する従来法に比べて、仕上が
りのデバイスにより近い形で測定でき、エッチング制御
を極めて精確に行うことができる。特に、ヘテロバイポ
ーラトランジスタのように、第２層目が薄いときに、こ
れをエッチングすることなく、第１層目のみを確実に除
去することができ、エッチング工程における歩留まりを
向上させることができる。(Effects of the Invention) The present invention measures the resistance corresponding to the residual thickness of the surface layer by adopting the above configuration,
Compared to the conventional method of simply measuring the etching depth, the measurement can be performed in a form closer to the finished device, and the etching control can be performed extremely accurately. In particular, when the second layer is thin like a hetero bipolar transistor, only the first layer can be reliably removed without etching the second layer, and the yield in the etching step can be improved.
第１図は本発明のエッチング制御方法を説明するための
図、第２図はエッチングをある程度進行させた後の試料
片の斜視図、第３図（ａ）〜（ｆ）はエッチング開始か
ら終了までの間の６点におけるＩ−Ｖ特性を示した図で
ある。FIG. 1 is a view for explaining an etching control method of the present invention, FIG. 2 is a perspective view of a sample piece after etching is advanced to some extent, and FIGS. FIG. 9 is a diagram showing IV characteristics at six points up to the point.
フロントページの続き (56)参考文献 特開 平１−198078（ＪＰ，Ａ) 特開 昭56−88372（ＪＰ，Ａ) 特開 昭61−220335（ＪＰ，Ａ) 特開 昭63−96961（ＪＰ，Ａ) 特開 昭58−95869（ＪＰ，Ａ) 特開 平１−165184（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/306,21/3063,21/3065 Continuation of front page (56) References JP-A-1-198078 (JP, A) JP-A-56-88372 (JP, A) JP-A-61-220335 (JP, A) JP-A-63-96961 (JP, A) JP-A-58-95869 (JP, A) JP-A-1-165184 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/306, 21/3063, 21/3065
Claims (1)
ち、表面側のエピタキシャル膜のエッチング操作を制御
する方法において、エピタキシャル膜表面に電極を２つ
形成し、該電極間の電流を測定することにより、表面側
のエピタキシャル膜の厚さを検知して、前記電極領域を
除いた前記表面側のエピタキシャル膜をエッチングする
操作を終了することを特徴とするエッチングの制御方
法。In a method for controlling an etching operation of an epitaxial film on a surface side of an epitaxial film having a pn junction, two electrodes are formed on a surface of the epitaxial film and a current between the electrodes is measured. Detecting the thickness of the epitaxial film on the front side, and terminating the operation of etching the epitaxial film on the front side excluding the electrode region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02130158A JP3127448B2 (en) | 1990-05-22 | 1990-05-22 | Etching control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02130158A JP3127448B2 (en) | 1990-05-22 | 1990-05-22 | Etching control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0426125A JPH0426125A (en) | 1992-01-29 |
| JP3127448B2 true JP3127448B2 (en) | 2001-01-22 |
Family
ID=15027385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02130158A Expired - Fee Related JP3127448B2 (en) | 1990-05-22 | 1990-05-22 | Etching control method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3127448B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11996013B2 (en) | 2019-05-02 | 2024-05-28 | Pilot Italia S.P.A. | Label and manufacturing method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109887872B (en) * | 2019-03-29 | 2024-11-15 | 华南理工大学 | Precision etching device and etching method for preparing recessed gate enhancement type device |
-
1990
- 1990-05-22 JP JP02130158A patent/JP3127448B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11996013B2 (en) | 2019-05-02 | 2024-05-28 | Pilot Italia S.P.A. | Label and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0426125A (en) | 1992-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3853650A (en) | Stress sensor diaphragms over recessed substrates | |
| US5167778A (en) | Electrochemical etching method | |
| US3994009A (en) | Stress sensor diaphragms over recessed substrates | |
| JP3127448B2 (en) | Etching control method | |
| CN107993957A (en) | The evaluating method of ion implantation concentration detection method and different ions board ion implantation concentration uniformity | |
| US3650020A (en) | Method of monitoring semiconductor device fabrication | |
| US3697873A (en) | Method for determining excess carrier lifetime in semiconductor devices | |
| JPH11317398A (en) | Method for manufacturing semiconductor device and etching system thereof | |
| EP0016596B1 (en) | Semiconductor device having a monitor pattern and method of monitoring the same | |
| GB1569931A (en) | Manufacture of semiconductor devices | |
| US20040256244A1 (en) | Selective electrochemical etching method for two-dimensional dopant profiling | |
| EP0077921A2 (en) | Semiconductor device | |
| JP2559512B2 (en) | Metal film thickness measurement method | |
| JP3777742B2 (en) | Manufacturing method of semiconductor device | |
| RU190700U1 (en) | TEST PLANAR TRANSISTOR | |
| JPS62186529A (en) | Element for measuring deformed amount of pattern | |
| JP2869112B2 (en) | Method for manufacturing semiconductor device | |
| JPH02238646A (en) | Measurement of impurities in semiconductor | |
| JPS5946098B2 (en) | Manufacturing method of semiconductor device | |
| JPS6043653B2 (en) | Manufacturing method of semiconductor device | |
| JP3109566B2 (en) | Evaluation method of semiconductor device | |
| JPH01196858A (en) | Transistor | |
| Lawrence | A diffused field effect current limiter | |
| JPS58141390A (en) | Etching method of silicon plate | |
| JPH01167674A (en) | Manufacture of semiconductor acceleration sensor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |