JP3124381B2 - Semiconductor device and mounting structure - Google Patents
Semiconductor device and mounting structureInfo
- Publication number
- JP3124381B2 JP3124381B2 JP04179574A JP17957492A JP3124381B2 JP 3124381 B2 JP3124381 B2 JP 3124381B2 JP 04179574 A JP04179574 A JP 04179574A JP 17957492 A JP17957492 A JP 17957492A JP 3124381 B2 JP3124381 B2 JP 3124381B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- main surface
- lead
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 126
- 238000007789 sealing Methods 0.000 claims description 61
- 239000011347 resin Substances 0.000 claims description 55
- 229920005989 resin Polymers 0.000 claims description 55
- 239000008188 pellet Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 25
- 230000000694 effects Effects 0.000 description 6
- 239000008393 encapsulating agent Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、高密度実装に好適な半導体装置に適用して有効な技
術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a technology effective when applied to a semiconductor device suitable for high-density mounting.
【０００２】[0002]
【従来の技術】特願平１−３３４１３７号（出願日 平
成１年１２月２２日）に高密度実装に好適な樹脂封止型
半導体装置の開示がある。2. Description of the Related Art A resin-sealed semiconductor device suitable for high-density mounting is disclosed in Japanese Patent Application No. 1-334137 (filing date: December 22, 2001).
【０００３】この樹脂封止型半導体装置は、半導体ペレ
ットが封止された樹脂封止体の一側面に複数本の外部リ
ードを配列し、樹脂封止体の前記一側面と対向する他の
一側面に放熱板を突出させる。半導体ペレットの素子形
成面にはＤＲＡＭ（ＤynamicＲandom Ａccess Ｍemor
y）が搭載される。複数本の外部リードの一端の夫々は
樹脂封止体の内部の内部リードを通して半導体ペレット
の複数個の外部端子（ボンディングパッド）の夫々に個
々に電気的に接続される。複数本の外部リードの他端の
夫々は樹脂封止体の上面からこの樹脂封止体の側面に沿
って裏面に折り返し引き回される。In this resin-encapsulated semiconductor device, a plurality of external leads are arranged on one side of a resin encapsulant in which semiconductor pellets are encapsulated, and another external lead facing the one side of the resin encapsulant is provided. Make the heat sink protrude from the side. DRAM is the element formation surface of the semiconductor pellet (D ynamic R andom A ccess M emor
y) is mounted. One end of each of the plurality of external leads is individually electrically connected to each of the plurality of external terminals (bonding pads) of the semiconductor pellet through the internal leads inside the resin sealing body. Each of the other ends of the plurality of external leads is turned around from the upper surface of the resin sealing body to the rear surface along the side surface of the resin sealing body.
【０００４】この樹脂封止型半導体装置は、面実装構造
で構成され、プリント配線基板等の実装基板表面上に複
数個重ね合わせ、メモリモジュールとして実装でき、非
常に高い実装密度が得られる。しかも、個々の樹脂封止
型半導体装置は、放熱板を有しているので、メモリモジ
ュールとしての放熱効果にも優れている。This resin-encapsulated semiconductor device has a surface mounting structure, and can be mounted as a memory module on a mounting board such as a printed wiring board by superimposing a plurality thereof, thereby obtaining a very high mounting density. Moreover, since each resin-encapsulated semiconductor device has a heat radiating plate, it is also excellent in heat radiating effect as a memory module.
【０００５】[0005]
【発明が解決しようとする課題】しかしなから、本発明
者は、前述の樹脂封止型半導体装置において、以下の点
についての配慮がなされていないことを見出した。However, the present inventor has found that the following points are not taken into consideration in the above-described resin-sealed semiconductor device.
【０００６】（１）前記樹脂封止型半導体装置は、ＤＩ
Ｐ構造やＳＯＰ構造と同様に、樹脂封止体の内部の半導
体ペレットの素子形成面又は裏面を実装基板の表面と対
向させ、半導体ペレットの厚さ方向と実装基板の厚さ方
向を一致させ、実装基板表面上に実装される。つまり、
前記樹脂封止型半導体装置は、実装基板表面と一致する
横方向に樹脂封止体が長く、実装基板表面に垂直な縦方
向に樹脂封止体が短くなる、所謂横型実装方式で実装さ
れる。この樹脂封止型半導体装置は縦方向に複数個重ね
合される。(1) The resin-encapsulated semiconductor device is a DI
Similarly to the P structure or the SOP structure, the element forming surface or the back surface of the semiconductor pellet inside the resin sealing body is opposed to the front surface of the mounting substrate, and the thickness direction of the semiconductor pellet is made to coincide with the thickness direction of the mounting substrate, It is mounted on the mounting board surface. That is,
The resin-encapsulated semiconductor device is mounted by a so-called horizontal mounting method in which the resin encapsulant is long in the horizontal direction corresponding to the surface of the mounting substrate and the resin encapsulant is short in the vertical direction perpendicular to the surface of the mounting substrate. . A plurality of the resin-encapsulated semiconductor devices are vertically stacked.
【０００７】しかしながら、前記樹脂封止型半導体装置
は実装基板表面への実装方式が横型実装方式に一義的に
決まっているので、実装基板表面と一致する横方向に空
き空間がなく、縦方向には空き空間が存在する装置への
組み込みができないという制約が発生する。換言すれ
ば、無理に装置に組み込む場合には、装置の内部に無駄
な空き空間が発生し、結果的に実装基板表面での樹脂封
止型半導体装置の実装密度が低下する。However, in the resin-encapsulated semiconductor device, since the mounting method on the surface of the mounting substrate is uniquely determined to be the horizontal mounting method, there is no empty space in the horizontal direction corresponding to the surface of the mounting substrate, and Has a restriction that it cannot be incorporated into a device having an empty space. In other words, when it is forcibly incorporated into the device, a useless empty space is generated inside the device, and as a result, the mounting density of the resin-encapsulated semiconductor device on the surface of the mounting substrate is reduced.
【０００８】（２）前記樹脂封止型半導体装置は樹脂封
止体の外部に外部リードが突出し、この外部リードの突
出した分、実装基板表面での複数個の樹脂封止型半導体
装置の間に無駄な空き空間が発生し、実装基板表面での
樹脂封止型半導体装置の実装密度が低下する。(2) In the resin-encapsulated semiconductor device, external leads protrude outside the resin encapsulant, and the projecting portion of the external leads causes a plurality of resin-encapsulated semiconductor devices on the surface of the mounting board to be mounted. Useless empty space is generated, and the mounting density of the resin-encapsulated semiconductor device on the surface of the mounting board is reduced.
【０００９】（３）前記樹脂封止型半導体装置は、樹脂
封止体の外部に外部リードが突出しているので、この突
出した外部リードに外部応力が加わりやすく、外部リー
ドの成型形状に折れや曲がりが発生しやすい。(3) In the resin-encapsulated semiconductor device, since external leads protrude outside the resin-encapsulated body, external stress is easily applied to the protruded external leads, and the external leads are likely to be broken into a molded shape. Bending is likely to occur.
【００１０】本発明の目的は、以下の通りである。The objects of the present invention are as follows.
【００１１】（１）封止体の外部に外部リードが配列さ
れた半導体装置において、実装基板の実装面に横型実装
方式、縦型実装方式のいずれの方式でも実装ができ、実
装基板の実装面での実装密度を向上する。(1) In a semiconductor device in which external leads are arranged outside a sealing body, the semiconductor device can be mounted on a mounting surface of a mounting substrate by either a horizontal mounting method or a vertical mounting method. To increase the mounting density.
【００１２】（２）前記目的（１）を達成するととも
に、実装基板の実装面において、隣接する半導体装置の
間若しくは積層された半導体装置の間の無駄な空き空間
を廃止し、実装密度を向上する。(2) Achieving the object (1), eliminating unnecessary empty space between adjacent semiconductor devices or stacked semiconductor devices on the mounting surface of the mounting board, and improving the mounting density. I do.
【００１３】（３）前記目的（２）を達成するととも
に、前記半導体装置の外部リードの損傷を防止する。(3) The object (2) is achieved and the external leads of the semiconductor device are prevented from being damaged.
【００１４】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１５】[0015]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones will be briefly described as follows.
【００１６】一主面を有する半導体ペレットと、前記半
導体ペレットの一主面に形成された外部端子と、前記一
主面上に一部が延在して前記外部端子と電気的に接続さ
れ他部は前記一主面から遠ざかる方向に延在するリード
と、前記半導体ペレット及び前記リードの一部を封止し
た樹脂封止体とからなる半導体装置であって、前記リー
ドの内部リードは前記樹脂封止体内において前記一主面
上に延在する第１部分と前記第１部分から前記一主面上
を覆う前記樹脂封止体表面近くまで延在する第２部分と
からなり、前記第２部分に連続して前記樹脂封止体表面
から外部リードである第３部分が露出し、前記樹脂封止
体は前記半導体ペレットの一主面上を覆う第１の部分と
前記半導体ペレットの側面を覆う第２の部分と前記半導
体ペレットの一主面とは反対側の他の主面上を覆う第３
の部分とからなり、前記外部リードは前記樹脂封止体の
第１の部分から露出するとともに前記樹脂封止体の第２
の部分及び第３の部分に沿って屈曲している。一主面及
びこの一主面とは反対側の他の主面を有する半導体ペレ
ットと、前記半導体ペレットの一主面に設けられた外部
端子と、前記外部端子に接続された内部リードと、前記
内部リードに連続した外部リードと、前記半導体ペレッ
ト及び内部リードを封止する上面、側面、底面を有し樹
脂からなる封止体とを有し、前記内部リードの一部は前
記一主面上に前記外部端子に接近して設けられ、前記内
部リードの他部は前記半導体ペレットの他の主面方向と
は反対方向に前記一主面から遠ざかるように延在し、更
に前記内部リードの他部に連続する外部リードは前記封
止体から露出して前記封止体の上面、側面、及び底面に
沿って設けられた半導体装置と、この半導体装置と同じ
構造の他の半導体装置とが積層され実装基板に実装され
ている。[0016] a semiconductor pellet having one main surface, wherein the semiconductor external terminals formed on one main surface of the pellets, the other is connected the to an external terminal electrically extend partially on said one main surface The part is a semiconductor device comprising a lead extending in a direction away from the one main surface, and a resin sealing body sealing the semiconductor pellet and a part of the lead, wherein the internal lead of the lead is the resin A first portion extending on the one main surface in the sealing body, and a second portion extending from the first portion to near the surface of the resin sealing body covering the one main surface; A third portion, which is an external lead, is exposed from the surface of the resin sealing body following the portion, and the resin sealing is performed.
A body covering a first main surface of the semiconductor pellet;
A second portion covering a side surface of the semiconductor pellet and the semiconductor;
A third covering the other main surface opposite to the one main surface of the body pellet;
The external lead is formed of the resin sealing body.
A second portion of the resin sealing body exposed from the first portion;
And the third portion. A semiconductor pellet having one main surface and another main surface opposite to the one main surface, an external terminal provided on one main surface of the semiconductor pellet, an internal lead connected to the external terminal, An external lead continuous with the internal lead, and a sealing body made of a resin having an upper surface, a side surface, and a bottom surface for sealing the semiconductor pellet and the internal lead, and a part of the internal lead is on the one main surface. The other part of the internal lead extends away from the one main surface in a direction opposite to the other main surface direction of the semiconductor pellet, and further includes the other part of the internal lead. An external lead continuous to the portion is formed by stacking a semiconductor device exposed from the sealing body and provided along the top surface, side surface, and bottom surface of the sealing body, and another semiconductor device having the same structure as the semiconductor device. And mounted on the mounting board.
【００１７】[0017]
【作用】上述した手段によれば、前記半導体装置におい
て、以下の作用効果がある。 （１）前記封止体の第１主面、第２主面、第３主面のい
ずれかに引き回された外部リードをいずれかの主面にお
いて実装基板に電気的に接続し、縦型実装方式、横型実
装方式のいずれの方式でも前記半導体装置を前記実装基
板に実装できるので、いずれかの用途に応じて前記半導
体装置を実装でき、前記実装基板の実装面での無駄な空
間を排除し、前記実装基板の実装面での半導体装置の実
装密度を向上できる。 （２）前記封止体の第１主面若しくは第２主面に引き回
された外部リードをいずれかの主面において実装基板に
電気的に接続し、この実装基板に縦型実装方式、横型実
装方式のいずれかの方式で前記半導体装置を実装した状
態において、前記封止体の第３主面に横方向、縦方向の
いずれかの方向に他の半導体装置を相互に電気的に接続
した状態で積層し実装できる。また、前記封止体の第３
主面に引き回された外部リードを実装基板にその主面に
おいて電気的に接続し、この実装基板に横型実装方式、
縦型実装方式のいずれかの方式で前記半導体装置を実装
した状態において、前記封止体の第１主面若しくは第２
主面に縦方向又は横方向に他の半導体装置を相互に電気
的に接続した状態で積層し実装できる。したがって、前
記実装基板表面での無駄な半導体装置と他の半導体装置
との間の空間を廃止でき、前記実装基板の実装面での半
導体装置の実装密度を向上できる。 （３）前記外部リードが実質的に封止体の主面よりも内
部側に埋め込まれ、前記外部リードのリード厚さに相当
する分、前記半導体装置の外径寸法を縮小でき、前記半
導体装置の小型化を図れる。 （４）前記外部リードが実質的に封止体の主面よりも内
部側に埋め込まれ、前記外部リードの成型形状を封止体
で保護できるので、外部リードの折れや曲がりを防止で
きる。 （５）前記半導体装置は封止体の第１主面、第２主面、
第３主面のそれぞれに外部リードを引き回した面実装型
で構成されるので、実装基板の互いに対向する実装面の
両面に複数個の半導体装置を夫々実装でき、実装基板の
実装面での半導体装置の実装密度を向上できる。According to the above-described means, the following effects can be obtained in the semiconductor device. (1) An external lead routed to one of the first, second, and third main surfaces of the sealing body is electrically connected to a mounting substrate on any of the main surfaces, and Since the semiconductor device can be mounted on the mounting board by any of a mounting method and a horizontal mounting method, the semiconductor device can be mounted according to any application, and wasteful space on the mounting surface of the mounting board is eliminated. In addition, the mounting density of the semiconductor device on the mounting surface of the mounting substrate can be improved. (2) An external lead routed to the first main surface or the second main surface of the sealing body is electrically connected to a mounting substrate on one of the main surfaces, and a vertical mounting method, a horizontal mounting In a state in which the semiconductor device is mounted by any of the mounting methods, another semiconductor device is electrically connected to the third main surface of the sealing body in any of a horizontal direction and a vertical direction. It can be stacked and mounted in a state. In addition, the third of the sealing body
The external leads routed to the main surface are electrically connected to the mounting board on the main surface, and the horizontal mounting method,
In a state where the semiconductor device is mounted by any of the vertical mounting methods, the first main surface or the second
Other semiconductor devices can be stacked and mounted in a state where they are electrically connected to each other in the vertical direction or the horizontal direction on the main surface. Therefore, a useless space between the semiconductor device and another semiconductor device on the surface of the mounting board can be eliminated, and the mounting density of the semiconductor device on the mounting surface of the mounting board can be improved. (3) The external lead is substantially embedded inside the main surface of the sealing body, and the outer diameter of the semiconductor device can be reduced by an amount corresponding to the lead thickness of the external lead. Can be reduced in size. (4) Since the external lead is substantially embedded inside the main surface of the sealing body and the molded shape of the external lead can be protected by the sealing body, it is possible to prevent the external lead from being bent or bent. (5) The semiconductor device includes a first main surface, a second main surface of a sealing body,
Since the third main surface is formed by a surface mounting type in which external leads are routed, a plurality of semiconductor devices can be mounted on both sides of the mounting surface facing each other on the mounting substrate, and the semiconductor on the mounting surface of the mounting substrate can be mounted. The mounting density of the device can be improved.
【００１８】以下、本発明の構成について、樹脂封止型
半導体装置に本発明を適用した一実施例とともに説明す
る。Hereinafter, the structure of the present invention will be described together with an embodiment in which the present invention is applied to a resin-sealed semiconductor device.
【００１９】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having identical functions are given same symbols and their repeated explanation is omitted.
【００２０】[0020]
【実施例】本発明の一実施例である樹脂封止型半導体装
置の構成について図１（断面図）、図２（要部拡大断面
図）及び図３（側面図）を使用し説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction of a resin-sealed semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 1 (cross-sectional view), FIG. 2 (enlarged cross-sectional view of essential parts), and FIG.
【００２１】図１乃至図３に示すように、樹脂封止型半
導体装置１は半導体ペレット２が樹脂封止体６で封止さ
れる。前記半導体ペレット２の素子形成面に配列された
複数個の外部端子２０の夫々には、各々、複数本の内部
リード３０を介在し、複数本の外部リード３１の夫々が
電気的に接続される。As shown in FIGS. 1 to 3, in a resin-sealed semiconductor device 1, a semiconductor pellet 2 is sealed with a resin sealing body 6. Each of the plurality of external terminals 20 arranged on the element forming surface of the semiconductor pellet 2 has a plurality of internal leads 30 interposed therebetween, and each of the plurality of external leads 31 is electrically connected. .
【００２２】前記半導体ペレット２は単結晶珪素で形成
され、この半導体ペレット２の素子形成面には図示しな
い回路システムが搭載される。本実施例において、回路
システムはＤＲＡＭで構成される。なお、回路システム
はＤＲＡＭに限らず、ＳＲＡＭ（Ｓtatic Ｒandom Ａcc
ess Ｍemory）等のメモリシステムやロジックシステム
で形成してもよい。The semiconductor pellet 2 is formed of single crystal silicon, and a circuit system (not shown) is mounted on the element forming surface of the semiconductor pellet 2. In this embodiment, the circuit system is constituted by a DRAM. The circuit system is not limited to DRAM, SRAM (S tatic R andom A cc
ess M emory) may be formed in the memory system and logic systems, and the like.
【００２３】前記半導体ペレット２の外部端子２０、リ
ード３の内部リード３０の一端側の夫々はワイヤ５を通
して電気的に接続される。ワイヤ５は例えばＡｕワイヤ
が使用される。Each of the external terminals 20 of the semiconductor pellet 2 and one end of the internal lead 30 of the lead 3 is electrically connected through a wire 5. As the wire 5, for example, an Au wire is used.
【００２４】前記リード３の内部リード３０の他端側
は、半導体ペレット２の素子形成面上に絶縁性フィルム
４を介在して延在し、外部リード３１の一端側に電気的
に接続される（一体に成型される）。絶縁性フィルム４
は例えばポリイミド系樹脂、エポキシ系樹脂等、樹脂膜
を主体に形成される。前記リード３の内部リード３０の
他端側は前述のように半導体ペレット２の素子形成面上
を延在するので、本実施例の樹脂封止型半導体装置１は
所謂ＬＯＣ（Ｌead Ｏn Ｃhip）構造で構成される。The other end of the internal lead 30 of the lead 3 extends on the element forming surface of the semiconductor pellet 2 with the insulating film 4 interposed therebetween, and is electrically connected to one end of the external lead 31. (Molded integrally). Insulating film 4
Is mainly formed of a resin film such as a polyimide resin or an epoxy resin. Since the other end of the inner lead 30 of the lead 3 extends over the element formation surface of the semiconductor pellet 2, as described above, the resin sealed semiconductor device 1 of this embodiment is a so-called LOC (L ead O n C hip) structure.
【００２５】前記リード３の外部リード３１の一端側は
樹脂封止体６の表面の上面（図１中及び図２中、上側表
面）において内部リード３０の他端側に接続される。こ
の外部リード３１の他端側は、樹脂封止体６の表面の上
面から側面（図１中及び図２中、右側面）に沿って樹脂
封止体６の表面に熱膨張時においても接触せずに延在
し、この側面から樹脂封止体６の表面の下面（図１中及
び図２中、下側表面）まで延在する。つまり、１本の外
部リード３１は樹脂封止体６の表面の上面、側面及び下
面の合計３つの面に渡って延在する。図１及び図２に示
すように、複数本の外部リード３１は、樹脂封止体６の
４つの側面のうちの１つの側面において、一端から他端
に向かって規則的に配列される。つまり、本実施例の樹
脂封止型半導体装置１は所謂ＳＩＰ（Ｓingle Ｉn line
Ｐackage）構造で構成される。One end of the external lead 31 of the lead 3 is connected to the other end of the internal lead 30 on the upper surface (the upper surface in FIGS. 1 and 2) of the surface of the resin sealing body 6. The other end of the external lead 31 contacts the surface of the resin sealing body 6 along the side surface (the right side surface in FIGS. 1 and 2) from the upper surface of the surface of the resin sealing body 6 even during thermal expansion. 1 and extends from the side surface to the lower surface of the surface of the resin sealing body 6 (the lower surface in FIGS. 1 and 2). That is, one external lead 31 extends over a total of three surfaces of the upper surface, the side surface, and the lower surface of the surface of the resin sealing body 6. As shown in FIGS. 1 and 2, the plurality of external leads 31 are regularly arranged from one end to the other end on one of the four side surfaces of the resin sealing body 6. That is, the resin sealed semiconductor device 1 of this embodiment is a so-called SIP (S ingle I n line
( Package) structure.
【００２６】前記外部リード３１は樹脂封止体６の表面
の上面、側面及び下面の外部リード３１が延在する領域
に形成された溝６０の内部において延在する。図２に示
すように、外部リード３１の表面の高さは、樹脂封止体
６の表面の上面、側面及び下面の外部リード３１が延在
しない領域の高さに比べて、いずれも寸法Ｃ１、Ｃ２、
Ｃ３を有する低い位置で構成される。つまり、外部リー
ド３１はその表面が樹脂封止体６の表面から突出せずに
溝６０の内部に埋め込まれる。また、前記外部リード３
１の表面の高さは、樹脂封止体６の表面の高さと同等に
構成してもよい。The external lead 31 extends inside a groove 60 formed in a region where the external lead 31 extends on the upper surface, side surface and lower surface of the surface of the resin sealing body 6. As shown in FIG. 2, the height of the surface of the external lead 31 is smaller than the height of the area where the external lead 31 does not extend on the upper surface, the side surface, and the lower surface of the surface of the resin sealing body 6. , C2,
Consists of a low position with C3. That is, the external lead 31 is embedded in the groove 60 without its surface protruding from the surface of the resin sealing body 6. The external lead 3
The height of the first surface may be the same as the height of the surface of the resin sealing body 6.
【００２７】前記内部リード３０、外部リード３１を含
むリード３は例えばＦｅ−Ｎｉ系合金、Ｃｕ、Ｃｕ合金
等の導電性材料で構成される。The leads 3 including the internal leads 30 and the external leads 31 are made of a conductive material such as, for example, an Fe-Ni alloy, Cu, or a Cu alloy.
【００２８】前記樹脂封止体６は例えばトランスファー
モールド法で成型されたエポキシ系樹脂で形成される。The resin sealing body 6 is made of, for example, an epoxy resin molded by a transfer molding method.
【００２９】このように構成される樹脂封止型半導体装
置１は、図４（横型実装方式で実装したときのシステム
構成図）、図５（縦型実装方式で実装したときのシステ
ム構成図）に示すように、実装されかつ積層され、メモ
リモジュールを構成する。The resin-encapsulated semiconductor device 1 thus configured is shown in FIG. 4 (system configuration diagram when mounted in a horizontal mounting system), and FIG. 5 (system configuration diagram when mounted in a vertical mounting system). As shown in (1), they are mounted and stacked to form a memory module.
【００３０】図４に示すメモリモジュールは、プリント
配線基板等の実装基板１０の実装面（図４中、上側表
面）に横型実装方式で樹脂封止型半導体装置１が実装さ
れ、この樹脂封止型半導体装置１の上側にさらに３個の
樹脂封止型半導体装置１が積層される。この実装は、実
装基板１０の実装面に配置された端子１１に樹脂封止型
半導体装置１の樹脂封止体６の表面の下面に位置する外
部リード３１を電気的に接続しかつ機械的に接続するこ
とで行われる。端子１１と外部リード３１との接続は例
えば半田１２で行なう。また、積層された樹脂封止型半
導体装置１の夫々は、半田を介在し、各々の外部リード
３１を電気的にかつ機械的に接続することにより接続さ
れる。In the memory module shown in FIG. 4, a resin-sealed semiconductor device 1 is mounted on a mounting surface (upper surface in FIG. 4) of a mounting board 10 such as a printed wiring board by a horizontal mounting method. Three resin-sealed semiconductor devices 1 are further stacked on the upper side of the semiconductor device 1. In this mounting, the external leads 31 located on the lower surface of the surface of the resin sealing body 6 of the resin-sealed semiconductor device 1 are electrically connected to the terminals 11 arranged on the mounting surface of the mounting board 10 and mechanically. This is done by connecting. The connection between the terminal 11 and the external lead 31 is made by, for example, the solder 12. Further, each of the laminated resin-sealed semiconductor devices 1 is connected by electrically and mechanically connecting the respective external leads 31 via solder.
【００３１】図５に示すメモリモジュールは、実装基板
１０の実装面（図４中、上側表面）に縦型実装方式で複
数個の樹脂封止型半導体装置１が実装され、この複数個
の樹脂封止型半導体装置１の夫々は横方向において積層
される。前述と同様に、実装や積層には半田１２等が使
用される。In the memory module shown in FIG. 5, a plurality of resin-encapsulated semiconductor devices 1 are mounted on a mounting surface (an upper surface in FIG. 4) of a mounting substrate 10 by a vertical mounting method. Each of the sealed semiconductor devices 1 is stacked in the lateral direction. As described above, solder 12 and the like are used for mounting and lamination.
【００３２】以上説明したように、本実施例によれば以
下の作用効果が得られる。As described above, according to the present embodiment, the following operational effects can be obtained.
【００３３】樹脂封止体６の内部に封止される半導体ペ
レット２の外部端子２０、前記樹脂封止体６の外部に配
列される外部リード３１の夫々が電気的に接続される樹
脂封止型半導体装置１において、前記外部リード３１
が、前記樹脂封止体６の表面の上側からこの樹脂封止体
６の上側と対向する下側まで、前記樹脂封止体６の上側
と下側との間の側面に沿って引き回されるとともに、前
記外部リード３１の表面の高さが、前記樹脂封止体６の
前記外部リード３１が引き回された領域以外の主面の高
さと同一か又は前記樹脂封止体６の前記外部リード３１
が引き回された領域以外の主面の高さに比べて低く構成
される。The external terminals 20 of the semiconductor pellet 2 sealed inside the resin sealing body 6 and the external leads 31 arranged outside the resin sealing body 6 are electrically connected to each other by resin sealing. In the semiconductor device 1, the external leads 31
Is routed along the side surface between the upper side and the lower side of the resin sealing body 6 from the upper side of the surface of the resin sealing body 6 to the lower side facing the upper side of the resin sealing body 6. In addition, the height of the surface of the external lead 31 is the same as the height of the main surface of the resin sealing body 6 other than the area where the external lead 31 is routed, or the height of the external surface of the resin sealing body 6 Lead 31
Is configured to be lower than the height of the main surface other than the region where the wiring is provided.
【００３４】この構成により、（１）前記樹脂封止体６
の上側、下側、側面のいずれかに引き回された外部リー
ド３１をいずれかの表面において実装基板１０に電気的
に接続し、縦型実装方式（図５参照）、横型実装方式
（図４参照）のいずれの方式でも前記樹脂封止型半導体
装置１を前記実装基板１０に実装できるので、いずれか
の用途に応じて前記樹脂封止型半導体装置１を実装で
き、前記実装基板１０の実装面での無駄な空間を排除
し、前記実装基板１０の実装面での樹脂封止型半導体装
置１の実装密度を向上できる。（２）前記樹脂封止体６
の下側に引き回された外部リード３１をこの主面におい
て実装基板１０に電気的に接続し、この実装基板１０に
横型実装方式（図４参照）で前記樹脂封止体型半導体装
置１を実装した状態において、前記樹脂封止体６の表面
の上側に縦方向に他の樹脂封止型半導体装置１を相互に
電気的に接続した状態で積層し実装できる。また、前記
樹脂封止体６の表面の側面に引き回された外部リード３
１を実装基板１０にその主面において電気的に接続し、
この実装基板１０に縦型実装方式（図５参照）で前記樹
脂封止型半導体装置１を実装した状態において、前記樹
脂封止体６の表面の上側若しくは下側に横方向に他の樹
脂封止型半導体装置１を相互に電気的に接続した状態で
積層し実装できる。したがって、前記実装基板１０の表
面での無駄な樹脂封止型半導体装置１と他の樹脂封止型
半導体装置１との間の空間を廃止でき、前記実装基板１
０の実装面での樹脂封止型半導体装置１の実装密度を向
上できる。（３）前記外部リード３１が実質的に樹脂封
止体６の表面よりも内部側に埋め込まれ、前記外部リー
ド３１のリード厚さに相当する分、前記樹脂封止型半導
体装置１の外径寸法を縮小でき、前記樹脂封止型半導体
装置１の小型化を図れる。（４）前記外部リード３１が
実質的に樹脂封止体６の主面よりも内部側に埋め込ま
れ、前記外部リード３１の成型形状を樹脂封止体６で保
護できるので、外部リード３１の折れや曲がりを防止で
きる。（５）前記樹脂封止型半導体装置１は樹脂封止体
６の表面の上側、下側、側面の夫々に外部リード３１を
引き回した面実装型で構成されるので、実装基板１０の
互いに対向する実装面の両面に複数個の樹脂封止型半導
体装置１を夫々実装でき、実装基板１０の実装面での樹
脂封止型半導体装置１の実装密度を向上できる。With this configuration, (1) the resin sealing body 6
The external leads 31 routed to any one of the upper, lower, and side surfaces are electrically connected to the mounting substrate 10 on any surface, and the vertical mounting method (see FIG. 5) and the horizontal mounting method (see FIG. 4). 2), the resin-encapsulated semiconductor device 1 can be mounted on the mounting substrate 10. Therefore, the resin-encapsulated semiconductor device 1 can be mounted according to any application, and the mounting substrate 10 can be mounted. It is possible to eliminate useless space on the surface and improve the mounting density of the resin-sealed semiconductor device 1 on the mounting surface of the mounting substrate 10. (2) The resin sealing body 6
The external leads 31 routed downward are electrically connected to the mounting substrate 10 on this main surface, and the resin-sealed semiconductor device 1 is mounted on the mounting substrate 10 by a horizontal mounting method (see FIG. 4). In this state, another resin-encapsulated semiconductor device 1 can be stacked and mounted vertically above the surface of the resin-encapsulated body 6 while being electrically connected to each other. Also, the external leads 3 routed around the side surface of the surface of the resin sealing body 6
1 is electrically connected to the mounting substrate 10 on its main surface,
In a state where the resin-encapsulated semiconductor device 1 is mounted on the mounting substrate 10 by a vertical mounting method (see FIG. 5), another resin-encapsulation is provided laterally above or below the surface of the resin encapsulant 6. The semiconductor devices 1 can be stacked and mounted in a state where they are electrically connected to each other. Therefore, a wasteful space between the resin-encapsulated semiconductor device 1 and another resin-encapsulated semiconductor device 1 on the surface of the mounting substrate 10 can be eliminated.
The mounting density of the resin-encapsulated semiconductor device 1 on the mounting surface 0 can be improved. (3) The outer diameter of the resin-encapsulated semiconductor device 1 is substantially equal to the lead thickness of the external lead 31 because the external lead 31 is substantially embedded inside the surface of the resin sealing body 6. The size can be reduced, and the resin-sealed semiconductor device 1 can be downsized. (4) Since the external lead 31 is substantially embedded in the inner side of the main surface of the resin sealing body 6 and the molded shape of the external lead 31 can be protected by the resin sealing body 6, the external lead 31 is broken. And bending can be prevented. (5) Since the resin-encapsulated semiconductor device 1 is of a surface-mount type in which the external leads 31 are routed on the upper, lower, and side surfaces of the resin-encapsulated body 6, the mounting substrates 10 face each other. A plurality of resin-sealed semiconductor devices 1 can be respectively mounted on both sides of the mounting surface to be mounted, and the mounting density of the resin-sealed semiconductor devices 1 on the mounting surface of the mounting substrate 10 can be improved.
【００３５】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is:
Although the present invention has been described in detail with reference to the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the scope of the invention.
【００３６】例えば、本発明は、前記樹脂封止型半導体
装置１の樹脂封止体６の表面の上側若しくは下側のいず
れか一方と対向する２つの側面に沿って外部リード３１
を延在してもよい。For example, according to the present invention, the external leads 31 are provided along two side surfaces facing either the upper side or the lower side of the surface of the resin sealing body 6 of the resin sealing type semiconductor device 1.
May be extended.
【００３７】また、本発明は、前記樹脂封止型半導体装
置１の樹脂封止体６の対向する２つの側面に夫々複数本
の外部リード３１を配列した、ＳＯＰ（Ｓmall Ｏut li
neＰackage）構造に適用してもよい。Further, the present invention provides an array of external leads 31 each plurality of the two opposite sides of the resin molded body 6 of the resin-sealed semiconductor device 1, SOP (S mall O ut li
may be applied to ne P ackage) structure.
【００３８】また、本発明は、樹脂封止型半導体装置に
限らず、半導体ペレットをセラミック封止体で封止する
ガラス封止型半導体装置に適用してもよい。The present invention is not limited to a resin-sealed semiconductor device, but may be applied to a glass-sealed semiconductor device in which a semiconductor pellet is sealed with a ceramic sealing body.
【００３９】[0039]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
【００４０】（１）封止体の外部に外部リードが配列さ
れた半導体装置において、実装基板の実装面に横型実装
方式、縦型実装方式のいずれの方式でも実装ができ、実
装基板の実装面での実装密度を向上できる。(1) In a semiconductor device in which external leads are arranged outside a sealing body, the semiconductor device can be mounted on a mounting surface of a mounting board by either a horizontal mounting method or a vertical mounting method. The mounting density can be improved.
【００４１】（２）前記効果（１）が得られるととも
に、実装基板の実装面において、隣接する半導体装置の
間若しくは積層された半導体装置の間の無駄な空き空間
を廃止し、実装密度を向上できる。(2) In addition to the effect (1), the useless space between adjacent semiconductor devices or stacked semiconductor devices on the mounting surface of the mounting board is eliminated, and the mounting density is improved. it can.
【００４２】（３）前記効果（２）が得られるととも
に、前記半導体装置の外部リードの損傷を防止できる。(3) The effect (2) can be obtained, and the external leads of the semiconductor device can be prevented from being damaged.
【図１】 本発明の一実施例の樹脂封止型半導体装置の
断面図。FIG. 1 is a cross-sectional view of a resin-sealed semiconductor device according to one embodiment of the present invention.
【図２】 前記樹脂封止型半導体装置の要部拡大断面
図。FIG. 2 is an enlarged sectional view of a main part of the resin-sealed semiconductor device.
【図３】 前記樹脂封止型半導体装置の側面図。FIG. 3 is a side view of the resin-encapsulated semiconductor device.
【図４】 前記樹脂封止型半導体装置の実装図。FIG. 4 is a mounting diagram of the resin-encapsulated semiconductor device.
【図５】 前記樹脂封止型半導体装置の実装図。FIG. 5 is a mounting diagram of the resin-encapsulated semiconductor device.
１…樹脂封止型半導体装置、２…半導体ペレット、２０
…外部端子、３１…外部リード、６…樹脂封止体、６０
…溝、１０…実装基板。DESCRIPTION OF REFERENCE NUMERALS 1: resin-sealed semiconductor device, 2: semiconductor pellet, 20
... external terminals, 31 ... external leads, 6 ... resin sealing body, 60
... grooves, 10 ... mounting boards.
フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/28 H01L 21/56 Continuation of the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/28 H01L 21/56
Claims (4)
半導体ペレットの一主面に形成された外部端子と、前記
一主面上に一部が延在して前記外部端子と電気的に接続
され他部は前記一主面から遠ざかる方向に延在するリー
ドと、前記半導体ペレット及び前記リードの一部を封止
した樹脂封止体とからなる半導体装置であって、前記リ
ードの内部リードは前記樹脂封止体内において前記一主
面上に延在する第１部分と前記第１部分から前記一主面
上を覆う前記樹脂封止体表面近くまで延在する第２部分
とからなり、前記第２部分に連続して前記樹脂封止体表
面から外部リードである第３部分が露出し、前記樹脂封
止体は前記半導体ペレットの一主面上を覆う第１の部分
と前記半導体ペレットの側面を覆う第２の部分と前記半
導体ペレットの一主面とは反対側の他の主面上を覆う第
３の部分とからなり、前記外部リードは前記樹脂封止体
の第１の部分から露出するとともに前記樹脂封止体の第
２の部分及び第３の部分に沿って屈曲していることを特
徴とする半導体装置。 A semiconductor pellet having one principal surface;
An external terminal formed on one main surface of the semiconductor pellet;
Partially extends on one main surface and is electrically connected to the external terminal
And the other part extends in a direction away from the one main surface.
And a part of the semiconductor pellet and the lead are sealed.
A semiconductor device comprising:
The internal lead of the lead is
A first portion extending on a surface and the one main surface from the first portion;
A second portion extending to near the surface of the resin sealing body covering the upper portion
And the resin sealing body surface is continuous with the second portion.
The third portion, which is the external lead, is exposed from the surface,
The stopper is a first portion covering one main surface of the semiconductor pellet.
A second portion covering a side surface of the semiconductor pellet and the half portion;
The second covering the other main surface opposite to the one main surface of the conductor pellet
3 and the external lead is the resin-sealed body.
Exposed from the first portion of the
A semiconductor device, wherein the semiconductor device is bent along the second portion and the third portion .
１の部分、第２の部分及び第３の部分の夫々に形成され
た溝に沿って延在することを特徴とする請求項１に記載
の半導体装置。2. The external lead according to claim 1 , wherein
The first part, the second part and the third part are formed respectively.
2. The method of claim 1, wherein the groove extends along the groove.
Semiconductor device.
主面を有する半導体ペレットと、前記半導体ペレットの
一主面に設けられた外部端子と、前記外部端子に接続さ
れた内部リードと、前記内部リードに連続した外部リー
ドと、前記半導体ペレット及び内部リードを封止する上
面、側面、底面を有し樹脂からなる封止体とを有し、前
記内部リードの一部は前記一主面上に前記外部端子に接
近して設けられ、前記内部リードの他部は前記半導体ペ
レットの他の主面方向とは反対方向に前記一主面から遠
ざかるように延在し、更に前記内部リードの他部に連続
する外部リードは前記封止体から露出して前記封止体の
上面、側面、及び底面に沿って設けられた半導体装置
と、この半導体装置と同じ構造の他の半導体装置とが積
層され実装基板に実装されていることを特徴とする実装
構造体。 3. A main surface and another main surface opposite to the main surface.
A semiconductor pellet having a main surface;
An external terminal provided on one main surface; and an external terminal connected to the external terminal.
Internal lead and an external lead connected to the internal lead.
To seal the semiconductor pellet and the internal lead.
Front, side, and bottom surfaces, and a sealing body made of resin.
Some of the internal leads are connected to the external terminals on the one main surface.
And the other part of the internal lead is connected to the semiconductor pen.
Farther from the one principal surface in the direction opposite to the other principal surface direction of the let
Extends in a zigzag manner and continues to the other part of the internal lead
The external leads that are exposed from the sealing body
Semiconductor device provided along top surface, side surface, and bottom surface
And another semiconductor device having the same structure as this semiconductor device.
Mounting characterized by being layered and mounted on a mounting board
Structure.
体装置の外部リード同士が接続されていることを特徴と
する請求項３に記載の実装構造体。 4. The semiconductor device according to claim 1 , wherein
The external leads of the body device are connected to each other.
The mounting structure according to claim 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04179574A JP3124381B2 (en) | 1992-07-07 | 1992-07-07 | Semiconductor device and mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04179574A JP3124381B2 (en) | 1992-07-07 | 1992-07-07 | Semiconductor device and mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0629429A JPH0629429A (en) | 1994-02-04 |
| JP3124381B2 true JP3124381B2 (en) | 2001-01-15 |
Family
ID=16068119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04179574A Expired - Lifetime JP3124381B2 (en) | 1992-07-07 | 1992-07-07 | Semiconductor device and mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3124381B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100209782B1 (en) * | 1994-08-30 | 1999-07-15 | 가나이 쓰도무 | Semiconductor device |
| US6002167A (en) * | 1995-09-22 | 1999-12-14 | Hitachi Cable, Ltd. | Semiconductor device having lead on chip structure |
| KR0184076B1 (en) * | 1995-11-28 | 1999-03-20 | 김광호 | Three-dimensional stacked package |
| KR0179803B1 (en) * | 1995-12-29 | 1999-03-20 | 문정환 | Lead Exposure Semiconductor Package |
| JPH09260568A (en) * | 1996-03-27 | 1997-10-03 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| JP3026426B2 (en) * | 1996-08-29 | 2000-03-27 | 沖電気工業株式会社 | Resin-sealed semiconductor device, method of manufacturing the same, and mold structure thereof |
-
1992
- 1992-07-07 JP JP04179574A patent/JP3124381B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0629429A (en) | 1994-02-04 |
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