JP3123182B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3123182B2 JP3123182B2 JP04017595A JP1759592A JP3123182B2 JP 3123182 B2 JP3123182 B2 JP 3123182B2 JP 04017595 A JP04017595 A JP 04017595A JP 1759592 A JP1759592 A JP 1759592A JP 3123182 B2 JP3123182 B2 JP 3123182B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysilicon
- poly
- polysilicon film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000010408 film Substances 0.000 claims description 83
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 59
- 229920005591 polysilicon Polymers 0.000 claims description 33
- 150000004767 nitrides Chemical class 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 6
- 238000005121 nitriding Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 230000003071 parasitic effect Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法に係り、特に駆動能力を向上させたポリシリコン
薄膜トランジスタ（ＴＦＴ）及びその製造方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a polysilicon thin film transistor (TFT) with improved driving capability and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、アクティブ層をポリシリコン（ｐ
ｏｌｙ−Ｓｉ）等からなる薄膜にした構造の薄膜トラン
ジスタ（ＴＦＴ）がＬＣＤ（液晶表示装置）駆動やＳＲ
ＡＭ等のメモリの負荷として用いられる。2. Description of the Related Art In recent years, the active layer has been made of polysilicon (p).
thin-film transistors (TFTs), such as poly-Si), are used for driving LCDs (Liquid Crystal Display) and
Used as a load on a memory such as an AM.
【０００３】このようなＴＦＴは、基本的にはゲート電
極上に形成されたゲート絶縁膜、ソース／ドレイン領域
を有する半導体薄膜、そしてソース／ドレインの各電極
から構成される。Such a TFT basically includes a gate insulating film formed on a gate electrode, a semiconductor thin film having source / drain regions, and source / drain electrodes.
【０００４】図３に従来のＴＦＴの製造工程の一例を示
す。まず、図３（ａ）に示すように、ＳｉＯ2等の絶縁
基板１上にｐｏｌｙ−Ｓｉからなるゲート電極２を形成
した後、ＳｉＯ2等からなるゲート絶縁膜３、その上に
約４０ｎｍのポリシリコン（ｐｏｌｙ−Ｓｉ）膜４を形
成する。FIG. 3 shows an example of a conventional TFT manufacturing process. First, as shown in FIG. 3 (a), after forming the gate electrode 2 made of poly-Si on the insulating substrate 1 of SiO 2 or the like, the gate insulating film 3 made of SiO 2 or the like, of from about 40nm thereon A polysilicon (poly-Si) film 4 is formed.
【０００５】次に、図３（ｂ）に示すように、熱酸化に
よりｐｏｌｙ−Ｓｉ膜４の表面を酸化して２０〜３０ｎ
ｍのＳｉＯ2膜５を形成する。この酸化は１０〜２０ｎ
ｍの厚さのｐｏｌｙ−Ｓｉ膜４ａを残存させる。Next, as shown in FIG. 3B, the surface of the poly-Si film 4 is oxidized by thermal oxidation to 20 to 30 nm.
An m 2 SiO 2 film 5 is formed. This oxidation is 10-20 n
The poly-Si film 4a having a thickness of m is left.
【０００６】次に、図３（ｃ）に示すように、ＳｉＯ2
膜５上で、しかもゲート電極２上方にレジスト６を配
し、そのレジスト６をマスクとしてＢＦ2 +をイオン注入
（ＩＩ）してソース領域７ａ、ドレイン領域７ｂをｐｏ
ｌｙ−Ｓｉ膜４ａ内に形成する。この後、レジストを除
去し、図示はしないが層間絶縁膜を形成し、コンタクト
ホールを開孔し、コンタクト用のＡｌ電極を形成し、最
後にパッシベーションｐ（プラズマ）−ＳｉＮを堆積
し、シンターを行なうことにより、ｐｏｌｙ−ＳｉＴＦ
Ｔの水素化を行ってＴＦＴを完成させていた。[0006] Next, as shown in FIG. 3 (c), SiO 2
A resist 6 is disposed on the film 5 and above the gate electrode 2, and BF 2 + is ion-implanted (II) using the resist 6 as a mask to form the source region 7a and the drain region 7b as po.
It is formed in the ly-Si film 4a. Thereafter, the resist is removed, an interlayer insulating film (not shown) is formed, a contact hole is opened, an Al electrode for contact is formed, and finally a passivation p (plasma) -SiN is deposited, and a sinter is formed. By performing, poly-SiTF
T was hydrogenated to complete the TFT.
【０００７】[0007]
【発明が解決しようとする課題】上記方法によって得ら
れた構造のｐｏｌｙ−Ｓｉ ＴＦＴは、ソース領域７ａ
とドレイン領域７ｂ間のチャネル領域のｐｏｌｙ−Ｓｉ
膜厚は１０〜２０ｎｍと薄くでき、リーク電流が小と良
好である。しかしながら、ソース領域７ａとドレイン領
域７ｂもチャネル領域の厚さと同様に薄いため、ソース
（Ｓ）／ドレイン（Ｄ）の寄生抵抗が増大し、ＯＮ電流
が低下する。The poly-Si TFT having the structure obtained by the above-described method has a source region 7a.
-Si of the channel region between the gate and the drain region 7b
The film thickness can be made as thin as 10 to 20 nm, and the leak current is small and good. However, since the source region 7a and the drain region 7b are as thin as the thickness of the channel region, the parasitic resistance of the source (S) / drain (D) increases and the ON current decreases.
【０００８】そこで、本発明は、低リーク電流を保持し
た状態で、ソース／ドレインの寄生抵抗を低下させてＯ
Ｎ電流を増大させたポリシリコン薄膜トランジスタを製
造することを目的とする。Therefore, the present invention reduces the parasitic resistance of the source / drain while maintaining a low leakage current, and
An object is to manufacture a polysilicon thin film transistor having an increased N current.
【０００９】[0009]
【課題を解決するための手段】上記課題は本発明によれ
ば、絶縁基板上に形成されたポリシリコン薄膜トランジ
スタであって、ソース領域及びドレイン領域を有する前
記ポリシリコン膜表面上に窒化膜を有し、チャネル領域
を有するポリシリコン膜の膜厚が、表面上に前記窒化膜
を有する前記ポリシリコン膜の膜厚より薄く且つ該チャ
ネル領域を有するポリシリコン膜表面に酸化膜が形成さ
れてなることを特徴とする半導体装置によって解決され
る。According to the present invention, there is provided a polysilicon thin film transistor formed on an insulating substrate, comprising a nitride film on a surface of the polysilicon film having a source region and a drain region. The thickness of the polysilicon film having the channel region is smaller than the thickness of the polysilicon film having the nitride film on the surface, and the oxide film is formed on the surface of the polysilicon film having the channel region. The semiconductor device is characterized by the following.
【００１０】更に、上記課題は本発明によれば、絶縁基
板上にゲート電極、ゲート絶縁膜及びポリシリコン膜を
順次形成する工程、前記ポリシリコン膜表面を薄く窒化
して窒化膜を形成する工程、前記ゲート電極上方の窒化
膜部及びポリシリコン膜部の一部を除去して溝を形成す
る工程、前記溝内に窒化膜を形成した後、該酸化膜をマ
スクとしてイオン注入しソース領域及びドレイン領域を
ポリシリコン膜内に形成する工程、を含むことを特徴と
する半導体装置の製造方法によって解決される。Further, according to the present invention, there is provided a method of forming a gate electrode, a gate insulating film and a polysilicon film sequentially on an insulating substrate, and forming a nitride film by thinly nitriding the surface of the polysilicon film. Forming a groove by removing a portion of the nitride film portion and the polysilicon film portion above the gate electrode; forming a nitride film in the groove; implanting ions using the oxide film as a mask; Forming a drain region in a polysilicon film.
【００１１】[0011]
【作用】本発明によれば、絶縁基板上に形成されるポリ
シリコン（ｐｏｌｙ−Ｓｉ）ＴＦＴにおいて、図２
（ａ）に示すように、ポリシリコン膜１４の表面に急速
窒化（ＲＴＮ）法を用いて非常に薄く窒化膜１６を形成
した後、ゲート電極１２上方のｐｏｌｙ−Ｓｉ膜１４
（窒化膜１６も）を一部除去し、その部分に酸化膜（Ｓ
ｉＯ2膜）１５を形成しているため、チャネル部ではポ
リシリコン膜１４の厚さを薄く、ソース（Ｓ）、ドレイ
ン（Ｄ）部ではポリシリコン膜１４の厚さを厚くするこ
とができるため、リーク電流を小にし、しかもソース、
ドレイン領域の寄生抵抗を低減できるため、ＯＮ電流も
改善することができる。According to the present invention, in a polysilicon (poly-Si) TFT formed on an insulating substrate, FIG.
As shown in FIG. 1A, a very thin nitride film 16 is formed on the surface of a polysilicon film 14 using a rapid nitridation (RTN) method, and then a poly-Si film 14 above the gate electrode 12 is formed.
(The nitride film 16 is also partially removed, and the oxide film (S
Since the iO 2 film 15 is formed, the thickness of the polysilicon film 14 can be reduced in the channel portion, and the thickness of the polysilicon film 14 can be increased in the source (S) and drain (D) portions. , Reduce the leakage current, and
Since the parasitic resistance of the drain region can be reduced, the ON current can be improved.
【００１２】[0012]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【００１３】図１及び図２は、本発明に係るｐｏｌｙ−
Ｓｉ ＴＦＴ及びその製造方法を適用した一実施例をそ
れぞれ示す断面図及び工程断面図である。FIG. 1 and FIG. 2 show a poly- according to the present invention.
It is sectional drawing and process sectional drawing which show each Example which applied Si TFT and its manufacturing method, respectively.
【００１４】本発明に係るｐｏｌｙ−Ｓｉ ＴＦＴは、
図１に示すように絶縁基板１１上に形成されたゲート電
極１２、絶縁基板１１とゲート電極１２を覆うゲート絶
縁膜１３、アクティブ層としてのポリシリコン（ｐｏｌ
ｙ−Ｓｉ）膜１４、ｐｏｌｙ−Ｓｉ膜１４の表面を窒化
して形成した窒化膜（ＳｉＮ）１６、ゲート電極１２上
方で且つｐｏｌｙ−Ｓｉ膜の一部を除去して形成された
ＳｉＯ2膜１５、層間絶縁膜１８、取り出し電極２０、
そして上面を覆うプラズマ窒化膜（ＳｉＮ）２１から構
成されている。The poly-Si TFT according to the present invention comprises:
As shown in FIG. 1, a gate electrode 12 formed on an insulating substrate 11, a gate insulating film 13 covering the insulating substrate 11 and the gate electrode 12, and polysilicon (pol) as an active layer
y-Si) film 14, nitride film (SiN) 16 formed by nitriding the surface of poly-Si film 14, SiO 2 film formed above gate electrode 12 and by removing part of the poly-Si film 15, an interlayer insulating film 18, an extraction electrode 20,
And it is composed of a plasma nitride film (SiN) 21 covering the upper surface.
【００１５】上記ＴＦＴ構造でゲート電極上方のｐｏｌ
ｙ−Ｓｉ膜１４の厚さＷ１を約１５ｎｍとし、その両側
のｐｏｌｙ−Ｓｉ膜１４の厚さＷ２を約３０〜３５ｎ
ｍ、その表面の窒化膜１６の厚さを５〜１０ｎｍ程度と
した。In the above TFT structure, the pol
The thickness W1 of the y-Si film 14 is about 15 nm, and the thickness W2 of the poly-Si film 14 on both sides thereof is about 30 to 35 n.
m, the thickness of the nitride film 16 on the surface was set to about 5 to 10 nm.
【００１６】このようなｐｏｌｙ−Ｓｉ ＴＦＴは、ｐ
ｏｌｙ−Ｓｉ膜１４のチャネル部（厚さＷ１の部分）は
薄くなっているため、リーク電流を小にし、一方ソース
／ドレイン領域（厚さＷ２の部分）は厚く形成されてい
るため、寄生抵抗の増大が抑制され、ＯＮ電流が改善さ
れる。Such a poly-Si TFT has p
Since the channel portion (portion of thickness W1) of the poly-Si film 14 is thin, the leakage current is small, while the source / drain region (portion of thickness W2) is formed thick, so that the parasitic resistance is reduced. Is suppressed, and the ON current is improved.
【００１７】以下、図１に示したｐｏｌｙ−Ｓｉ ＴＦ
Ｔの製造方法を図２に基づいて説明する。Hereinafter, the poly-Si TF shown in FIG.
A method for manufacturing T will be described with reference to FIG.
【００１８】まず、図２（ａ）に示すように、ＳｉＯ2
からなる絶縁基板１１上に、Ｐ+ｐｏｌｙ−Ｓｉからな
るゲート電極１２をＣＶＤ法によるｐｏｌｙ−Ｓｉの堆
積、ＢＦ２+のイオン注入、リソグラフィ技術によるパ
ターンニングによって形成し、その後全面に約３０ｎｍ
の厚さにＳｉＯ2からなるゲート絶縁膜１３を形成す
る。次に、ゲート絶縁膜１３上にＣＶＤ法によって５５
０℃の温度、０．６Ｔｏｒｒの温度でアモルファス（非
晶質）シリコン（ａ−Ｓｉ）を堆積し、そのａ−Ｓｉを
６００℃の温度で１０時間アニールすることにより、固
相結晶化する。ポリシリコン（ｐｏｌｙ−Ｓｉ）膜１４
は４０ｎｍの厚さである。その後表面を１０５０℃の温
度で急速窒化（ＲＴＮ）を行い、５〜１０ｎｍの厚さの
窒化膜１６を形成する。[0018] First, as shown in FIG. 2 (a), SiO 2
A gate electrode 12 made of P + poly-Si is formed on an insulating substrate 11 made of P + by deposition of poly-Si by a CVD method, ion implantation of BF 2 + , and patterning by a lithography technique.
A gate insulating film 13 made of SiO 2 is formed to a thickness of 3 nm. Next, 55 nm is formed on the gate insulating film 13 by the CVD method.
Amorphous silicon (a-Si) is deposited at a temperature of 0 ° C. and a temperature of 0.6 Torr, and the a-Si is annealed at a temperature of 600 ° C. for 10 hours to perform solid-phase crystallization. Polysilicon (poly-Si) film 14
Is 40 nm thick. Then the surface subjected to rapid nitride (RTN) at a temperature of 1050 ° C., to form a nitride film 16 having a thickness of 5 to 10 nm.
【００１９】次に、ゲート電極１２上のｐｏｌｙ−Ｓｉ
膜１４部を露出するようにレジスト（図示せず）を塗布
した後、レジストをマスクとして例えばホットリン酸に
よるウエットエッチングによりゲート上方のｐｏｌｙ−
Ｓｉの窒化層とｐｏｌｙ−Ｓｉの一部を除去する（図２
（ｂ））。Next, the poly-Si on the gate electrode 12 is
After applying a resist (not shown) so as to expose the film 14 portion, the poly-above the gate is wet-etched with hot phosphoric acid using the resist as a mask, for example.
The silicon nitride layer and a part of the poly-Si are removed (FIG. 2).
(B)).
【００２０】次に、図２（ｃ）に示すように、８００〜
８５０℃の温度で、例えばウェット酸化を行い約２０〜
２５ｎｍの厚さのＳｉＯ2膜１５を形成する（この際、
ゲート上以外のｐｏｌｙ−Ｓｉ層表面は窒化されている
のでゲート上に比べてそれ程酸化されない）。ＳｉＯ2
膜１５を形成した後、このＳｉＯ2膜１５をマスクとし
てＢＦ2 +をイオン注入しアニールすることによって、ポ
リシリコン（ｐｏｌｙ−Ｓｉ）膜１４にソース（Ｓ）、
ドレイン（Ｄ）の各領域を形成する。Next, as shown in FIG.
At a temperature of 850 ° C., for example, wet oxidation
A SiO 2 film 15 having a thickness of 25 nm is formed (at this time,
Since the surface of the poly-Si layer other than on the gate is nitrided, it is less oxidized than on the gate). SiO 2
After the film 15 is formed, BF 2 + is ion-implanted and annealed using the SiO 2 film 15 as a mask, so that the polysilicon (poly-Si) film 14 has a source (S),
Each region of the drain (D) is formed.
【００２１】続いて、図２（ｄ）に示すように、層間絶
縁膜１８をＣＶＤ法等により形成し、その後リソグラフ
ィー技術を用いてコンタクトホール１９を形成する。Subsequently, as shown in FIG. 2D, an interlayer insulating film 18 is formed by a CVD method or the like, and thereafter, a contact hole 19 is formed by using a lithography technique.
【００２２】その後、図１に示したように、Ａｌを蒸着
そしてパターニングすることにより取り出し電極２０を
形成し、次に例えばＳｉＨ4とＮＨ3との混合ガスを反応
ガスとして用いたプラズマＣＶＤ法によりプラズマ窒化
膜（ｐ−ＳｉＮ）２１を形成し、例えば４００℃の温度
で所定時間アニール（シンター）を行ってＴＦＴを水素
化しｐｏｌｙ−Ｓｉ ＴＦＴを完成させる。Thereafter, as shown in FIG. 1, an extraction electrode 20 is formed by depositing and patterning Al, and then, for example, by a plasma CVD method using a mixed gas of SiH 4 and NH 3 as a reaction gas. A plasma nitride film (p-SiN) 21 is formed, and the TFT is hydrogenated by annealing (sintering) at a temperature of, for example, 400 ° C. for a predetermined time to complete a poly-Si TFT.
【００２３】[0023]
【発明の効果】以上説明したように、本発明によれば、
ポリシリコン膜のチャネル領域に比較してソース領域及
びドレイン領域の酸化をより防止することができるた
め、チャネル領域よりソース及びドレイン領域のポリシ
リコン膜を厚く維持することができ、酸化によるソース
及びドレイン領域の寄生抵抗の増加を防止することがで
き、ＯＮ電流も改善できる。As described above, according to the present invention,
Oxidation of the source region and the drain region can be more prevented than that of the channel region of the polysilicon film, so that the polysilicon film of the source and drain regions can be maintained thicker than the channel region, and the source and drain due to oxidation can be maintained. An increase in the parasitic resistance of the region can be prevented, and the ON current can be improved.
【図１】本発明に係るｐｏｌｙ−Ｓｉ ＴＦＴの一実施
例を示す断面図である。FIG. 1 is a sectional view showing one embodiment of a poly-Si TFT according to the present invention.
【図２】図１に示したｐｏｌｙ−Ｓｉ ＴＦＴの製造方
法の一実施例を示す工程断面図である。FIG. 2 is a process sectional view showing one embodiment of a method for manufacturing the poly-Si TFT shown in FIG.
【図３】従来例を説明するための工程断面図である。FIG. 3 is a process cross-sectional view for explaining a conventional example.
１，１１ 絶縁基板 ２，１２ ゲート電極 ３，１３ ゲート絶縁膜 ４，４ａ，１４ ポリシリコン（ｐｏｌｙ−Ｓｉ）膜 ５，１５ ＳｉＯ2膜 ６ レジスト ７ａ ソース領域 ７ｂ ドレイン領域 １６ 窒化膜（ＳｉＮ） １７ 溝 １８ 層間絶縁膜 １９ コンタクトホール ２０ 取り出し電極 ２１ プラズマ窒化膜（ＳｉＮ）Reference Signs List 1,11 Insulating substrate 2,12 Gate electrode 3,13 Gate insulating film 4,4a, 14 Polysilicon (poly-Si) film 5,15 SiO 2 film 6 Resist 7a Source region 7b Drain region 16 Nitride film (SiN) 17 Groove 18 Interlayer insulating film 19 Contact hole 20 Extraction electrode 21 Plasma nitride film (SiN)
Claims (3)
膜トランジスタであって、ソース領域及びドレイン領域
を有する前記ポリシリコン膜表面上に窒化膜を有し、チ
ャネル領域を有するポリシリコン膜の膜厚が、表面上に
前記窒化膜を有する前記ポリシリコン膜の膜厚より薄く
且つ該チャネル領域を有するポリシリコン膜表面に酸化
膜が形成されてなることを特徴とする半導体装置。1. A polysilicon thin film transistor formed on an insulating substrate, comprising: a nitride film on a surface of the polysilicon film having a source region and a drain region; and a polysilicon film having a channel region. An oxide film formed on a surface of the polysilicon film having a thickness smaller than a thickness of the polysilicon film having the nitride film on a surface thereof.
及びポリシリコン膜を順次形成する工程、 前記ポリシリコン膜表面を薄く窒化して窒化膜を形成す
る工程、 前記ゲート電極上方の前記窒化膜部及び前記ポリシリコ
ン膜部の一部を除去して溝を形成する工程、 前記溝内に酸化膜を形成した後、該酸化膜をマスクとし
てイオン注入しソース領域及びドレイン領域を前記ポリ
シリコン膜内に形成する工程、 を含むことを特徴とする半導体装置の製造方法。2. a step of sequentially forming a gate electrode, a gate insulating film and a polysilicon film on an insulating substrate; a step of thinly nitriding a surface of the polysilicon film to form a nitride film; and a step of forming the nitride film above the gate electrode. Forming a groove by removing a portion of the polysilicon film portion and a portion of the polysilicon film portion. After forming an oxide film in the groove, ion-implanting is performed by using the oxide film as a mask to form a source region and a drain region in the polysilicon film. Forming a semiconductor device therein.
なうことを特徴とする請求項２記載の方法。3. The method according to claim 2, wherein said nitride film is formed by a rapid nitriding method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04017595A JP3123182B2 (en) | 1992-02-03 | 1992-02-03 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04017595A JP3123182B2 (en) | 1992-02-03 | 1992-02-03 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05218424A JPH05218424A (en) | 1993-08-27 |
| JP3123182B2 true JP3123182B2 (en) | 2001-01-09 |
Family
ID=11948250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04017595A Expired - Fee Related JP3123182B2 (en) | 1992-02-03 | 1992-02-03 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3123182B2 (en) |
-
1992
- 1992-02-03 JP JP04017595A patent/JP3123182B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05218424A (en) | 1993-08-27 |
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