JP3117514B2 - Reset type discrimination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset type for providing a processor (CPU) with reset type information indicating whether a system of an information processing apparatus is activated by a power-on sequence or by a reset operation after power-on. It relates to a determination circuit.

[0002]

2. Description of the Related Art Generally, in an information processing apparatus, the system is started by turning on a power supply (hereinafter, referred to as a cold start) or restarted by an operation on a reset switch or the like performed after the cold start. (Hereinafter, referred to as a hot start) may be required to be determined after startup.

For example, when the system uses a volatile memory, the memory contents are volatile at the time of a cold start, so that the contents must be initialized and data loaded. Since the contents are not volatilized, the above-described initialization processing is unnecessary.
It is also desirable to focus on increasing the number of diagnostic items and diagnostic patterns to increase the failure detection rate at the time of a cold start during the initial diagnosis of the system. In many cases, the diagnosis is limited to a minimum.

As described above, since different startup processing is required depending on the startup type (reset type) of the system, it is essential that software (ie, the processor of the information processing apparatus) can identify the startup state. is there.

In order to make such identification, it is conceivable to provide a reset signal for each reset type to a processor through a separate input terminal. However, many processors which are already on the market often use a reset signal input terminal. Has only one. Therefore, conventionally, the OR outputs of the above-described two types of reset signals are given to the reset signal input terminal of the processor. Conventionally, in such a situation, the processor can identify the reset type.
A reset type discriminating circuit capable of giving reset type information to the processor is provided.

FIG. 2 is a block diagram showing a conventional reset type discriminating circuit. 2, the reset type discriminating circuit has a basic configuration including a power-on reset generation circuit 1 and a reset type holding flip-flop circuit 7.

The power-on reset generation circuit 1 supplies +5 V
The power-on reset signal for initializing the circuit is generated for a fixed time by detecting that the power supply has become higher than the reference voltage. The power-on reset generation circuit 1 includes a resistor 2,
3 and 5, and reset integrated circuit (reset IC) 4
And a capacitor 6. The resistors 2 and 3 connected in series divide the + 5V power supply and input the divided voltage to the reset IC 4. When the power is turned on, the + 5V power supply also gradually rises from 0V to 5V, so that the divided voltage also rises gradually. The reset IC 4 is, for example, a commercially available IC having a reference power supply therein, and is an active-low power-on reset signal PONRST-N from the time when the divided voltage becomes larger than the reference power supply to the time determined by the capacitor 6. (-N means active low). In addition, reset IC
Since the output stage 4 has an open collector output configuration, a pull-up resistor 5 for pulling up the output stage is provided.

As the reset type holding flip-flop circuit 7, a D-type flip-flop circuit is applied.
The power-on reset signal PONRST-N output from the power-on reset generation circuit 1 is invertedly input to the reset terminal of the flip-flop circuit 7. The clock terminal receives a system reset signal SYSRST-N generated by a system reset generation circuit (not shown) in response to operation of a reset switch or the like. Note that the flip-flop circuit 7 is of a type that takes in data at the rising edge of the system reset signal SYSRST-N. The data input terminal is connected to a + 5V power supply via a resistor 8, and a preset terminal for receiving an inverted input is also connected to a + 5V power supply via a resistor 8. Therefore, H-level data is always input, and no preset is instructed. Then, the output is sent from the inverted output terminal to the outside (CPU) to the power-on reset instruction signal PONIND-P (-
P means active high).

In the flip-flop circuit 7, when the power-on reset signal PONRST-N is at a significant L level, the power-on reset instruction signal PONIND-P is at a significant H level, and the power-on reset signal PONRST-N is at an H level. Even when the power-on reset instruction signal PONIND-P changes to the H level, the H-level is maintained. That is, the level indicating the power-on reset (cold start) is held. In such a state, when the system reset signal SYSRST-N returns to a significant L level and then returns to a high level, the data at the H level is always taken in. Accordingly, the power-on reset instruction signal PONIND-P changes to the low level. Changes to That is, the level is changed to a level indicating a system reset (hot start).

FIG. 3 is a flowchart showing a process at the time of starting a processor using the reset type discriminating circuit having such a configuration.

When a reset signal is input to the reset input terminal and returns to the original level, the processor (not shown) starts the processing shown in FIG. 3 (step S1) and is held in the flip-flop circuit 7 described above. The power-on reset instruction signal PONIND-P is read (step S2), and it is determined whether the contents indicate a cold start (H level) or a hot start (L level) (step S3). If a cold start is instructed, a cold start process is executed (step S4). If a hot start is instructed, a hot start process is executed (step S5). Go to (Step S6).

[0012]

Since the process shown in FIG. 3 is executed as an interrupt process when a reset signal is given, a reset signal is generated during the execution of the process shown in FIG. In this case, the process of FIG. 3 is restarted from the beginning.

For example, as shown in FIG. 4, even if a system reset signal SYSRST-N is given when a reset switch is pressed during execution of a cold start process, the process shown in FIG. 3 is restarted from the beginning. In such a case, the power-on reset instruction signal PONI
The ND-P is read. At the time of reading, the power-on reset instruction signal PONIND-P has changed to a state in which a system reset (hot start) is instructed. Therefore, at this time, a hot start process is executed.

However, in such a case, the hot start process is executed in a state where the cold start process is not completed, and the operation proceeds to the normal operation state, so that a failure may occur in the normal operation state.

For example, when a memory or the like with a parity check is mounted on an information processing apparatus using this reset type discriminating circuit, the following problems occur. Generally, memory initialization is performed during a cold start process. If the reset switch is pressed during the cold start process, the processor (not shown) is interrupted by the reset input even if the memory initialization is being performed. When the reset signal returns to the original level,
The processor starts the boot process of FIG. 3, but determines that it is a hot start, and executes the hot start process to start operation. Therefore, the above-described initialization of the memory has not been performed to the end, and the operation has proceeded to the operation state.
If an uninitialized memory area is read during this operation, a parity error will be detected.

The present invention has been made in view of the above points, and even if a system reset occurs during a cold start process, an information processing apparatus having the reset type discriminating circuit can operate normally. It is intended to provide a reset type determination circuit.

[0017]

According to the present invention, there is provided a power-on reset at power-on.
Cold start processing for the
Hot start processing for external system reset signal
When performing the processing of one of the, the reset type determination circuit holding the reset type information processor issues taken were as follows.

That is, there are provided a power-on reset generation means for generating a power-on reset signal when power is turned on, and a reset type holding means for holding reset type information. When the power-on reset signal is given, the reset type holding means holds reset type information indicating a power-on reset until a power-on instruction clear signal is given from the processor, and the reset type information indicating that the cold start process has been completed. power-on the instruction clear signal is given from, updating hold reset type information to the reset type information indicating a system reset co
In addition, the processor completes the cold start process.
Only when the power-on instruction clear signal is output .

[0019]

In the present invention, the reset type holding means sets and holds the reset type information to the power-on reset type when the power-on reset signal generated from the power-on reset generation means is given. The reset type holding means updates and holds the reset type information to the system reset type based on the signal output when the processor has completed the cold start processing.

Therefore, even when the system reset signal is generated during the cold start processing, the cold start processing is executed instead of the hot start processing. That is, normal operation processing is not executed in a state where the cold start processing is not completed, and occurrence of a failure can be prevented.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. Here, FIG. 1 shows a reset type discriminating circuit according to this embodiment, and FIG. 5 is a flow chart showing a start-up process of a processor using this reset type discriminating circuit. In FIG. 1, the same reference numerals are given to portions corresponding to those in FIG. In FIG. 5, steps corresponding to those in FIG. 3 are denoted by the same reference numerals.

In FIG. 1, the reset type discriminating circuit according to this embodiment also has a basic configuration of a power-on reset generating circuit 1 and a flip-flop circuit 7. This reset type discriminating circuit includes, in addition to the basic configuration unit 10,
Processor (CPU) 1 that executes a boot processing program (see FIG. 5) stored in program ROM 12
1 is also a constituent element. As is well known, the input / output interface circuit 13 and the system bus 14 are interposed between the basic component 10 and the processor 11 for signal transmission / reception.

Also in this embodiment, the power-on reset signal PONRST output by the power-on reset generation circuit 1
-N is applied to a reset terminal which inverts and takes in the input of the flip-flop circuit 7.

However, the connection of the other input terminals of the flip-flop circuit 7 is different from the conventional one. The data input terminal and the clock terminal are grounded. In other words, this is equivalent to always being at the L level and having no clock input and no data input. The preset terminal for inverting and inputting the input is connected to the input / output interface circuit 13 so that the power-on instruction clear signal INDCLR-N output from the processor 11 is supplied. The pulse width (L level period) of the power-on instruction clear signal INDCLR-N is a short period.

Therefore, the flip-flop circuit 7
After the L-level power-on reset signal PONRST-N is supplied, the L-level power-on instruction clear signal INDCLR-N
Until is supplied, a power-on reset instruction signal PONIND-P of H level meaning a power-on reset is output, and a power-on instruction clear signal INDCLR-N of L level is output.
Is supplied, an L-level power-on reset instruction signal PONIND-P indicating a system reset is output.

Here, since the reset type discriminating circuit holds reset type information indicating whether the reset type is a power-on reset or a system reset, it is apparently necessary to input both the power-on reset signal and the system reset signal. It seems like. However, since there is a limitation that the power-on reset occurs only when the power is turned on, by using this property, it is possible to form an instruction signal PONIND-P that can determine the two types of reset by inputting only the power-on reset signal. . This embodiment utilizes such a property.

Next, a startup process performed by the processor 11 when a reset signal is supplied will be described with reference to FIG.

The basic processing flow is almost the same as in the prior art. That is, when the reset signal is input to the reset input terminal, the processing being executed at that time is stopped, and when it returns to the original level, the processing shown in FIG. 5 is started (step S1). Then, the power-on reset instruction signal PONIND-P held in the flip-flop circuit 7 is read (step S2), and the content thereof indicates a cold start (H level) or a hot start (L level). Is determined (step S3). And
When a cold start is instructed, a cold start process is executed (step S4). When a hot start is instructed, a hot start process is executed (step S5), and thereafter, the operation proceeds to a normal operation state. (Step S6).

However, in the case of this embodiment, the processing for outputting the power-on instruction clear signal INDCLR-N is provided after the cold start processing and before entering the normal operation state (step S7). Power-on instruction clear signal
INDCLR-N is connected to the flip-flop circuit 7 as described above.
Is switched from a state in which power-on reset is instructed to a state in which system reset is instructed by pressing a reset switch or the like. Therefore, providing the processing for outputting the power-on instruction clear signal INDCLR-N at this position means that the holding state of the flip-flop circuit 7 is changed from the state of instructing the power-on reset only when the cold start processing is completed. This means switching to a state in which a system reset is instructed.

FIG. 6 shows an operation timing chart of the reset type discriminating circuit. Hereinafter, FIG.
The operation of the reset type discriminating circuit of this embodiment will be described with reference to FIG. In particular, an operation when a system reset occurs during a cold start process will be described. FIG.
(B) shows a system reset signal SYSR similar to the conventional system reset signal which is not directly used in the reset type discriminating circuit of this embodiment.
ST-N is shown.

The processing from power-on to execution of the cold start processing is the same as in the prior art, and a description thereof will be omitted.

At time T2 during execution of the cold start process, it is assumed that a reset switch (not shown) is pressed and the system reset signal SYSRST-N becomes significant. However, in this embodiment, since the reset type discriminating circuit does not use this system reset signal SYSRST-N, the power-on reset instruction signal PONIND-P is switched to the L level for instructing a system reset (hot start). There is no. Further, since the process of transmitting the power-on instruction clear signal INDCLR-N in step S7 described above is not performed during the cold start process, the power-on reset instruction signal PONIND-P indicates a system reset (hot start). There is no switching to level.

In such a state, when the system reset signal SYSRST-N returns to the insignificant H level at time T3, the processor 11 starts the processing of FIG. At this time, the power-on reset instruction signal PONIND-P is at the H level meaning power-on reset.
1 starts a cold start process. In other words, the same processing as when the power-on reset has occurred is executed despite the occurrence of the system reset. When the cold start process thus started is completed, the processor 11 sends a significant power-on instruction clear signal INDCLR-N at the time T6, and proceeds to the process of the operating state.
At this time, the flip-flop circuit 7 performs a preset operation, and the power-on reset instruction signal PONIND-P changes to L level meaning system reset (hot start).

The flip-flop circuit 7 holds a state in which a system reset (hot start) is instructed, and at time T7 when the processor 11 is executing a normal operation process, the reset switch (not shown) is pressed to When the reset signal SYSRST-N becomes significant, the processor 11 stops the normal operation processing. Eventually, when the system reset signal SYSRST-N returns to insignificant at time T8, the processing shown in FIG. 5 is started, and the power-on reset instruction signal PO
Determine the contents of NIND-P. At this time T8, since the power-on reset instruction signal PONIND-P indicates a system reset (hot start) as described above, the processor 11 executes the hot start processing, and the processor 11 normally executes the hot start processing from the time T9 when this processing ends. Operation processing.

Therefore, according to the above-described embodiment, when the system reset occurs during the cold start processing, the reset type information is held so that the cold start processing is executed. The normal operation processing is not executed in a state where the initialization is not completed, and it is possible to prevent a failure from occurring due to insufficient initialization.

The circuit that holds the reset state is not limited to a D-type flip-flop circuit. Further, the detailed configuration of the power-on reset generation circuit 1 is not limited to the above-described embodiment. Further, the significance levels of various signals are not limited to those in the above embodiment.

[0037]

As is evident from the foregoing description, according to the present invention, a cold-start process even when the system reset has occurred is executed when a co Lumpur <br/> de start process has not been completed, Cold When the start process is not completed, the process does not proceed to the normal operation process, and the information processing apparatus including the reset type determination circuit can operate normally.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an embodiment.

FIG. 2 is a block diagram showing a conventional configuration.

FIG. 3 is a flowchart showing startup processing by a conventional processor.

FIG. 4 is an operation timing chart of a conventional configuration.

FIG. 5 is a flowchart illustrating startup processing by a processor according to the embodiment.

FIG. 6 is an operation timing chart of the embodiment.

[Explanation of symbols]

1 Power on reset generation circuit, 7 Flip-flop circuit, 11 Processor (CPU), PONRST-N Power on reset signal, PONIND-P Power on reset instruction signal, INDCLR-N Power on instruction clear signal.

Claims (1)

(57) [Claims] 1. A power-on reset signal at power-on
Cold start processing and system
Hot start processing for system reset signal
Reset that the processor fetches when performing any of the operations
Reset type discrimination circuit that holds type information
At power-onToPower to generate power-on reset signal
Holds on-reset generation means and reset type information
Reset type holding means, wherein the reset type holding means includes a power-on reset signal.
Is given, the power-on instruction
A reset indicating a power-on reset until a rear signal is given
Holds the set type information and completes cold start processing
Power-on instruction clear signal from the processor
The reset type information indicates a system reset.
Update to reset type informationAlong with The processor indicates that the cold start process has been completed.
Only when the power-on instruction clear signal is output Features
Reset type discriminating circuit.