CN101470613A - Computer system and debugging method and starting method of basic input and output system thereof - Google Patents

Abstract

A computer system includes a first BIOS unit, a second BIOS unit, a bus, a detection unit, and a first delay unit. The detection unit can be operatively connected to the bus, the first BIOS unit, and the second BIOS unit to detect a bus signal in the bus. In addition, the first delay unit can be electrically connected to the detection unit to control the detection unit to detect the state of the bus signal after a preset delay time. Thus, the detection unit can switch to the first BIOS unit or the second BIOS unit for booting according to the state of the bus signal.

Description

Debugging method and booting method of computer system and its basic input and output system

technical field

The present invention relates to a computer system, and in particular to a computer system with multiple basic input and output systems and a booting method thereof.

Background technique

The Basic Input Output System (hereinafter referred to as BIOS) is usually stored in a non-volatile memory, such as flash memory, and is the most basic software program code loaded on the computer hardware system. Generally speaking, the main functions of the BIOS include Power On Self Test (POST), initialization actions, recording system settings, providing resident program libraries, and loading the operating system.

Due to the progress of the semiconductor manufacturing process, the hardware update speed around the computer system is also getting faster and faster. In order for the computer system to recognize these updated peripheral hardware, the firmware of the BIOS also needs to be updated synchronously. In the actual update process, the BIOS will be damaged if you are not careful. For example, in the process of updating the BIOS, once a sudden power failure occurs, the contents of the entire BIOS will be destroyed, and the entire computer system cannot be started smoothly.

Contents of the invention

Therefore, the present invention provides a BIOS and its error detection circuit, which can effectively restore a BIOS when a BIOS is damaged.

The present invention also provides a basic input and output system error detection method and a computer system boot method, which can effectively detect whether an error occurs in the BIOS, and can repair it in time when an error occurs.

The invention provides a computer system, which includes a first BIOS unit, a second BIOS unit, a bus, a detection unit and a first delay unit. The detection unit is operatively connected to the bus, the first BIOS unit, and the second BIOS unit to detect a bus signal in the bus. In addition, the first delay unit can be electrically connected to the detection unit, so as to control the detection unit to detect the state of the bus signal after a preset delay time. Thus, the detection unit can be switched to use the first BIOS unit or the second BIOS unit to start up according to the state of the bus signal.

In one embodiment, the invention also includes a buffer and an inverter. Wherein, the buffer can be electrically connected to the detection unit to receive the state of the output terminal and send it to the first BIOS unit. In addition, the inverter can be electrically connected to the buffer and the second BIOS unit. Thus, the inverter can invert the output of the buffer and send it to the second BOIS unit.

In a preferred embodiment, the detection unit can be realized by using a D-type flip-flop. Wherein, the D-type flip-flop also has a clearing terminal and a preset terminal, and the preset terminal is fixed at a voltage level.

In addition, the above-mentioned delay unit is electrically connected to the clearing terminal of the D-type flip-flop, and includes a resistor and a capacitor. Wherein, the resistor can electrically connect the clearing end of the D-type flip-flop to the voltage source. Alternatively, a capacitor can connect the clear terminal to ground.

From another point of view, the present invention provides a basic input output system error detection method, which can be applied to a computer system. The error detection method of the present invention includes performing a power self-test and checking the status of bus signals in a bus after a delay time. When the state of the bus signal is different from the bus signal when the computer system is normally powered on, it is judged that the BIOS is not normal.

From another point of view, the present invention further provides a method for booting a computer system, including using the first BIOS to execute a boot program of the computer system, and checking the state of the bus signal after a delay time. When the state of the bus signal is different from the bus signal when the computer system is normally started, the second BIOS is used to start the computer system.

In an embodiment of the present invention, the aforementioned bus signal may be a signal transmitted on a serial peripheral interface, a small number of pin interface, a front side bus, or a peripheral component interconnection interface.

Because the present invention can judge whether the BIOS is normal according to the state of the bus signal generated by the BIOS. Therefore, the present invention can effectively detect errors of the BIOS, and can use the second BIOS to repair when errors occur in the BIOS.

Description of drawings

In order to make the above-mentioned and other objects, features and advantages of the present invention more comprehensible, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows, wherein:

FIG. 1 is a system block diagram of a computer system according to a preferred embodiment of the present invention.

FIG. 2 is a circuit block diagram of a BIOS module according to a preferred embodiment of the present invention.

Figure 3 shows the structure diagram of a general basic input and output system.

4A-4C show waveform diagrams of bus signals.

FIG. 5A is a waveform diagram of the output terminal of the D-type flip-flop in state 1. FIG.

FIG. 5B is a waveform diagram of the output terminal of the D-type flip-flop in state 2. FIG.

FIG. 6 is a flow chart showing the steps of restoring the main BIOS according to a preferred embodiment of the present invention.

FIG. 7 is a flow chart showing the steps of a booting method of a computer system according to a preferred embodiment of the present invention.

Detailed ways

FIG. 1 shows a system block diagram of a computer system according to a preferred embodiment of the present invention. Referring to FIG. 1 , a computer system 100 may include a processing unit (CPU) 102 , a chipset 104 , a memory 106 , and a BIOS module 200 . The above-mentioned processing unit 102 can be electrically connected to a chipset 104 , wherein the chipset 104 includes a north bridge chip 112 and a south bridge chip 114 . The processing unit 102 is electrically connected to the north bridge chip 112 through a front side bus (FSB), and the north bridge chip 112 is electrically connected to the south bridge chip 114 through a peripheral component interconnect interface (PCI) bus. In addition, the north bridge chip 112 is also electrically connected to the memory 106 . The above-mentioned processing unit 102 can also be electrically connected to the south bridge chip 114 through other buses. The south bridge chip 114 can be electrically connected to the BIOS module 200 through a serial peripheral interface (SPI) bus or a low pin count (LPC) bus.

In this embodiment, the bus used includes a serial peripheral interface, a small number of pins interface, a front side bus, or a peripheral component interconnection interface. In other embodiments, other bus interfaces may also be included.

FIG. 2 is a circuit block diagram of a BIOS module according to a preferred embodiment of the present invention. For its description, please refer to FIG. 1 and FIG. 2 together. The BIOS module 200 provided in this embodiment includes a first BIOS unit 202 , a second BIOS unit 204 , a detection unit 220 and a delay unit 240 . The delay unit 240 is electrically connected to the detection unit 220 to form a part of a bus signal detection circuit. In this embodiment, the detection unit 220 can be implemented by using a D-type flip-flop 222 . The D-type flip-flop 222 has an input terminal D, a timing terminal CLK, a clear terminal CLR, a preset terminal PR and an output terminal Q. The timing terminal CLK receives the bus signal output by the first BIOS unit 202 and the second BIOS unit 204 , and the clearing terminal CLR can be electrically connected to the delay unit 240 . In this embodiment, the bus signal detected by the timing terminal CLK can be a CS# signal (Hardware signal) in the serial peripheral interface 116 .

It should be noted that, in this embodiment, the bus signal detection circuit is used to detect the bus signal between the south bridge chip 114 and the first BIOS unit 202 and the second BIOS unit 204 , such as the CS# signal. In other embodiments, the bus signal detection circuit can also detect bus signals between other components, for example: the bus signal between the processing unit 102 and the north bridge chip 112; the bus signal between the processing unit 102 and the south bridge chip 114 ; The bus signal between the north bridge chip 112 and the south bridge chip 114 .

In order to make the following description clear and concise, in the following descriptions, the CS# signal is used as the bus signal detected by the detection unit 220 . However, those skilled in the art should know that the present invention is not limited thereto.

Please continue to refer to FIG. 2 , the input terminal D of the D-type flip-flop 222 can be electrically connected to a voltage V1 through a resistor 224 , which is, for example, +3.3 volts. In addition, the preset terminal PR can also be electrically connected to the voltage V2 through the resistor 226 , which can also be set to +3.3 volts. In this implementation, the preset terminal PR of the D-type flip-flop 222 has a logic characteristic of being enabled in a low state, and in this embodiment, the preset terminal PR is fixedly set to a disabled state (Disable State).

In this embodiment, the BIOS module 200 may further include a buffer 228 and an inverter 230 . Wherein, the buffer 228 further includes buffer units 2281 , 2282 and a delay unit 2283 . The buffer unit 2281 is electrically connected to the detection unit 220 , that is, the buffer unit 2281 can be electrically connected to the output terminal Q of the D-type flip-flop 222 . In addition, the buffer unit 2282 is electrically connected to the buffer unit 2281 , the delay unit 2283 , the first BIOS unit 202 , and the inverter 230 . The output of the inverter 230 is electrically connected to the second BIOS unit 204 . Thus, the buffer 228 can transmit the state of the output terminal Q of the D-type flip-flop 222 to the first BIOS unit 202, and the inverter 230 can invert the state of the output terminal Q of the D-type flip-flop 222, Then send to the second BIOS unit 204 .

In this embodiment, both delay units 240 and 2283 can be realized by using RC delay circuits. Taking the delay unit 240 as an example, the delay unit 240 has at least a resistor 242 and a capacitor 244 . The resistors 242 are respectively electrically connected to the clearing terminal CLR of the D-type flip-flop 222 and the voltage source V3, and the capacitors 244 are respectively electrically connected to the clearing terminal CLR. In this embodiment, the level of the voltage source V3 can also be set as +3.3 volts.

In order to enable those skilled in the art to clearly understand the spirit of the present invention, the structure of the BIOS will be briefly described below.

Figure 3 shows the structure diagram of a general basic input and output system. Please refer to FIG. 3, most of the current BIOS program codes are stored in non-volatile memory (for example, the first BIOS unit 202 and the second BIOS unit 204 in FIG. 2), which can include a boot block 302, a fixed boot block (External Boot Block) 304 and main system block 306. When the BIOS is in the process of POST, there are many devices that need to be initialized, and these initializations need the first BIOS unit 202 or the second BIOS unit 204 to transmit through each bus. In this process, each bus will transmit various bus signal, and the present embodiment is to use the bus signal detection circuit to detect the bus signal of the serial peripheral interface bus between the south bridge chip 114 and the first BIOS unit 202 and the second BIOS unit 204, such as the bus in FIG. 2 Signal CS#.

In the POST process, if the BIOS program code in the first BIOS unit 202 is normal and can be executed normally, then the computer system is in the normal power-on situation (in the POST process), and the signal waveforms in each bus related to the execution of the BIOS can be, for example, as shown in Fig. 4A. FIG. 4A shows the CS# signal waveform in the SPI bus under normal power-on condition.

In FIG. 4A, when the BIOS program code starts to execute (t0), the voltage level of the bus signal CS# can be switched from the low-state voltage VL to the high-state voltage VH, and will be between the high-state voltage VH and the low-state voltage VL. The range oscillates back and forth. The voltage level of the bus signal CS# will be fixed at the high state voltage VH until the BIOS finishes executing (t1). Of course, in other embodiments, the waveform of the bus signal may be different due to the adoption of different bus protocols or circuit designs.

If the program codes in the first BIOS unit 202 (such as the program codes in the boot block and the program codes in the main system block 306) are damaged too severely, and the computer system cannot be started, the waveform of the bus signal CS# may be As shown in Figure 4B. In FIG. 4B , the bus signal CS# is fixed at the high-state voltage VH when the BIOS starts to be executed (t0), and does not oscillate back and forth.

In addition, if some program codes in the fixed boot block 304 or the main system block 306 are damaged, the computer system may be able to boot normally to a certain extent. The state of # can be shown in FIG. 4C. In FIG. 4C , the bus signal CS# also switches from the low-state voltage VL to the high-state voltage VH when the BIOS starts to be executed (t0), and may also oscillate. However, the voltage level of the bus signal CS# is fixed at the high-state voltage VH before the execution of the BIOS is completed (t1).

It can be seen from the above description that the waveform of the bus signal is different when the computer system is normally powered on and when the computer system cannot be normally powered on. Based on this characteristic, this embodiment is exactly after BIOS starts to carry out power supply self-test (POST), uses delay unit to delay after a preset delay time, and starts to detect the bus signal of one of bus lines in the computer system, judges current BIOS Whether to execute normally. Wherein, the bus is a bus related to BIOS execution during a boot process.

Please refer back to FIG. 2 , when the computer system is turned on, the first BIOS unit 202 is activated to start executing POST. At this moment, the state of the preset terminal PR of the D-type flip-flop 222 is Disabled, and the clear terminal CLR is still in a low state when the delay unit 240 generates the RC delay effect. In this embodiment, the clearing terminal CLR has a low-state enable feature, so the output terminal D of the D-type flip-flop 222 is in a low state when the computer is just turned on.

After a delay time, the capacitor 244 in the delay unit 240 is charged to a critical value, so that the clearing terminal CLR is also disabled. At this time, the state of the output terminal Q of the D-type flip-flop 222 is determined according to the state of the bus signal CS#. In particular, the time for the capacitor 244 to charge to a critical value is the so-called delay time, which can be designed to be slightly longer than the time required by the BIOS program code of the boot block 302 in FIG. 3 . In some embodiments, the delay time of the delay unit 240 may be 200ms, and the delay time of the delay unit 2283 may be 400ms. Wherein, the delay time of the delay unit 240 is used to determine the time point when the detection unit 220 starts to detect the bus signal, and the delay time of the delay unit 2283 is used to determine how long the output terminal Q of the flip-flop 222 starts to be released. Passed to BIOS unit 202,204.

Several types of situations are proposed below to illustrate the operation of the BIOS module 200 after the delay time has elapsed after the computer system is turned on.

Situation 1

The waveform diagram of the output terminal of the D-type flip-flop in state 1 shown in FIG. 5A . Please refer to FIG. 2 and FIG. 5A together. When the computer system is just powered on (t0), the output terminal Q of the D-type flip-flop 222 is in a low state VL (because the clear terminal CLR is enabled). After the delay time P1, at t2, the clear terminal CLR is disabled. At this time, if the content of the first BIOS unit 202 is completely normal, the state of the bus signal CS# of this embodiment can be as shown in FIG. Output Q output. In other words, the state of the output Q will change from a low state to a high state. At this time, the first BIOS unit 202 can maintain the running state. In addition, the inverter 230 will output a low-state logic signal after inverting the state of the output terminal Q, so that the second BIOS unit 204 is continuously disabled.

Situation 2

The waveform diagram of the output terminal of the D-type flip-flop in state 2 shown in FIG. 5B . Please refer to FIG. 2 and FIG. 5B together. If the data of the first BIOS unit 202 is damaged, the state of the bus signal CS# detected by the D-type flip-flop 222 may be as shown in FIG. 4B or FIG. 4C. That is to say, even when the state of the clearing terminal CLR is switched from low to high at t2, the output terminal Q remains in a low state because the bus signal CS# received by the timing terminal CLK does not oscillate. At this time, the first BIOS unit 202 is disabled. Correspondingly, the inverter 230 will output a low-state signal to the second BIOS unit 204 after inverting the state of the output terminal Q, causing the second BIOS unit 204 to be enabled and perform a recovery procedure (hereinafter will be explained in detail).

Looking back at situation 1, if the bus signal CS# received by the timing terminal CLK oscillates after the delay time has elapsed, it means that at least the boot block in the first BIOS unit 202 has no data damage. However, although erroneous data does not occur in the boot block, it may still occur in, for example, the fixed boot block 304 or the main system block 306 in FIG. 3 . Therefore, in some embodiments, when the program code in the fixed boot block 304 or the main system block 306 is to be executed, a checksum action is performed. Specifically, the program codes in the fixed boot block 304 and the main system block 306 are summed up respectively, and a check sum can be obtained.

When any sum of the program codes in the fixed boot block 304 and the main system block 306 is not equal to the corresponding default value, then the first BIOS such as the south bridge chip 114 in FIG. 1 can enable a control signal, and This causes the output Q of the D-type flip-flop 222 to switch from a high state back to a low state. At this time, the first BIOS unit 202 is disabled, and the second BIOS unit 204 is enabled, and the recovery procedure can be executed.

In contrast, if the sum of the program codes in the fixed boot block 304 and the main system block 306 is equal to the corresponding default value, it means that neither the fixed boot block 304 nor the main system block 306 in the first BIOS unit 202 has In case of data corruption. Therefore, the computer system can use the first BIOS unit 202 to complete the boot process.

FIG. 6 shows a flow chart of steps for restoring the main BIOS according to a preferred embodiment of the present invention. Please refer to Fig. 1, Fig. 2 and Fig. 6 in combination, when the second BIOS unit 204 is enabled and a recovery program needs to be executed, as described in step S602, the program code in the second BIOS unit 204 can be transferred from the bus interface 116, and copied to the storage area in the memory 106 through the chipset 104. Next, the second BIOS unit 204 can be disabled, and the first BIOS unit 202 can be enabled, as described in step S604.

In the program code copied to the storage area by the second BIOS unit 204, there is a recovery program. Therefore, the restoration procedure in this embodiment also includes executing the restoration procedure in the storage area, that is, step S606. At this point, this embodiment can copy the program code stored in the storage area to the first BIOS unit 202 as described in step S608 to restore the data of the first BIOS unit 202 . However, in some embodiments, after the first BIOS unit 202 completes the data recovery procedure, the computer system 100 can be restarted.

After sorting out the above description, the preferred embodiment of the present invention provides a flow of steps of a computer system startup method in FIG. 7 . Please refer to FIG. 7, when a computer system is turned on, as described in step S702, first execute the program code in the boot block of the first BIOS to perform a power self-test, and the bus in the computer system will start to transmit related bus signal. In addition, in this embodiment, as described in step S704, after a delay time, it may be checked whether the state of the above-mentioned bus signal (for example: CS# signal) is normal. Wherein, the delay time may be slightly longer than the time required for executing the boot block.

If after the delay time, it is found that the state of the bus signal is different from that of the bus signal under normal power-on conditions, such as being fixed at a voltage level (as shown in FIG. 4B or 4C), then perform step S706, which is to disable the first a BIOS, and enable a second BIOS. Therefore, in this embodiment, as described in step S708 , the second BIOS can be used to perform a recovery procedure on the first BIOS, just like the procedure disclosed in FIG. 6 . In addition, after the data of the first BIOS is restored, the computer system may be restarted as described in step S710, and steps such as S702 may be repeatedly executed.

In contrast, if the state of the bus signal is found to be normal during step S704 , for example, the voltage level is oscillating within a certain range, it means that the data of the boot block should not be damaged. At this point, step S712 can be performed, which is to further check whether the program code sum of the fixed boot block and the program code sum of the main system block in the first BIOS are equal to the corresponding default values.

As long as any of the program code sum of the fixed boot block and the program code sum of the main system block in the first BIOS is not equal to the corresponding default value, it means that the program in the fixed boot block or the main system block An error occurred in the code. At this point, steps such as S706 may be performed. On the contrary, if the program code sum of the fixed boot block in the first BIOS and the program code sum of the main system block are equal to the corresponding default values, then step S714 is performed, which is to execute the fixed boot block and the main system block. The program code in the computer system is used to complete the booting procedure of the computer system.

In summary, because the preferred embodiment of the present invention can check the state of the bus signal after a delay time, and perform a checksum procedure on the fixed boot block and the main system block, the present invention can accurately detect whether the BIOS An error occurred. In addition, since the present invention also has a second BIOS, when an error occurs in the first BIOS, the second BIOS can be used to recover quickly, thereby increasing the convenience of the recovery procedure.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and changes without departing from the spirit and scope of the present invention. modification, so the scope of protection of the present invention should be defined by the claims.

Claims (13)

1. A computer system, characterized in that, comprising: a first BIOS unit; a second BIOS unit; a bus; A detection unit, operatively connected to the bus, the first BIOS unit, and the second BIOS unit, to detect a bus signal in the bus; and A first delay unit, electrically connected to the detection unit, to control the detection unit to detect the state of the bus signal after a preset delay time, so that the detection unit switches to the first state according to the state of the bus signal The BIOS unit or the above-mentioned second BIOS unit is started. 2. The computer system according to claim 1, wherein the detection unit has a first terminal, a second terminal, and a third terminal, the first terminal is coupled to a first voltage, and the first terminal is coupled to a first voltage. The two terminals are operatively connected to the bus to receive the bus signal, and the third terminal is respectively operatively connected to the first BIOS unit and the second BIOS unit, so that the detection unit can be based on the bus signal. state, and output the state of the first terminal from the third terminal to the first BIOS unit and the second BIOS unit. 3. The computer system according to claim 1, wherein the detection unit further has a preset terminal and a clear terminal, the clear terminal is electrically connected to the first delay unit, and the preset terminal is disabled able. 4. The computer system according to claim 3, wherein said first delay unit comprises: a resistor electrically connected to the clearing terminal and a voltage source; and A capacitor is electrically connected to the clearing end and the ground respectively. 5. The computer system according to claim 1, further comprising: A buffer, electrically connected between the detection unit and the first BIOS unit and the second BIOS unit, to receive the state of the third terminal and send it to the first BIOS unit output system unit; and An inverter, electrically connected to the buffer and the second BIOS unit, for inverting the output of the buffer and then sending it to the second BIOS unit. 6. The computer system according to claim 5, wherein the buffer further comprises a first buffer unit, a second buffer unit, and a second delay unit, and the first buffer unit and the detection unit Electrically connected, the second buffer unit is respectively electrically connected to the first buffer unit, the second delay unit, the first BIOS unit, and the inverter. 7. The computer system according to claim 1, wherein when the state of the bus signal is different from the bus signal of normal startup, the detection unit outputs an output signal to the first BIOS unit, disabling the first BIOS unit so that the computer system can be powered on with the second BIOS unit. 8. The computer system according to claim 1, wherein the bus is a serial peripheral interface, a small number of pins interface, a front side bus, or a peripheral component interconnection interface. 9. A basic input and output system error detection method, applicable to a computer system, characterized in that the above error detection method comprises the following steps: performing a power supply self-test; checking the status of a bus signal in a bus in the computer system after a delay of a preset delay time; and When the state of the above-mentioned bus signal is different from the bus signal of the above-mentioned computer system when the computer system is normally powered on, it is determined that the above-mentioned BIOS is not normal. 10. The error detection method of the BIOS according to claim 9, wherein the bus is a serial peripheral interface, a small number of pin interface, a front side bus, or a peripheral component interconnection interface. 11. A booting method for a computer system, comprising the following steps: Executing a boot procedure with a first BIOS; checking a bus signal in a bus in the computer system after delaying for a preset delay time; and When the state of the above-mentioned bus signal is different from the bus signal of the above-mentioned computer system during normal startup, a second BIOS is used to start the computer system. 12. The booting method of the computer system according to claim 11, wherein when the state of the bus signal is the same as that of the bus signal when the computer system is normally booted up, the first basic input and output system is used to Start up. 13. The booting method of the computer system according to claim 11, wherein the bus is a serial peripheral interface, a small number of pin interface, a front side bus, or a peripheral component interconnection interface.

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