JP3116898B2 - Interface conversion circuit of subscriber circuit and signal conversion method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface conversion circuit of a subscriber circuit and a signal conversion method thereof, and is particularly suitable for multiplexing and transmitting information having different signal speeds, such as voice and data. The present invention relates to an interface conversion circuit for a subscriber circuit.

[0002]

2. Description of the Related Art Conventionally, in an area where telephone lines cannot be installed in a mountain area or the like, as shown in FIG. 6, a subscriber station apparatus 200 and an exchange 210 provided in the area are connected by a microwave 220. In addition, by transmitting the multiplexed signal to the exchange 200, a necessary line has been secured.

However, when such devices are to be provided in many regions, the types of the subscriber circuits 230 connected to the device 200 differ from region to region. It is necessary to design a subscriber station device equipped with each interface circuit.
There is a disadvantage that the design work becomes extremely complicated. In order to solve such a drawback, in the conventional apparatus, the necessary interface circuits are provided in the subscriber station apparatus 200 by fixing in advance the types and the number of the subscriber circuits that can be connected to the multiplexing apparatus. Was.

However, actually, since the types of the subscriber circuits 230 to be connected differ from region to region, necessary interface circuits are insufficient, and unnecessary interface circuits are installed without being used. There was a problem that a line could not be secured.

[0005]

SUMMARY OF THE INVENTION The object of the present invention is to remedy the above-mentioned disadvantages of the prior art and, in particular, to provide subscribers with whatever subscriber circuit is connected to the subscriber station equipment. An object of the present invention is to provide a new interface conversion circuit of a subscriber circuit and a signal conversion method thereof which are automatically connectable by automatically detecting the type of the circuit.

[0006]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, a first aspect of the interface circuit of the subscriber circuit according to the present invention is an interface conversion circuit of the subscriber circuit for converting information of different signal speeds from the subscriber circuit into a predetermined signal speed, An identification circuit for identifying the type of circuit, a clock generation circuit for generating a predetermined clock signal based on the identification result of the identification circuit, and outputting the clock signal to the subscriber circuit; and A timing signal generation circuit that outputs a predetermined timing signal to the subscriber circuit; and a signal from the subscriber circuit is written based on a write signal output from the timing signal generation circuit, and is read out at a predetermined timing. And a signal speed conversion circuit for converting the signal speed to a predetermined signal speed. A clock signal generated by the clock generation circuit is supplied to the timing generation circuit and the signal speed conversion circuit, and a third aspect is a configuration in which a plurality of outputs of the plurality of interface conversion circuits are output. A multiplexing circuit for multiplexing signals is provided, and the clock signal is generated using a reference clock of the multiplexing circuit. In a fourth aspect, the interface conversion circuit includes: Is provided with a control circuit, and when the control circuit receives a signal indicating the identification result from the identification circuit, outputs a frequency-divided signal corresponding to the identification result to the clock generation circuit, and based on the signal, the clock generation circuit Outputs the clock signal, and the fifth mode converts the output from the signal conversion circuit into a predetermined signal format. A signal format conversion circuit for converting the control signal is provided, and the control circuit extracts a predetermined control signal from the control signal, and incorporates this signal into the signal format as a control signal to a higher-level device. Is what you do.

Further, according to an embodiment of the signal conversion method for a subscriber circuit according to the present invention, the signal speed of the subscriber circuit is identified, a predetermined clock signal is generated based on the identification result, and the clock signal is generated based on the clock signal. In addition to supplying the signal to the subscriber circuit, the clock signal reads the signal of the subscriber circuit, converts the read signal into a signal having a predetermined speed, and multiplexes the signal with another signal whose speed has been converted. It is characterized by doing.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An interface conversion circuit according to the present invention provides a clock signal and a timing signal corresponding to a connected subscriber circuit to the subscriber circuit, and includes a signal speed conversion circuit and a signal format conversion circuit. And a common circuit for connecting to subscriber circuits having different interface conditions.

As shown in FIG. 1, the connected subscriber circuit 20 is identified by an interface identification circuit 90, and a clock and timing signal suitable for the subscriber circuit are output to the subscriber circuit 20. Further, the subscriber signal 12 from the subscriber circuit 20 is converted to a common signal speed by a signal speed conversion circuit 70, and further converted to a common signal format by a signal format conversion circuit 80, and a plurality of signals having different interface conditions are obtained. The signal from the subscriber circuit 20 is multiplexed by the multiplex distribution circuit 100.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an example of an interface conversion circuit for a subscriber circuit according to the present invention; 1 to 3 are block diagrams showing specific examples of an interface conversion circuit of a subscriber circuit according to the present invention. In these drawings, information on different signal speeds from the subscriber circuit 20 is stored at a predetermined signal speed. An interface conversion circuit 10 of a subscriber circuit for converting the clock signal into a clock signal, and an identification circuit 90 for identifying the type of the subscriber circuit 20; and a predetermined clock signal 6 based on the identification result of the identification circuit 90. A clock generation circuit 60 for outputting a signal 6 to the subscriber circuit 20; and a predetermined timing signal 9 based on the identification result of the identification circuit 90.
And a signal from the subscriber circuit 20 are written based on the write signal 13 output from the timing signal generation circuit 60 and read out at a predetermined timing. A signal speed conversion circuit 70 for converting the signal speed to a predetermined signal speed;
3 shows an interface conversion circuit of a subscriber circuit characterized by the following configuration.

Next, the present invention will be described in more detail. FIG.
, The interface identification circuit 90 receives the identification signal 1 from the subscriber circuit 20 connected to the interface identification circuit 90,
For example, identify whether the subscriber circuit is a telephone or ISDN. As a specific method of identification, as shown in FIG. 3, a number of signal lines 90a corresponding to the number of types are drawn from the subscriber circuit 20 to the interface identification circuit 90, and the state of this signal line is detected, whereby the subscriber is identified. Circuit 2
It is configured to identify the type of 0. The control circuit 50 receiving the detection signal 2 for detecting the type of the subscriber circuit from the interface identification circuit 90 outputs the frequency-divided signal 3 of the clock having the frequency corresponding to the subscriber circuit 20 to the clock generation circuit 40.
And a signal 4 indicating the identification result is output to the timing signal generation circuit 60.

When the clock generation circuit 40 receives the frequency-divided signal 3, the clock generation circuit 40
The master clock 5 from 0 is converted to a clock signal 6 having a frequency corresponding to the type of the subscriber circuit 20 and the subscriber circuit 2
0 and each circuit in the interface conversion circuit 10. A timing signal generation circuit 60 composed of a memory such as a ROM storing waveform data supplies a timing signal 9 such as a frame pulse corresponding to the subscriber circuit 20 to the subscriber circuit 20, and outputs a signal speed conversion circuit 70 and a signal The format conversion circuit 80 also supplies the signal conversion timing signal 7
And a write timing signal 8. The signal rate conversion circuit 70 receives the subscriber signal 1 from the subscriber circuit 20.
2 to a common signal rate. Further, the signal 15 is converted into a signal 15 of a common format by the signal format conversion circuit 80 and transmitted to the multiplexing circuit (multiplexing distribution circuit) 100. The multiplexing circuit 100 multiplexes the signal 15 converted into a common format from the plurality of subscriber circuits 20 as shown in FIG.

In the interface conversion circuit configured as described above, when the type of the connected subscriber circuit 20 is identified by the interface identification circuit 90, the result is output to the control circuit 50. The control circuit 50 outputs the frequency-divided signal 3 to a frequency-dividing circuit such as a counter provided in the clock generating circuit 40 so as to generate a clock signal having a frequency corresponding to the subscriber circuit 20.

At this time, the clock generation circuit 40 synchronizes the master clock 5 from the clock oscillation circuit 30 with the reference clock 15 of the reference clock generation circuit 110 using a PLL circuit or the like, and generates a clock having a frequency corresponding to the subscriber circuit 20. Generate signal 6. The clock signal 6 is not only supplied to the subscriber circuit 20 but also used by the timing signal generation circuit 60 and the signal speed conversion circuit 70. If the clock signal 6 supplied to the subscriber circuit 20 can be frequency-divided from the reference clock 15, the clock oscillation circuit 30 can be omitted, and the clock generation circuit 40 is composed of only a frequency division circuit such as a counter.

A timing signal generation circuit 60 composed of a ROM or the like generates a timing signal 9 such as a frame pulse using the signal 4 indicating the subscriber identification result from the control circuit 50 and the clock signal 6 from the clock generation circuit 40. And outputs it to the subscriber circuit 20. A signal speed conversion circuit 70 composed of a FIFO or the like writes the subscriber signal 12 from the subscriber circuit 20 with the write signal 13 from the timing signal generation circuit 60 and the clock 6 from the clock generation circuit 40,
The speed is converted into a signal 14 having the same frequency as the reference clock 15 by reading out the reference clock 15 from the reference clock generation circuit 110 and the readout signal 11 generated by the timing generation circuit 60 from the reference clock 15.

A signal format conversion circuit 80 composed of a dual port RAM or the like writes the speed conversion signal 14 output from the signal speed conversion circuit 70 into the RAM with the write timing signal 8 from the timing signal generation circuit 60, and By reading the signals at the determined common timing, the signals of all the subscriber circuits are converted into the signals 16 of the common format by the respective interface conversion circuits.
Convert to

The multiplexing circuit 100 is constructed by these conversion circuits.
Can receive signals of a common format synchronized with the reference clock 15 from all the subscriber circuits 20, multiplex these signals without being aware of the difference in interface conditions of the subscriber circuits 20, and Can be sent to the server. FIG. 5 is a drawing showing another example of the present invention.

Referring to FIG. 5, a control signal 21 from the subscriber circuit and a control signal 22 to the host device 150 are exchanged between the signal format conversion circuit 80 and the control circuit 50. Thereby, the control signal 21 from the subscriber circuit is
Is once taken into the control device 50, converted into a common control signal format, and multiplexed by the signal format conversion circuit 80 as a control signal to the host device 150.

By using the above-mentioned control signal in the host device 150, the subscriber signal 12 transmitted with a small number of bits can be obtained.
Can be reproduced in accordance with the control signal 22. Therefore, this configuration enables efficient information transmission with a small number of transmission bits.

[0020]

As described above, the interface conversion circuit of the subscriber circuit and the signal conversion method according to the present invention are configured as described above, so that subscriber circuits having different interface conditions are connected using the same interface conversion circuit. Therefore, the subscriber station device can be used efficiently.

In addition, since the same subscriber station device can be used, it has excellent features such as easy design and construction work.

[Brief description of the drawings]

FIG. 1 is a block diagram of an interface conversion circuit according to the present invention.

FIG. 2 is a block diagram showing a connection state of the interface conversion circuit according to the present invention.

FIG. 3 is a diagram of a main part for describing types of subscriber circuits.

FIG. 4 is a block diagram of another specific example of the interface conversion circuit according to the present invention.

FIG. 5 is a block diagram illustrating a conventional technique.

FIG. 6 is a block diagram illustrating a conventional technique.

[Explanation of symbols]

 1 Identification signal 2 Detection signal 3 Divided signal 4 Signal indicating identification result 6 Clock signal 8 Write timing signal 9 Frame pulse 10 Interface conversion circuit 11 Read signal 12 Subscriber signal 13 Write signal 14 Speed conversion signal 15 Reference clock 16 Common format Signal 30 clock oscillation circuit 40 clock generation circuit 50 control circuit 60 timing signal generation circuit 70 signal speed conversion circuit 80 signal format conversion circuit 90 interface identification circuit 100 multiplexing circuit (multiplex distribution circuit) 110 reference clock generation circuit 150 host device

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/02 H04L 12/50 H04Q 1/30-1/56 H04Q 3/42 H04Q 3/52-3 / 62 H04Q 3/70-3/74 H04Q 11/00-11/04

Claims (6)

(57) [Claims] 1. An interface conversion circuit of a subscriber circuit for converting information of a different signal speed from a subscriber circuit into a predetermined signal speed, comprising: an identification circuit for identifying a type of the subscriber circuit; A clock generation circuit that generates a predetermined clock signal based on the identification result of the above, and outputs the clock signal to the subscriber circuit; and a timing that outputs a predetermined timing signal to the subscriber circuit based on the identification result of the identification circuit. A signal generation circuit, a signal speed conversion circuit for writing a signal from the subscriber circuit based on a write signal output from the timing signal generation circuit, and reading out the signal at a predetermined timing to convert the signal to a predetermined signal speed; An interface conversion circuit for a subscriber circuit, comprising: 2. The interface conversion circuit according to claim 1, wherein the clock signal generated by the clock generation circuit is supplied to the timing generation circuit and a signal speed conversion circuit. 3. A multiplexing circuit for multiplexing output signals of the plurality of interface conversion circuits, wherein the clock signal is generated using a reference clock of the multiplexing circuit. An interface conversion circuit for the subscriber circuit as described. 4. A control circuit is provided in the interface conversion circuit, and when the control circuit receives a signal indicating the identification result from the identification circuit, outputs a frequency-divided signal corresponding to the identification result to the clock generation circuit. 4. The interface conversion circuit for a subscriber circuit according to claim 1, wherein the clock generation circuit outputs the clock signal based on the signal. 5. A signal format conversion circuit for converting an output from the signal conversion circuit into a predetermined signal format is provided. The control circuit extracts a predetermined control signal from the control signal, and converts the signal into a higher-level device. 5. The interface conversion circuit for a subscriber circuit according to claim 1, wherein the interface conversion circuit is configured to be incorporated in the signal format as a control signal to the subscriber circuit. 6. A type of a signal of a subscriber circuit is identified, a predetermined clock signal is generated based on a result of the identification, the clock signal is supplied to the subscriber circuit, and the subscription is performed based on the clock signal. A signal conversion method for a subscriber circuit, comprising: reading a signal from a subscriber circuit; converting the read signal into a signal having a predetermined speed; and multiplexing the signal with another speed-converted signal.