JP3112470B2 - Connection structure of electric element and liquid crystal panel - Google Patents
Connection structure of electric element and liquid crystal panelInfo
- Publication number
- JP3112470B2 JP3112470B2 JP02191221A JP19122190A JP3112470B2 JP 3112470 B2 JP3112470 B2 JP 3112470B2 JP 02191221 A JP02191221 A JP 02191221A JP 19122190 A JP19122190 A JP 19122190A JP 3112470 B2 JP3112470 B2 JP 3112470B2
- Authority
- JP
- Japan
- Prior art keywords
- electric element
- substrate
- wiring pattern
- liquid crystal
- connection structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims description 58
- 239000000853 adhesive Substances 0.000 claims description 34
- 230000001070 adhesive effect Effects 0.000 claims description 34
- 239000012790 adhesive layer Substances 0.000 claims description 10
- 239000010419 fine particle Substances 0.000 claims description 10
- 239000011521 glass Substances 0.000 description 22
- 239000004065 semiconductor Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 8
- 238000007689 inspection Methods 0.000 description 7
- 230000001172 regenerating effect Effects 0.000 description 6
- 239000002245 particle Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電気素子の接続構造及び電気素子の接続方
法に関する。具体的には、半導体チップが基板上に搭載
された液晶表示装置及びその製造方法に関するものであ
る。The present invention relates to a connection structure of an electric element and a method of connecting an electric element. More specifically, the present invention relates to a liquid crystal display device having a semiconductor chip mounted on a substrate and a method for manufacturing the same.
従来の電気素子の接合構造は第２図（ａ）〜（ｃ）の
ようなものであった。第２図において、21は基板、22は
基板上の配線パターン、23は電気素子、24は電気素子の
電極を示す。まず第２図（ａ）は、基板上の配線パター
ンにプローバ25をおしあてて基板の検査をしている工程
を示す。次に第２図（ｂ）は、第２図（ａ）において合
格になった基板について導電性微粒子27を拡散・混在さ
せた接着剤シート26を載置した工程を示す。FIGS. 2 (a) to 2 (c) show a conventional electrical element bonding structure. In FIG. 2, 21 is a substrate, 22 is a wiring pattern on the substrate, 23 is an electric element, and 24 is an electrode of the electric element. First, FIG. 2A shows a process of applying a prober 25 to a wiring pattern on a substrate to inspect the substrate. Next, FIG. 2 (b) shows a process in which an adhesive sheet 26 in which conductive fine particles 27 are diffused and mixed is placed on a substrate which has passed in FIG. 2 (a).
この導電粒子を拡散・混在させた接着剤シートは厚さ
20〜30μｍ、導電微粒子の径は５〜12μｍである。The adhesive sheet in which the conductive particles are diffused and mixed has a thickness
20 to 30 μm, and the diameter of the conductive fine particles is 5 to 12 μm.
また、第２図（ｃ）は、電気素子の上面より加熱なが
ら加圧し、接着剤を硬化させ、電気素子を基板の上に接
合させた様子を示す。FIG. 2 (c) shows a state in which pressure is applied while heating from the upper surface of the electric element, the adhesive is cured, and the electric element is bonded on the substrate.
しかし、従来の電気素子の接合構造は第２図より明ら
かなように幾多の問題点を有するものであった。However, the conventional electric element bonding structure has a number of problems as apparent from FIG.
まず電気素子23を基板21の上に接合する時電気素子の
電極24と対応する基板上の配線パターン22とは平面的な
位置合わせを行なう必要がある。First, when the electric element 23 is bonded onto the substrate 21, it is necessary to perform planar alignment between the electrode 24 of the electric element and the corresponding wiring pattern 22 on the substrate.
しかし、この基板が機能的な基板であり、検査を行な
って良品の基板のみを選別する必要がある場合、第２図
（ｃ）のような電気素子を基板上に接合する工程の前
に、第２図（ａ）のようなプローバ25を使った検査工程
が必要となる。However, when this substrate is a functional substrate and it is necessary to perform inspection and select only non-defective substrates, before the step of bonding the electric elements on the substrate as shown in FIG. An inspection process using a prober 25 as shown in FIG. 2A is required.
この検査工程も当然の事ながら、プローバ25の先端位
置と基板の配線パターンの位置とを平面的に位置合わせ
する必要がある。この結果、煩雑で作業工数の大きな位
置合わせ工程が上記の電気素子の電極と基板の配線パタ
ーンとの位置合わせと合わせて２回必要ということにな
り、全体として作業工数の大きな、従って製造コストが
大きなものとなってしまうものであった。As a matter of course, it is necessary to align the position of the tip of the prober 25 with the position of the wiring pattern on the board in a planar manner. As a result, a complicated positioning process requiring a large number of man-hours is required twice in addition to the positioning between the electrodes of the electric elements and the wiring patterns on the substrate. It was a big one.
さらに電気素子23も別個に使用に検査しておく必要が
あり、検査もれがあった場合、そのまま第２図（ｃ）の
ように接着剤を硬化させて接合した場合、接合後の良品
率が下がるものであった。Further, it is necessary to separately inspect the electric element 23 for use. If there is any omission in the inspection, if the adhesive is cured and bonded as shown in FIG. Was going down.
さらに、本説明の様に、導電性微粒子を拡散、混在さ
せた接着剤を用いて、電気素子を基板上へ接合して、そ
の後、不良が発見された場合、上記接着剤が硬化してい
るにもかかわらず、電気素子を基板から剥離して再生し
なければならない。しかし、上記接着剤が硬化している
為、剥離再生は極めて難しく、剥離再生作業の工数が大
きいばかりでなく、剥離再生が失敗する確率も高いもの
である。Furthermore, as described in the present description, the electric element is bonded onto the substrate using an adhesive in which conductive fine particles are diffused and mixed, and then, when a defect is found, the adhesive is cured. Nevertheless, the electric element must be peeled off from the substrate and regenerated. However, since the adhesive is hardened, peeling and regenerating is extremely difficult. Not only is the man-hour for peeling and regenerating work large, but also the probability of peeling and regenerating failure is high.
そこで、本発明は従来のこの様な欠点を解決し電気素
子と基板の位置合わせを容易にし、不良時の剥離再生を
不用とする事を目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to solve the conventional drawbacks described above, to facilitate the alignment between the electric element and the substrate, and to eliminate the need for peeling and regenerating when there is a defect.
本発明の電気素子の接続構造は、配線パターンが形成
されている基板と、当該基板の前記配線パターンに電気
的接続される複数の電極を有した電気素子の接続構造で
あって、前記電気素子は、導電性微粒子を含む第１の接
着剤層と、前記電気素子の前記複数の電極と前記基板の
前記配線パターンの対応部位を除いて前記電極の間の前
記第１の接着剤層上に形成される第２の接着剤シートと
を介在させて前記基板と接合されていることを特徴とす
る。The connection structure of an electric element of the present invention is a connection structure of an electric element having a substrate on which a wiring pattern is formed, and a plurality of electrodes electrically connected to the wiring pattern of the substrate, wherein the electric element A first adhesive layer containing conductive fine particles, and the plurality of electrodes of the electric element and the first adhesive layer between the electrodes except for portions corresponding to the wiring pattern of the substrate. It is characterized by being joined to the substrate with a second adhesive sheet formed therebetween.
又、本発明の液晶パネルは、配線パターンが形成され
ている基板と、前記配線パターンに電気的接続される複
数の電極を有した電気素子と、を具備する液晶パネルで
あって、前記電子素子は、導電性微粒子を含む第１の接
着剤層と、前記電気素子の前記複数の電極と前記基板の
前記配線パターンの対応部位を除いて前記電極の間の前
記第１の接着剤剤上に形成された第２の接着剤シートと
を介在させて前記基板と接合されてることを特徴とす
る。The liquid crystal panel of the present invention is a liquid crystal panel including: a substrate on which a wiring pattern is formed; and an electric element having a plurality of electrodes electrically connected to the wiring pattern. A first adhesive layer containing conductive fine particles, and the plurality of electrodes of the electric element and the first adhesive between the electrodes except for portions corresponding to the wiring pattern of the substrate. It is characterized by being bonded to the substrate with the formed second adhesive sheet interposed.
以下に本発明の実施例を図面を用いて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明による電気素子の接続
構造を示すものである。1 (a) to 1 (d) show a connection structure of an electric element according to the present invention.
第１図において、１は基板たるガラス基板、２はガラ
ス基板上の配線パターン、３は電気素子たる半導体チッ
プ、４は半導体チップの電極、５は導電異方性接着剤シ
ート、６は導電性微粒子、６は液晶パネル、８はシール
部、９は液晶層、10は液晶駆動用電極、11は接着剤シー
トを示す。In FIG. 1, 1 is a glass substrate as a substrate, 2 is a wiring pattern on the glass substrate, 3 is a semiconductor chip as an electric element, 4 is an electrode of the semiconductor chip, 5 is a conductive anisotropic adhesive sheet, and 6 is conductive. Fine particles, 6 is a liquid crystal panel, 8 is a seal portion, 9 is a liquid crystal layer, 10 is a liquid crystal driving electrode, and 11 is an adhesive sheet.
第１図（ａ）は複数個の突起電極を有する電気素子た
る半導体チップと、これに対応する複数の配線パターン
が形成された液晶パネルのガラス基板の一部の接合前の
断面図を示す。この配線パターンの一部は液晶パネルの
液晶駆動用電極と電気的に結びついているものである。FIG. 1 (a) is a cross-sectional view of a part of a glass substrate of a liquid crystal panel on which a semiconductor chip as an electric element having a plurality of projecting electrodes and a plurality of wiring patterns corresponding thereto are formed before bonding. A part of this wiring pattern is electrically connected to the liquid crystal driving electrode of the liquid crystal panel.
第１図（ｂ）は、上記基板たるガラス基板の上に配さ
れた配線パターン部上に導電性微粒子を拡散・混在させ
た薄い導電異方性接着剤シートと、非導電性の接着剤シ
ートを載置したものであり、上記非導電性の接着剤シー
トは上記電気素子の突起電極と上記基板の配線パターン
の対応部位を除いて配されている。導電性粒子の粒径は
上記薄い導電異方性接着剤シートの厚さとほぼ同等にし
てある。FIG. 1 (b) shows a thin conductive anisotropic adhesive sheet in which conductive fine particles are diffused and mixed on a wiring pattern portion disposed on the glass substrate, and a non-conductive adhesive sheet. The non-conductive adhesive sheet is disposed except for a portion corresponding to the protruding electrode of the electric element and the wiring pattern of the substrate. The particle size of the conductive particles is substantially equal to the thickness of the thin conductive anisotropic adhesive sheet.
第１図（ｃ）は半導体チップを上記導電異方性の接着
剤シートと非導通性の接着剤シートを介してガラス基板
上に常温下で押しつけているものであり、半導体チップ
の突起電極とガラス基板の配線パターンと平面的に位置
があっている。上記導電異方性接着剤シートは薄い為、
半導体チップをガラス基板に押しつけると、半導体チッ
プの突起電極とガラス基板の配線パターンは電気的導通
状態にする事ができる。この状態で外部から駆動信号を
半導体チップひいてはガラス基板に入力してやれば、液
晶パネルを駆動して検査する事ができる。FIG. 1 (c) shows a semiconductor chip pressed at room temperature on a glass substrate via the conductive anisotropic adhesive sheet and the non-conductive adhesive sheet. There is a planar position with the wiring pattern of the glass substrate. Because the conductive anisotropic adhesive sheet is thin,
When the semiconductor chip is pressed against the glass substrate, the projecting electrodes of the semiconductor chip and the wiring pattern of the glass substrate can be brought into an electrically conductive state. In this state, if a driving signal is externally input to the semiconductor chip and thus to the glass substrate, the liquid crystal panel can be driven and inspected.
さらに第１図（ｄ）は、第１図（ｃ）の工程において
検査合格となったものについて、半導体チップの上から
加熱しながら加圧し、接着剤層を硬化させて、半導体チ
ップとガラス基板を強固に接合、固定したものである。
この時、半導体チップの突起電極とガラス基板の配線パ
ターンは導電性微粒子を介して電気的導通状態にある。Further, FIG. 1 (d) shows that the semiconductor chip and the glass substrate which were passed the inspection in the step of FIG. Are firmly joined and fixed.
At this time, the protruding electrodes of the semiconductor chip and the wiring pattern of the glass substrate are in an electrically conductive state via the conductive fine particles.
導電異方性接着剤シートは薄いので、導電異方性接着
剤シートのみで半導体チップとガラス基板を接合した場
合、総接着剤量が足りず、半導体チップとガラス基板の
間に接着剤が充分充填されず大きな気泡あるいはすきま
が残ってしまう。その結果、電気素子のガラス基板への
接合強度が弱い、電気素子の突起電極とガラス基板の配
線パターンとの間の電気的導通の接続信頼性の低下等の
問題が起こるものであった。Since the conductive anisotropic adhesive sheet is thin, when the semiconductor chip and the glass substrate are joined only with the conductive anisotropic adhesive sheet, the total adhesive amount is insufficient, and the adhesive between the semiconductor chip and the glass substrate is sufficient. Large bubbles or gaps remain without being filled. As a result, there have been problems such as a low bonding strength of the electric element to the glass substrate and a reduction in connection reliability of electrical conduction between the projecting electrode of the electric element and the wiring pattern of the glass substrate.
本発明においては、薄い導電異方性接着剤シートと重
ね合わせて非導電性の接着剤シートがあり、この非導電
性の接着剤シートは電気素子の突起電極部を除いて配さ
れている為、電気素子の突起電極とガラス基板の配線パ
ターンの電気的導通を容易に確保した上で、電気素子た
る半導体チップとガラス基板の間の総接着剤量を充分に
確保して充填し、気泡を抱き込む事なく、半導体チップ
をガラス基板の上に接合することができるものであり、
その結果、半導体チップのガラス基板への接合強度を向
上させ、半導体チップの突起電極とガラス基板配線パタ
ーンとの間の電気的導通の接続信頼性を極めて向上させ
るものである。In the present invention, there is a non-conductive adhesive sheet superimposed on a thin conductive anisotropic adhesive sheet, and the non-conductive adhesive sheet is disposed except for the protruding electrode portion of the electric element. After easily securing the electrical continuity between the protruding electrodes of the electric element and the wiring pattern of the glass substrate, the total adhesive amount between the semiconductor chip as the electric element and the glass substrate is sufficiently ensured and filled, and bubbles are formed. It is possible to join a semiconductor chip on a glass substrate without hugging,
As a result, the bonding strength of the semiconductor chip to the glass substrate is improved, and the connection reliability of electrical continuity between the protruding electrode of the semiconductor chip and the wiring pattern of the glass substrate is significantly improved.
第１図（ｄ）においては、第１図（ｃ）において半導
体チップとガラス基板を位置合わせしたものをそのまま
加熱加圧する為、煩雑で工数の大きな位置合わせ工程
が、全工程で一回ですむ為製造コストが少なくてすむも
のである。In FIG. 1 (d), since the semiconductor chip and the glass substrate in FIG. 1 (c) are heated and pressurized as they are, a complicated and large number of man-hours positioning process is required only once in all processes. Therefore, the production cost is low.
さらに、本発明による電気素子の接続構造は第１図
（ｃ）の検査の後、合格の品物のみを第１図（ｄ）の様
に加熱加圧して接着剤層を硬化させれば、接合後の良品
率もおのずと向上するものである。従って剥離再生の必
要性も極端に低減され、作業の効率も極めて向上するも
のである。Further, the connection structure of the electric element according to the present invention is such that, after the inspection of FIG. 1 (c), only the passed products are heated and pressed as shown in FIG. 1 (d) to cure the adhesive layer. The rate of non-defective products will naturally increase. Therefore, the necessity of peeling and regenerating is extremely reduced, and the working efficiency is extremely improved.
本発明は以上説明したように、電気素子と基板の間に
薄い導電異方性接着剤層と非導電性の接着剤を二重に形
成することによって、電気素子と基板を初期的な電気的
接続状態にして検査をする事を可能にして、位置合わせ
工数を低減し、剥離再生必要な確立を低減させ、さらに
は接着強度を向上させて、接続信頼性を向上させる効果
がある。As described above, the present invention forms an initial electrical connection between an electric element and a substrate by forming a thin conductive anisotropic adhesive layer and a non-conductive adhesive between the electric element and the substrate. It is possible to perform the inspection in the connection state, thereby reducing the number of alignment steps, reducing the necessity of peeling and regenerating, and improving the bonding strength, thereby improving the connection reliability.
第１図（ａ）〜（ｄ）は、本発明による電気素子の接続
構造を示す図。 第２図（ａ）〜（ｃ）は、従来の電気素子の接続構造を
示す図。 １……ガラス基板 ２……配線パターン ３……半導体チップ ４……突起電極 ５……導電性接着剤シート ６……導電性微粒子 ７……液晶パネル ８……シール部 ９……液晶層 10……液晶駆動用電極 11……接着剤シート 21……基板 22……配線パターン 23……電気素子 24……電極 25……検査用プローバ 26……接着剤シート 27……導電性粒子1 (a) to 1 (d) are views showing a connection structure of an electric element according to the present invention. 2 (a) to 2 (c) are views showing a connection structure of a conventional electric element. DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Wiring pattern 3 ... Semiconductor chip 4 ... Protruding electrode 5 ... Conductive adhesive sheet 6 ... Conductive fine particles 7 ... Liquid crystal panel 8 ... Seal part 9 ... Liquid crystal layer 10 …… Electrode for liquid crystal drive 11 …… Adhesive sheet 21 …… Substrate 22 …… Wiring pattern 23 …… Electrical element 24 …… Electrode 25 …… Prober for inspection 26 …… Adhesive sheet 27 …… Conductive particles
フロントページの続き (56)参考文献 特開 昭61−279139（ＪＰ，Ａ) 特開 平３−29207（ＪＰ，Ａ) 特開 昭64−59826（ＪＰ，Ａ) 特開 平２−10316（ＪＰ，Ａ) 実開 昭63−80844（ＪＰ，Ｕ)Continuation of the front page (56) References JP-A-61-279139 (JP, A) JP-A-3-29207 (JP, A) JP-A-64-59826 (JP, A) JP-A-2-10316 (JP) , A) Japanese Utility Model Showa 63-80844 (JP, U)
Claims (2)
電極を有した電気素子の接続構造であって、 前記電気素子は、導電性微量子を含む第１の接着剤層
と、前記電気素子の前記複数の電極と前記基板の前記配
線パターンの対応部位を除いて前記電極の間の前記第１
の接着剤層上に形成される第２の接着剤シートとを介在
させて前記基板と接合されていることを特徴とする電気
素子の接続構造。1. A connection structure of a substrate on which a wiring pattern is formed, and an electric element having a plurality of electrodes electrically connected to the wiring pattern of the substrate, wherein the electric element is a conductive trace. A first adhesive layer including a chip, and a first adhesive layer between the electrodes except for a portion corresponding to the plurality of electrodes of the electric element and the wiring pattern of the substrate.
A connection structure for an electric element, wherein the connection structure is connected to the substrate via a second adhesive sheet formed on the adhesive layer of (1).
た前記素子と、を具備する液晶パネルであって、 前記電子素子は、導電性微粒子を含む第１の接着剤層
と、前記電気素子の前記複数の電極と前記基板の前記配
線パターンの対応部位を除いて前記電極の間の前記第１
の接着剤剤上に形成された第２の接着剤シートとを介在
させて前記基板と接合されていることを特徴とする液晶
パネル。2. A liquid crystal panel comprising: a substrate on which a wiring pattern is formed; and an element having a plurality of electrodes electrically connected to the wiring pattern. A first adhesive layer containing fine particles, and a first adhesive layer between the electrodes except for the plurality of electrodes of the electric element and a portion corresponding to the wiring pattern of the substrate;
A liquid crystal panel which is joined to the substrate via a second adhesive sheet formed on the adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02191221A JP3112470B2 (en) | 1990-07-19 | 1990-07-19 | Connection structure of electric element and liquid crystal panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02191221A JP3112470B2 (en) | 1990-07-19 | 1990-07-19 | Connection structure of electric element and liquid crystal panel |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8695199A Division JP3316472B2 (en) | 1999-03-29 | 1999-03-29 | Method of connecting electric element and method of manufacturing liquid crystal panel |
| JP8695099A Division JPH11330165A (en) | 1999-03-29 | 1999-03-29 | Connection structure of electric element and liquid crystal panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0476929A JPH0476929A (en) | 1992-03-11 |
| JP3112470B2 true JP3112470B2 (en) | 2000-11-27 |
Family
ID=16270914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02191221A Expired - Fee Related JP3112470B2 (en) | 1990-07-19 | 1990-07-19 | Connection structure of electric element and liquid crystal panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3112470B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997039611A1 (en) * | 1996-04-16 | 1997-10-23 | Matsushita Electric Industrial Co., Ltd. | Method and device for removing ic component |
| JP3343642B2 (en) | 1996-04-26 | 2002-11-11 | シャープ株式会社 | Tape carrier package and liquid crystal display |
| JP4151420B2 (en) * | 2003-01-23 | 2008-09-17 | セイコーエプソン株式会社 | Device manufacturing method |
| DE102020116531A1 (en) * | 2020-06-23 | 2021-12-23 | Preh Gmbh | Input device with movable handle on a capacitive detection surface and capacitive coupling devices |
-
1990
- 1990-07-19 JP JP02191221A patent/JP3112470B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0476929A (en) | 1992-03-11 |
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