JP3093218B2 - Digital image processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital image forming apparatus that forms a mosaic image by subjecting serially input digital image data applied to a digital copying machine or the like to predetermined processing. Regarding the image processing device, three line memories are provided so that a mosaic image can be formed in real time without using a large-capacity frame memory or complicated calculations, and writing / reading operations for these are alternately performed. By switching, the data processing is given a margin of time, and the image data in the unit block is represented by the pixel data sampled at predetermined intervals from the memory in the main scanning direction and the scanning direction, respectively. The present invention relates to a digital image processing device that forms an image.

[Conventional technology]

Recently, electronic image recording means such as digital color copiers and digital color printing machines have been required to reproduce original images on paper with extremely high fidelity, and have also applied certain processing to image data to provide unique aesthetics. There is an increasing demand for fostering mosaic images, and mosaic image processing can be cited as one of the representative ones.

Conventionally, as a method of forming a mosaic image, a manuscript image is formed into a large number of rectangular regions (hereinafter, referred to as “unit blocks”) of a certain size.
In general, a representative point is defined in the block, and the color and density of the representative point replace the entire area of the unit block.

[Problems to be solved by the invention]

Conventional plate making total scanner and DTP (Data Top Publ
In the mosaic function (function to form a mosaic image) such as ishing), image data of all original images is temporarily stored in a large-scale frame memory (two-dimensional image memory),
Through complicated calculations by U, the representative points in each unit block were accurately determined. For this reason, there has been a problem that the apparatus becomes large and expensive, and furthermore, real-time processing of data becomes impossible.

The present invention has been made in view of the above, and has as its object to realize a real-time process on data by avoiding an increase in size and cost of the device, averaging representative points in each unit block.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a digital image processing apparatus for forming a mosaic image by performing predetermined processing on digital image information. And the data read from the line memory
Means for sampling each predetermined number in the main scanning direction and the sub-scanning direction to form a unit block, and averaging by replacing read data included in the unit block with sampling data. Is provided.

Another object of the present invention is to provide a digital image processing apparatus to which an area generating means for designating a mosaic image area is added in addition to the above.

[Operation] The digital image processing apparatus according to the present invention stores digital image data input sequentially one by one alternately.
By alternately switching the writing / reading operation to the memory of the system, image data is extracted every N pixels in the main scanning direction and every M pixels in the sub-scanning direction. The entire image data in the rectangular area including the M × N pixels is replaced and transferred to the image recording unit at a predetermined timing.

In addition, the mosaic function is activated / released in a rectangular area arbitrarily set in the entire image plane.

〔Example〕

Hereinafter, digital image processing according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining the structure of the present apparatus. An image reading section 1 for reading a document image as digital data while scanning the image, an image processing section 2 for performing predetermined processing and processing on the image data, The image recording unit 3 that prints the image data supplied from the processing unit 2 on transfer paper constitutes an electronic image printing unit.

The image processing unit 2 executes mosaic processing using three line memories. First, a case where two line memories are used will be described.

FIG. 2 is a block diagram showing an example of the configuration of an image processing unit (a main part of the present invention). Reference numerals 301 and 302 denote first and second system memories, respectively, each of which stores an image for one line in the main scanning direction. It has a function of storing data. While image data is being written to one, the same data is read from the other. That is, the memories 301 and 302 for the first and second systems perform the functions of writing and reading while being alternately exchanged. Reference numerals 101 and 102 denote input registers for the first and second systems, respectively, for temporarily storing input image data for one line and outputting the image data to the first and second system memories 301 and 302, respectively. 201 is the pixel clock (hereinafter “CL
K)), a write address counter for counting the write addresses of the first and second system memories 301 and 302, and similarly a read address counter 202 for counting the read addresses. 103 and 104 are write address buffers for the first and second systems, respectively, 105 and 106 are read address buffers for the first and second systems, respectively, and 401 is an output register control for controlling the operation of the output registers 107 and 108 for the first and second systems. Department. Also, 107,1
08 is a first and second system output register, respectively, and 109 is a selector that selects one of the read values from 107 and 108 and supplies it to the next step (in this case, the image recording unit 3 shown in FIG. 1). . Reference numeral 402 denotes a memory control unit that controls the operation of the entire image processing unit.

The operation when the mosaic function is canceled first (in the case of normal image recording) in the configuration of FIG. 2 will be described.

The output of the read address counter 202 remains unchanged from the first and second
Input to the system read address buffers 105 and 106. As described above, when data writing to the first system memory 301 is in progress, data already stored is read from the second system memory 302, and its function is exchanged every predetermined period. The operation of these two systems will be described in parallel below.

The original image is read as digital data by an image reading unit (1 in FIG. 1) for each line, and the input register 101
The data is sequentially stored in the memory 301 (302) via (102). Each time data for one pixel is stored, the write address counter 201 counts one, and the write address buffer 103
The count value (read address) is stored in the memory 301 via (104).
(302), and the write address of 301 (302) advances by one address.

At the same time, data is read from the memory 302 (301). That is, the read address counter 202
As in the case of the write address counter 201, the count operation is repeated in response to the CLK pulse, and the count value passes through the read buffer 502 (during function stop) as it is and passes through the read address buffer 106 (105). And transmitted to the memory 302 (301). Therefore, the read address of the memory 302 (301) advances by one address. As a result, the memory 302 (301)
Data reading from the memory 302 (301) is performed in parallel with data writing to the memory 302.

The data read one pixel at a time from the memory 302 (301) passes through the output register 108 (107),
It is output to the next step (image recording unit 3) via 9. The selector 109 selects the output register 108 (107) when data is being read from the memory 302 (301).
When the reading of one line of data is completed, the selector 109
Switches and selects the output register 107 (108).

All the operations described above are controlled by a control signal output from the memory control unit 402 to each unit.

Next, in order to obtain a grid-like pattern as shown in FIG. 3 using N × M pixels as a unit block by the configuration of FIG. 108 (107) fetches data once every N times, and thereafter repeats this data N times and sends it to the selector 109. Even if the data processing for one line is completed, the switching of the write / read operation of the memory 301 (302) is not performed, and the data for M lines is repeatedly read from the 302 (301), and the next step (image recording unit) Sent to 3).

By appropriately shifting the data output timing from the output registers 108 and 107, the mosaic pattern shown in FIG. 4 can be formed.

In the two types of mosaic functions described above, original image data is sampled every N pixels in the main scanning direction and every M pixels in the sub-scanning direction, and all image data in a unit block is sampled by the data. Since it is a replacement, the device can be simplified and economical, and real-time image processing can be performed. This can be said to be a remarkable improvement over the conventional method of strictly calculating a representative point in a unit block for two-dimensional image data stored in a large-scale frame memory. On the other hand, the configuration of the present invention has a drawback that the operation of determining the representative point is not strict, but in many cases, there is a relatively strong correlation between the pixel data in the unit blocks. Substantially satisfactory results are obtained with some configurations.

Next, a circuit (FIGS. 5 and 6
FIG. 401 is a division register, 40
2 to 403 are adders; 101 is a write address register for correcting an address shift in the averaging process; 201 is a write address counter; 202 is a read address counter; 102 is a one-system write address buffer; Is a write address buffer for two systems, 104 is a write address buffer for three systems, 105 is an averaged read address buffer for one system, 106 is an averaged read address buffer for two systems, and 107 is an averaged read address for three systems. Reference numeral 108 denotes a read address buffer for one system, 109 denotes a read address buffer for two systems, 301 denotes a memory for one system, 302 denotes a memory for two systems, and 303 denotes a memory for three systems.
Reference numeral 00 denotes a selector that switches at the same time as the toggle operation between the one-system memory 301 and the two-system memory 302, and selects the memory that has not been read in the read address counter 202. Reference numerals 110 to 11n denote output registers. A group is constituted, 501 is a selector, and 405 is an averaging register.

In the above configuration, FIG. 7 is a timing chart in the line direction, and FIG. 8 is a timing chart in the image clock direction, where the mosaic size is 4 × 4.
Is shown.

Further, in FIG. 7, the timing chart corresponding to (1) indicates a normal toggle operation, and the timing chart corresponding to (2) indicates an operation for forming a mosaic. At this time, a mosaic pattern shown in FIG. 3 is formed.

 Hereinafter, the operation will be described in detail.

First line (odd line) The input image data is divided by the division register 401 according to the mosaic size. The output of the division register 401 is input to the adder 404, and the output of the division register 401 is directly output from the adder 404 and input to the three-system memory. Each time one piece of this data is stored, the write address counter 201 performs a count operation, and sends an address to the three-system memory 303 via the write address register 101 and the three-system write address buffer 104. At this time, the read address counter 202 performs a counting operation in the same manner as the write address counter 201, and the two-system memory 302 [the one-system read address buffer 108] via the two-system read address buffer 109 [the one-system read address buffer 108]. memory
301] to read memory data. The data read from the two-system memory 302 (the one-system memory 301) is input to the output register 111 [110], and the selector
Shift to registers 112, 113,... 11n via 501. Here, the averaging register 405 sets the selector 501, the output registers 112, 113,.
Averaging is performed on N pieces of data among the pieces of data. Therefore, the output of the averaging register 405 changes every N times by this operation, and the mosaic formation in the pixel direction is performed.

Second line (even line) The input image data is divided by the division register 401 according to the mosaic size. The output of the division register 401 is input to an adder 402 [403]. At the other input of the adder 402 [403], the three-system memory 303 written in the first line is read out via the three-system averaging read address buffer 107 based on the address of the write address counter 201. The output added by the adder 402 [403] is input to the one-system memory 301 [two-system memory 302]. Each time one piece of data is stored, the write address counter 201 performs a count operation, and passes through the write address register 101, the write address buffer 102 for one system (the write address buffer 103 for two systems), and the data for the three systems. Memory 3
Send the address to 03.

Subsequent two-system memory 302 [one-system memory 301]
Is the same as that of the first line described above, and a description thereof will be omitted.

Third line (odd lines other than the first line) In this case, since the operation is substantially similar to the operation of the first line, only portions different from the operation of the first line will be described.

The input of the adder 404 is the output of the division register 401 and the one-system memory 301 [the two-system memory 30] written in the previous line.
2] is read out from the address of the write address counter 201 via the one-system averaged read address buffer 105 [the two-system averaged read address buffer 106].
The adder 404 performs an addition process of the input. The operation other than that of the adder 404 is the same as the operation of the first line described above.

Thereafter, the above is alternately repeated until the operation for M lines (where M is an even number) is completed.

When the operation for the M lines described above is completed, the mosaic formation in the line direction is executed by exchanging the operations of the one-system memory 301 and the two-system memory 302.

By the above operation, a mosaic image of N × M blocks can be formed, and a mosaic shape as shown in FIG. 3 is formed.

Further, by setting the processing timing of the averaging register 405 to be different depending on when the one-system memory 301 and the two-system memory 302 are read, a mosaic shape as shown in FIG. 4 can be easily formed.

Next, an embodiment in which the above-described invention is further improved and its function is extended will be described. That is, as shown in FIG. 9, a mosaic image is formed in a rectangular area (mosaic area) set in a document image, and an image is to be recorded in a normal manner in the remaining area (normal area). It is. In the embodiment of the present invention, the circuit of FIG. 10 is added to the circuit configuration of FIGS. 5 and 6, and the circuits of FIGS. 5 and 6 are controlled by the area signal output from the circuit of FIG. Is done.

Here, FIGS. 11A and 11B are timing charts in the line direction, and FIG. 12 is a timing chart in the pixel clock direction, where the mosaic size is 4 × 4. The part corresponding to (1) in FIG. 11 is a normal toggle operation, and the part corresponding to (2) is an operation for forming a mosaic. At this time, the mosaic pattern shown in FIG. I do.

FIG. 10 is a circuit diagram illustrating one configuration of the area signal generation circuit. 603 to 606 are comparators. For convenience, if the inputs of the P terminal and the Q terminal are indicated by P and Q, respectively, if P> Q, L
, And if P <Q, H is output. 607 is NAND circuit, 608 is O
R circuit, 609 is an exclusive OR circuit, which outputs H only when one input is H and the other input is L, as is well known, and always outputs H for the other inputs. L is output. Reference numeral 203 denotes a sub-direction address counter that counts a line synchronization signal (LSYNC).

Here, it is assumed that an address of the image data in the main scanning direction (image clock direction) is x, and an address of the image data in the sub-scanning direction (line clock direction) is y. Correspondingly, the start address of the x-direction of the mosaic region shown in FIG. 9 x, the same end address displayed by x _2, also, y ₁ a start address in the y direction, by the same end address y ₂ It shall be displayed. The addresses in the main scanning direction and the sub-scanning direction that are currently being read are represented by x and y, respectively.
Therefore, x is the read address counter 20 of FIG. 10 or 11.
2 is the count value, and y is the count value of the sub-scanning direction address counter 203 described above.

As is clear from the configuration of FIG. 10, only when x ₁ <x <x ₂ , y ₁ <y <y ₂ (both x and y are in the mosaic area in FIG. 9), the NAND circuit 607 has the H level. Is output, and the output in other cases is L. In FIG. 10, MODE1 and MODE2 are 1-bit command signals for completing the mode signal (selected by the user of the apparatus). As is apparent from this circuit configuration, when MODE1 = L and MODE2 = L, image recording is performed in the manner shown in FIG.

When MODE1 = L and MODE2 = H, the mosaic area and the normal area in FIG. 9 are interchanged. Further, in the case of MODE1 = H, MODE2 = H _{is, x 1, x 2, y} 1, also to set the value of y ₂ in如向region,
The signal is always at L level, so that mosaic processing is not performed over the entire surface, and image recording is performed in a normal manner.

Finally, when MODE1 = H and MODE2 = L, the area signal becomes H regardless of the output value of the NAND circuit 607. That is, even if without setting the value of _{x 1, x 2, y 1} , y 2, mosaic processing is performed over the entire surface.

By simply loading such a simple circuit configuration, various varieties of image recording modes can be provided.

The operation of the digital image processing apparatus according to the present invention has been described based on the block diagram shown in FIG. 1 through the description of the above embodiments. It is not limited to the one immediately after reading, but may be one stored in a database or the like, or one transmitted from a remote place such as a facsimile machine. That is, the digital image processing apparatus of the present invention is widely applicable to electronic image recording means in general.

As described above, according to the present invention, the digital image processing apparatus
This means that the image data is sampled at regular image intervals in the main scanning direction and the sub-scanning direction, and the data of all the pixels in the unit block is replaced by the sampled image data.

For this reason, a large-scale frame memory becomes unnecessary, and real-time processing on image data becomes possible. In addition, since the write / read operation for the three systems is alternately switched, time margin is obtained for data processing.
Preparation for the repetitive recording operation of the next several lines can be easily completed in advance.

〔The invention's effect〕

As described above, according to the digital image processing apparatus according to the present invention, in the digital image processing apparatus that performs predetermined processing on digital image information to form a mosaic image, three line memories and the line memory Means for changing the switching timing of the toggle operation, and means for averaging the read data of the line memory, avoiding an increase in the size and cost of the device, averaging the representative points in each unit block, and Real-time processing can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital image processing apparatus according to the present invention, FIG. 2 is a block diagram showing an example of a configuration of an image processing unit in FIG. 1, and FIG. FIG. 4 is an explanatory diagram showing a pattern, FIG. 4 is an explanatory diagram showing a modification of the mosaic pattern in FIG. 3, and FIGS. 5 and 6 show other configurations of the image processing unit in FIG. FIG. 7 is a timing chart in the line direction of the circuit configuration shown in FIGS. 5 and 6, and FIG. 8 is a pixel clock direction in the circuit configuration shown in FIG. 5 and FIG. FIG. 9 is an explanatory diagram showing an example of a configuration for operating / releasing the mosaic function at a predetermined timing, FIG. 10 is an explanatory diagram showing a configuration of the area signal generating circuit, and FIG. FIG. 5 is a diagram in which the area signal generating circuit shown in FIG. 10 is added. FIG. 12 is a timing chart in the line direction of the circuit configuration shown in FIG. 6, and FIG. 12 is a timing chart in the pixel clock direction of the circuit configuration shown in FIGS. 5 and 6 to which the area signal generation circuit shown in FIG. 10 is added. It is a timing chart. DESCRIPTION OF SYMBOLS 1 ... Image reading unit 2 ... Image processing unit 3 ... Image recording unit 11n ... Output register 101 ... Write address register 102 ... Write address buffer 103 for one system 103 ... Write for two systems Address buffer 104: Write address buffer for three systems 105: Averaged read address buffer for one system 106: Averaged read address buffer for two systems 107: Averaged read address buffer for three systems 108: One system Read address buffer 109: Two-system read address buffer 110, 111, 112, 113 Output register 201: Write address counter 202: Read address counter 203: Sub-scanning direction address counter 301: One-system memory 302: Two systems Memory 303: Three-system memory 401: Division register 402, 403, 404: Adder 405: Averaging register 500, 501 ……selector

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/38-1/393 H04N 1/21 G06T 1/00

Claims (2)

(57) [Claims] 1. A digital image processing apparatus for forming a mosaic image by performing predetermined processing on digital image information, comprising: three line memories; and means for changing a switching timing of a toggle operation of the line memories. And averaging by sampling the read data of the line memory at predetermined intervals in the main scanning direction and the sub-scanning direction to form a unit block, and replacing the read data included in the unit block with the sampling data. A digital image processing apparatus comprising: 2. A digital image processing apparatus for forming a mosaic image by performing predetermined processing on digital image information, comprising: three line memories; and means for changing a switching timing of a toggle operation of the line memories. And averaging by sampling the read data of the line memory at predetermined intervals in the main scanning direction and the sub-scanning direction to form a unit block, and replacing the read data included in the unit block with the sampling data. A digital image processing apparatus, comprising: