JP3086726B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit of a semiconductor integrated circuit, and more particularly to an output circuit constituted by bipolar transistors for driving an inductive load.

[0002]

2. Description of the Related Art Conventionally, an output circuit of a semiconductor integrated circuit for driving an inductive load, such as a coil, is configured as shown in FIG. In the figure, the collector of an NPN output transistor 10 is connected to a power supply terminal 11. The power supply terminal 11 is connected to the positive polarity side of the power supply Vcc.
The negative side of the power supply Vcc is connected to the ground potential. The emitter of the transistor 10 is connected to the output terminal 12. Further, the collector of the NPN transistor 13 is connected to the output terminal 12. The emitter of the transistor 13 is connected to the ground potential. A drive signal is supplied from a driver circuit 16 to the bases of the transistors 10 and 13 respectively. One end of a coil 14 such as a motor, which is an inductive load, is connected to the output terminal 12. The other end of the coil 14 is connected to the ground potential. The output terminal 12 is connected to the cathode of a diode 15 for output clamping. The anode of this diode 15 is connected to the ground potential.

In the above conventional output circuit, when the transistor 10 is on and the transistor 13 is off, a load current flows through the load 14 in the direction of IF in the figure. Next, when the transistor 10 changes from on to off, the inductive load 14
The back electromotive force is generated so that the current that has been flowing until now continues to flow further. When this back electromotive voltage occurs in the load 14, a current flows through the diode 15 in the direction of IR in the figure. When this current flows, a potential difference is generated between both ends of the diode 15, and the value becomes about 0.7 V when the diode 15 is formed on a silicon substrate. Therefore,
Immediately after the back electromotive voltage generated in the load 14, the voltage drops to about -0.7 V at the output terminal 12 side. As a result, the output transistor 10 is prevented from being destroyed by the back electromotive voltage.

[0004]

In the above-mentioned conventional circuit, the transistors 10, 13 and the diode 15 are usually formed on the same silicon substrate together with the driver circuit 16. Such a problem arises.

FIG. 5 is a sectional view showing the element structure of each element including the NPN transistor 13. As shown in FIG. In the figure, 20
The P ^- , Respectively, are the N-type collector regions of the transistors, and 22 is the P ⁺ of the transistors. Type base region, 23 is the transistor N ⁺ Mold emitter area, 24
Is the N ⁺ of the transistor Collector contact region, and the collector region of each transistor is P ⁺ Mold separation area 2
Each element is separated from each other at 5, 25,.

The above P ⁺ Since the mold separation region 25 is connected to the ground potential, the potential of each N-type
As long as the potential of the negative polarity does not exceed the forward voltage between the N junctions, the pair of N-type collector regions 21 and P ⁺ The parasitic NPN transistor constituted by the type separation region 25 is not turned on, and no parasitic interference occurs between the transistors.

When a back electromotive voltage is generated in the inductive load 14 as described above, the potential of the output terminal 12 is reduced by the diode 15 to about-.
It is clamped to about 0.7V. Since the output terminal 12 is connected to the N-type collector region 21 of the transistor 13, the potential of the collector region 21 also drops to about -0.7V. Then, from the ground potential, P ⁺ Mold separation area 25
A forward current flows through the junction between the transistor and the N-type collector region 21. As a result, the parasitic NPN transistor is turned on and the current I in the drawing flows. The generation of this current adversely affects other elements formed on the same substrate, and causes a problem that the entire circuit causes abnormal operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to prevent the output transistor from being destroyed when a back electromotive force is generated in an inductive load. An object of the present invention is to provide an output circuit capable of preventing occurrence of circuit malfunction based on the back electromotive voltage.

[0009]

An output circuit according to the present invention comprises:
A collector connected to a positive power supply, an emitter connected to the output terminal, a first transistor for output supplied with a drive signal to the base, and one end connected to the output terminal;
An inductive load having the other end coupled to the ground potential; a second transistor having a collector and an emitter inserted between the output terminal and the ground potential; Bias means for supplying a constant DC bias voltage that is higher than the forward voltage between the base and the emitter of the second transistor.

[0010]

When the first transistor is turned off while the load current is flowing through the inductive load when the first transistor is on, a back electromotive voltage is generated across the inductive load. When this back electromotive voltage is generated, the second transistor is turned on, and the potential of the output terminal side of the inductive load becomes
The value is lower than the constant DC bias voltage supplied to the base of the second transistor by the forward voltage (V _BE ) between the base and the emitter of the second transistor.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the output circuit according to the present invention. In the figure, the collector of an NPN output transistor 10 is connected to a power supply terminal 11.
The power supply terminal 11 is connected to the positive polarity side of the power supply Vcc. The negative side of the power supply Vcc is connected to the ground potential. The emitter of the transistor 10 is connected to the output terminal 12. Further, the collector of the NPN output transistor 13 is connected to the output terminal 12.
The emitter of this transistor 13 is connected to the ground potential. A drive signal is supplied from a driver circuit 16 to the bases of the transistors 10 and 13 respectively. The output terminal 12 has an inductive load such as a coil of a motor or the like.
One end of 14 is connected. The other end of the coil 14 is connected to the ground potential.

The output terminal 12 has an output clamp NP.
The emitter of the N transistor 17 is connected. The collector of the transistor 17 is connected to the ground potential, and its base is supplied with a constant DC bias voltage Vbb generated by the DC bias voltage source 18. here,
The value of the DC bias voltage Vbb is set higher than the ground potential of 0 V and lower than the base-emitter forward voltage (V _BE ) of the transistor 17. For example, when the value of V _BE is 0.7 V of a silicon transistor, the value of Vbb is set to about 0.3 V.

Next, the operation of the circuit having the above configuration will be described. Now, when the transistor 10 is turned on and the transistor 13 is turned off based on the drive signal output from the driver circuit 16, a load current flows through the coil 14 in the direction of IF in the figure. Next, when the transistor 10 changes from on to off, a back electromotive voltage is generated across the coil 14 such that the output terminal 12 has a low potential. That is, the output terminal
The potential at 12 becomes negative. When such a back electromotive voltage is generated in the coil 14, the output clamping transistor 17
Then, the transistor 17 is turned on. Then, when the current IR shown in the drawing flows through the coil 14 via the transistor 17, the back electromotive force is absorbed. When the current IR flows, the potential at the output terminal 12 is V
_The value is reduced by _BE . For example, if V _BE is 0.7 V, the potential of the output terminal 12 becomes −0.4 V. In other words, the collector potential of the transistor 13 does not drop below -0.4V. Therefore, the current I in the parasitic NPN transistor as described with reference to FIG. 5 does not flow.

Therefore, in the circuit of this embodiment, it is possible to prevent the output transistor 10 from being destroyed when a back electromotive voltage is generated in the coil 14, which is an inductive load, and to cause a circuit malfunction caused by turning on the parasitic transistor. Can be prevented.

FIG. 2 is a circuit diagram of a second embodiment of this output circuit. This embodiment differs from the embodiment shown in FIG. 1 in that the collector of the output clamping transistor 17 is connected to the output terminal 12 and the emitter is connected to the ground potential. This is the same as the circuit of the embodiment.

In the circuit of this embodiment, when a back electromotive voltage is generated in the coil 14 and the output terminal 12 has a negative potential, the transistor 17 performs an inverse operation and a current IR flows between the emitter and the collector. The potential of terminal 12 is Vbb-V _BE
Is set to

FIG. 3 is a circuit diagram of a third embodiment of the output circuit according to the present invention. In this embodiment, the present invention is applied to a so-called H-bridge type output circuit. In the figure, the collector of an NPN output transistor 30 is connected to a power supply terminal 31. The power supply terminal 31 has a power supply V
The positive side of cc is connected. Also, this power supply Vc
The negative side of c is connected to the ground potential. The emitter of the transistor 30 is connected to a first output terminal 32. The collector of the NPN output transistor 33 is connected to the first output terminal 32. The emitter of the transistor 33 is connected to the control terminal. The collector of the NPN output transistor 35 is connected to the power supply terminal 31. The emitter of the transistor 35 is connected to the second output terminal 36. Further NP
The collector of the N-type output transistor 37 is connected to the second output terminal 36, and the emitter is connected to the control terminal 34. A motor coil 38 is connected between the first output terminal 32 and the second output terminal 36 as an inductive load. The cathode and anode of the diodes 40 and 41 are connected between the collector and the emitter of the transistor 30 and between the collector and the emitter of the transistor 35, respectively.

The first output terminal 32 is connected to the emitter of an NPN transistor 42 for output clamping. The collector of this transistor 42 is connected to the ground potential. Similarly, to the second output terminal 36, the emitter of an NPN transistor 43 for output clamping is connected. The collector of this transistor 43 is connected to the ground potential. The bases of the transistors 42 and 43 are connected in common, and a common connection point of the bases is connected to a fixed DC bias voltage V
bb is supplied. The value of the DC bias voltage Vbb is higher than the ground potential of 0 V, as in the first and second embodiments.
The values are set to lower values than the respective forward voltages (V _BE ) between the base and the emitter. For example, when the value of V _BE is 0.7 V of a silicon transistor, the value of Vbb is set to about 0.3 V.

A current detection resistor 39 is connected between the control terminal 34 and the ground potential. The above control terminal
A control circuit 45 is connected to 34. The control circuit 45 detects a voltage drop at the resistor 39, and its detection output is supplied to a driver circuit 46. The driver circuit 46 outputs a base drive signal for controlling the conduction of the transistors 30, 33, 35, and 37.

Next, the coil 38
The operation when a load current flows through the device will be described. This coil 38
The direction of the load current flowing through the driver circuit is determined by the drive signals of the transistors 30, 33, 35, and 37 output from the driver circuit 46.
Now, when the transistors 30 and 37 are turned on and the transistors 33 and 35 are turned off based on the driving signal output from the driver circuit 46, the load current flows through the coil 38 in the direction from the output terminal 32 to the output terminal 36. Flows. The transistors 33 and 35 are turned on based on the drive signal, and the transistors 33 and 35 are turned on.
When terminals 30 and 37 are off, this coil 38 has an output terminal
Load current flows from 36 to the output terminal 32.

The control of the amount of load current flowing through the coil 38 is performed based on the voltage drop by the resistor 39 detected by the control circuit 45. The control circuit 45 causes the transistor 30 or 35 to perform a chopping operation of repeatedly turning on and off by the driver circuit 46 so that the detected voltage drop becomes a desired value. When the direction of the load current is from the output terminal 32 to the output terminal 36, the transistor 30 performs the chopping operation. When the direction of the load current is from the output terminal 36 to the output terminal 32, the transistor 35 performs the chopping operation.

When the transistor 30 is turned off by chopping operation, a back electromotive voltage is generated across the coil 38 such that the output terminal 32 has a low potential. When the potential of the terminal 32 becomes lower than the potential Vbb of the base of the transistor 42 by V _BE , the base current of the transistor 42 flows. Thereafter, the transistor 42 is turned on, and a current due to the back electromotive voltage flows from the transistor 42 to the ground potential via the coil 38 and the turned on transistor 37. For the counter electromotive voltage is absorbed by the current flow, the potential of the terminal 32 is never lower than Vbb-V _BE. For example, V _{BE at} this time is 0.7V
Then, the potential of the terminal 32 does not decrease to -0.4 V or less. That is, the potential of the collector of the transistor 33 does not drop below -0.4V. Therefore, the current I in the parasitic NPN transistor as described with reference to FIG. 5 does not flow.

The back electromotive voltage generated between both ends of the coil 38 when the transistor 35 is turned from on to off by the chopping operation makes the output terminal 36 side a low voltage. When the potential of the terminal 36 decreases, the transistor 43 is turned on. Therefore, the current due to the back electromotive voltage flows from the transistor 43 to the ground potential via the coil 38 and the turned-on transistor 33, and the potential of the output terminal 36 is set to a value lower than the base potential Vbb of the transistor 43 by V _BE. Become.

Although the collectors of the output clamping transistors 42 and 43 are connected to the ground potential and the emitters are connected to the output terminal in the third embodiment, the connection between the emitter and the collector may be reversed. In this case, the back electromotive voltage generated in the coil 38 is absorbed by the inverse operation of the transistor 42 or 43 as in the second embodiment, and the potential of the output terminal on the low potential side becomes Vbb-V _BE .

[0026]

As described above, according to the present invention, it is possible to prevent the output transistor from being destroyed when a back electromotive voltage is generated in the inductive load, and to prevent a circuit malfunction based on the back electromotive voltage. An output circuit capable of preventing occurrence can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of an output circuit according to the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the output circuit according to the present invention.

FIG. 3 is a circuit diagram of a third embodiment of the output circuit according to the present invention.

FIG. 4 is a circuit diagram of a conventional output circuit.

FIG. 5 is a cross-sectional view of a semiconductor substrate on which a transistor element is formed.

[Explanation of symbols]

10, 13, 30, 33, 35, 37 ... output transistors, 12, 32,
36: output terminal, 14, 38: coil, 15: diode for output clamp, 17, 42, 43: transistor for output clamp, 18: DC bias voltage source, 21: collector region, 22: base region, 23: emitter region , 24 ... collector contact area, 25 ... isolation area.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-178424 (JP, A) JP-A-1-236730 (JP, A) JP-A-61-5819 (JP, A) JP-A-60-1985 185427 (JP, A) JP-A-58-84536 (JP, A) JP-A-4-239813 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17 / 00-17 / 70

Claims (6)

(57) [Claims] A first transistor having a collector connected to a positive power supply, an emitter connected to an output terminal, a base to which a drive signal is supplied, and one end connected to the output terminal; An inductive load having an end coupled to a ground potential; a second transistor having a collector-emitter inserted between the output terminal and the ground potential; and a base higher than the ground potential at a base of the second transistor. An output circuit comprising: bias means for supplying a constant DC bias voltage lower than a forward voltage between the base and the emitter of the second transistor. 2. The output circuit according to claim 1, wherein an emitter of the second transistor is connected to the output terminal, and a collector is connected to a ground potential. 3. An output second terminal having a collector connected to the output terminal, an emitter connected to ground potential, and a base supplied with a drive signal different from a drive signal supplied to the base of the first transistor. 3. The output circuit according to claim 1, further comprising three transistors. 4. A first transistor for output having a collector connected to a positive power supply, an emitter connected to a first output terminal, a base supplied with a first drive signal, and a collector connected to a second transistor. A second transistor for output, the emitter of which is coupled to the ground potential, the base of which is supplied with a second drive signal, the collector of which is connected to a positive power supply, and the emitter of which is connected to the second power supply. A third transistor for output, the base of which is supplied with a third drive signal; a collector connected to the first output terminal; an emitter connected to the ground potential; An output fourth transistor to which a drive signal is supplied, an inductive load inserted between the first and second output terminals, and a collector between the first output terminal and a ground potential. -Insert between emitters A fifth transistor, a sixth transistor having a collector and an emitter inserted between the second output terminal and the ground potential, and a base connected to the base of each of the fifth and sixth transistors. And a bias means for supplying a constant DC bias voltage that is higher than the forward voltage between the base and emitter of each of the fifth and sixth transistors. 5. The emitter of the fifth transistor is connected to the first output terminal, the emitter of the sixth transistor is connected to the second output terminal, and the collectors of both transistors are both connected to the ground potential. 5. The output circuit according to claim 4, wherein the output circuit is connected to the output circuit. 6. The output circuit according to claim 4, wherein a current detecting resistor is inserted between the emitters of said second and fourth transistors and a ground potential.