JP3065859B2 - Delay detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay detection circuit used in a demodulation circuit of a digital communication device, and more particularly to a delay detection circuit suitable for implementing a .pi. / 4 shift QPSK demodulation circuit used in a digital cordless telephone as an LSI. Things.

[0002]

2. Description of the Related Art Conventionally , for example , a π / 4 shift QPSK differential detection circuit for a digital cordless telephone has been disclosed in 19th place.
Proceedings of the 1992 IEICE Spring Conference p2-34
4, "π / 4 shift QPS for digital cordless telephones
K delay detection circuit ". In the disclosed delay detection circuit, an exclusive OR circuit (hereinafter referred to as EX-O) is used.
R circuit), a D-type flip-flop circuit, an analog reduction furnace, an analog / digital converter, and a logic circuit to form an instantaneous phase circuit. EX-O
Since the phase detection characteristics of the combination of the R circuit and the analog reduction reactor are such that 0 to π rises to the right and π to 2π falls to the right, the polarity is switched by the output of the D-type flip-flop circuit to detect the linear phase. I can do it.

[0003]

SUMMARY OF THE INVENTION However, the conventional
The delay detection circuit, an analog reduction furnace filter and an analog / digital converter of an LSI is extremely difficult, small
It has been desired to realize a delay detection circuit having a small circuit scale and a circuit configuration that can be easily formed into an LSI.

[0004]

Means for Solving the Problems] To solve the above problems
In the first aspect of the present invention, the delay detection circuit
And inputs a first modulated wave signal and a reference clock signal.
And the first modulated wave signal is generated based on the reference clock signal.
A first circuit for converting a frequency and outputting a second modulated wave signal
A wave number conversion circuit, the second modulated wave signal and the reference
Input a clock signal and, based on the reference clock signal,
The generated phase shifts by π / 2 (= 90 °).
Based on the first and second clock signals of one frequency,
The frequency of the modulated wave signal 2 to baseband (baseband)
A second output of the dropped first and second modulated wave information signals
Frequency conversion circuit, and the first and second modulated wave information signals
, And average the information of the modulated wave information signal.
First and second moving average fills respectively outputting values
Circuit and the first and second moving average filter circuits
And outputs the second modulated wave from the output signal.
A first method for outputting modulation information of a signal in the form of a digital signal
A logic circuit, and a digital output from the first logic circuit.
Digital signal and the reference clock signal, and
At a predetermined time based on the frequency of the reference clock signal.
From the delayed signal and the digital signal
Calculating a phase difference of the second modulated wave signal;
Means. Here, the second frequency conversion
Circuit, the first and second moving average filter circuits, and
An instantaneous phase detection circuit is constituted by the first logic circuit.
I have. In addition, the first and second moving average filter circuits
Each of the roads is composed of a plurality of stages, and the first and the second
Each of the harmonic information signals is synchronized with the reference clock signal.
And input the data of the first stage and the data of the final stage.
A shift register to output, and one stage of the shift register
If the data of the first row and the data of the last row have different values,
Outputs up-count signal or down-count signal
Then, the data of the first stage matches the data of the last stage.
When the up-count signal or down-count signal
A second logic circuit that does not output any of the signals
Based on the up-count signal or down-count signal.
Performs a counting operation and outputs the first and second modulated wave information signals.
Up / down cow that outputs the average value of the information
And In the second invention, a differential detection circuit
In the delay detection circuit according to the first invention, the phase difference
Inputting the output signal of the calculation means and the reference clock signal
And determines whether the output signal is based on the frequency of the reference clock signal.
A clock recovery circuit for recovering a data clock signal from the
The output signal of the phase difference calculation means and the data clock
Input clock signal and output based on the data clock signal.
A data reproducing circuit for reproducing data from the input signal.
ing. In a third aspect, the delay of the first or second aspect is provided.
In the detection circuit, the first frequency conversion circuit is
A reference clock signal is input, and the reference clock signal is
a 1 / n frequency dividing circuit for dividing the frequency by n (where n is a positive integer);
An output signal of the 1 / n frequency dividing circuit and the first modulated wave
A signal, and exclusion of the output signal and the first modulated wave signal
A first modulating means for obtaining a logical sum and outputting the second modulated wave signal
EX-OR circuit. In the fourth invention,
In the delay detection circuit according to the first or second invention,
2 the frequency conversion circuit inputs the reference clock signal.
And the reference clock signal is 1 / m (where m is a positive integer).
Number) 1 / m for dividing and outputting the first clock signal
A frequency dividing circuit, the first clock signal and the second
Receiving a modulated wave signal, the first clock signal and the second
Calculating an exclusive OR of the modulated wave signals to obtain the first modulated wave information;
A second EX-OR circuit for outputting a notification signal;
A clock signal is input, and the first clock signal is set to π / 2
The second clock signal is output with the phase shifted by just
a π / 2 phase shift circuit, the second clock signal and the
A second modulated wave signal is input, and the second clock signal and the second
An exclusive OR of the second modulated wave signal is obtained to obtain the second modulated wave signal.
And a third EX-OR circuit for outputting a harmonic information signal.
are doing.

[0005]

According to the present invention, the first modulated wave signal is supplied to the first circuit.
Is input to the wave number conversion circuit, said first frequency conversion circuit
Then, the first modulated wave signal is converted into a frequency band preferable for the instantaneous phase detection circuit to operate , and the second modulated wave signal is
Output. A second frequency conversion circuit in the instantaneous phase detection circuit converts the second modulated wave signal into a signal having information on a modulated wave phase component by two clock signals shifted by 90 °. First and second moving average filter circuit outputs the average value and the deviation direction of the information of the phase at a predetermined time phase component of the modulated wave digitally. And the first
The logic circuit, digital information of phase components of the modulated wave in which the first and second moving average filter circuit is generated if
And the phase difference of the modulated wave is calculated by the phase difference calculation means.
Is calculated. Then, if necessary, the clock recovery circuit
The data clock signal is reproduced by the
The data is regenerated.

[0006]

EXAMPLES First Embodiment FIG 1 is Ru circuit diagram der delay detection circuit showing a first embodiment of the present invention. This delay detection circuit receives a first modulated wave signal having a frequency f1 (for example , 10.8 MHz) .
It has a modulated wave input terminal 101 and an oscillator 102
You. The oscillator 102 has a frequency f2 (eg , N) that is sufficiently higher than the frequency f1 and is N times the data clock (eg , 384 kHz) (where N is a positive integer , eg, 50) .
Generating a reference clock signal having a 19.2 MHz)
Things. The output terminal of the oscillator 102 is divided by 1 / n
A road 1 / n frequency divider 103 (where n is a positive integer, examples
For example, via 2), a two-input first EX-OR circuit 10
4 is connected to one input terminal. Where 1 / n
By the frequency divider 103 and the first EX-OR circuit 104
Thus, a first frequency conversion circuit is configured. The first E
The other input terminal of the X-OR circuit 104 is the input terminal 10
1 connected . An output terminal of the first EX-OR circuit 104 is connected to an input side of the instantaneous phase detection circuit 105.
ing. The instantaneous phase detection circuit 105 is composed of two-input second and third EX-OR circuits 106 and 107 and a 1 / m frequency dividing circuit.
A certain 1 / m frequency divider 108 (where m is a positive integer , for example, 16), a π / 2 phase shifter 109 which is a π / 2 phase shift circuit, first and second moving average filter circuits 110 and 111 And a first logic circuit 112 . Where
2. Third EX-OR circuit 106, 107, 1 / m frequency division
, And the π / 2 phase shifter 109 causes the second cycle
A wave number conversion circuit is configured. One input terminal of each of the two-input second and third EX-OR circuits 106 and 107 is connected to an output terminal of the first EX-OR circuit 104.
Is connected. The input terminal of the 1 / m frequency divider 108 is
It is connected to the output terminal of the oscillator 102 . Second EX
-The other input terminal of the OR circuit 106 is a 1 / m frequency divider 1
08 is connected to the output terminal. 1 / m frequency divider 108
Is also connected to the input terminal of the π / 2 phase shifter 109. The other input of the third EX-OR circuit 107
Terminal is connected to the output terminal of the [pi / 2 phase shifter 109.

Output terminal of second EX-OR circuit 106
Has a control terminal connected to the input terminal of the first moving average filter circuit 110 connected to the output terminal of the oscillator 102.
Is, the output terminal of the third EX-OR circuit 107 is connected to an input terminal of the second moving average filter circuit 110 a control terminal connected to an output terminal of the oscillator 102. Here, the first and second moving average filter circuits 110,
Circuitry 111 are the same, be shown <br/> 2 a circuit diagram thereof. For example, as shown in FIG. 2, the moving average filter circuit 110 used in the first embodiment has ^2P stages (here, P
The shift register 405 a positive integer), it is composed of the second logic circuit 406 and up-down counter 407
ing. Input terminal 401 of moving average filter circuit 110
Is connected to the input terminal of the first stage A of the shift register 405
Have been. Clock input terminal of shift register 405
Is a control input terminal 404 of the moving average filter circuit 110.
Is connected to the oscillator 102 via the . Output terminal of first stage A of shift register 405 and output of second ^P stage B
The terminal is connected to the input terminal of the second logic circuit 406.
I have. The clock input terminal of the second logic circuit 406 is connected to the control input terminal 404 of the moving average filter circuit 110
Have been. The output terminal of the second logic circuit 406 is connected to an input terminal of the up-down counter 407, the output terminal of the up-down counter 407 is connected to the output terminal 408 of the moving average filter circuit 110.

Returning to FIG. 1, the instantaneous phase detection circuit 10
The explanation of 5 is continued. The output terminals of the first and second moving average filter circuits 110 and 111 are connected to the first logic circuit 11.
2 input terminals. Then, the output of the first logic circuit 112 becomes the output of the instantaneous phase detection circuit 105. Out of the instantaneous phase detection circuit 105
The input terminal is connected to the input terminal of the delay circuit 113 and the input terminal of the phase difference calculation circuit 114 . Where late
The delay circuit 113 and the phase difference calculation circuit 114
Phase difference calculating means is configured. The clock input terminal of the delay circuit 113 is connected to the oscillator 102. The output terminal of the phase difference calculation circuit 114 is connected to the input terminal of the clock recovery circuit 116 and also to the input terminal of the data recovery circuit 115 . The clock input terminal of the clock recovery circuit 116 is connected to the oscillator 102 , and the clock input terminal of the data recovery circuit 115 is connected to the output terminal of the clock recovery circuit 116 . Output terminal of data recovery circuit 115 and clock recovery circuit 1
The 16 output terminals are connected to the reproduced data output terminal 117 and the reproduced clock output terminal 118 of the delay detection circuit of the first embodiment , respectively .

Next , the operation of the delay detection circuit according to the first embodiment will be described. Since the 1 / n frequency divider 103 divides the frequency of the clock signal by n, the frequency f2 / n is output from its output terminal.
Is output. The first EX-OR circuit 104 has a clock signal having a frequency f2 / n and a frequency f2 / n.
Since one first modulated wave signal is input, a second modulated wave signal having a frequency f3 = f1-f2 / n is output from its output terminal . As described above, the 1 / n frequency divider 103 and the first EX-OR circuit 104 work as a mixer for converting the frequency of the modulated wave signal. Since the 1 / m frequency divider 108 divides the clock signal by m, a first clock signal having a frequency f2 / m is output from its output terminal . π
From the / 2 phase shifter 109, the clock signal having the frequency f2 / m is shifted by 90 ° (π / 2) to the second phase .
Of the clock signal is output. Therefore, the second EX-O
The R circuit 106 is the input clock signal and a modulated wave signal and the frequency f2 / m is the frequency f3 = f1-f2 / n is the third EX-OR circuit 107, the frequency f3
= F1-f2 / n a is be modulated wave signal and the frequency f2 / m 90 ° and a clock signal whose phase is shifted by the input. These second and third EX-OR circuits 106, 1
07 (ie, the first and second modulation signals ).
The frequency of the harmonic information signal is f4 = f1-f2 / n-f
2 / m.

Here, the frequencies f1 and f2 and the frequency division numbers n and m
Has the following relationship: f2 / m = f1-f2 / n ··· (1) (1) equation becomes f4 = 0 is substituted into f4, the signal output from the second and third EX-OR circuit 106 and 107, the modulation The baseband modulated wave information signal is obtained by lowering the modulated wave frequency of the wave signal to the baseband (baseband). The baseband modulation wave information signal is applied to the input terminal of the first stage A of the shift register 405 through an input terminal 401 of the moving average filter circuit 110, 111 shown in FIG. In the shift register 405, sampling the baseband modulated wave information signal as the data according to the sampling clock signal input to the clock input terminal, it reads the first stage A. Then the shift register 405, a sampling clock signal shifts the data read every advancing cycle to the right, the first stage A
Data read in is shifted to the 2 ^P stage B by 2 ^P over one sampling clock. The second logic circuit 406 operates as shown in Table 1. That is ,
The second logic circuit 406 synchronizes the up-count signal and the down-count signal with any of the data read into the first stage A of the shift register 405 and the data read into the second ^P- stage B in synchronization with the sampling clock. An operation of not outputting a signal is performed. The up / down counter 407 counts up by one when the signal from the second logic circuit 406 is an up count signal, and counts down by one when the signal is a down count signal.

[0011]

[Table 1] The output signal of the up / down counter 407, that is, the output signal of the moving average filter circuits 110 and 111, is generated from a signal obtained by taking an exclusive OR of the clock signal and the modulated wave signal whose phases are shifted from each other by 90 °. For,
These are digitally representing information on the average value of the phase difference component of the modulated wave over a certain period of time and the direction of the shift of the phase difference. In the first logic circuit 112 combines the average value and the deviation direction of the digital information of the phase difference at a certain time of the phase difference component is output as a modulation digital information of one of the modulated wave. Output of the first logic circuit 112
The signal is supplied to the second delay circuit 113 and the phase difference calculation circuit 11
4 is input. In the second delay circuit 113, the oscillator 1
The output signal of the first logic circuit 112 is delayed by the symbol rate (in this embodiment, 倍 times the data rate) based on the reference clock signal generated in step S 02 and input to the phase difference calculation circuit 114. . Phase difference calculation circuit 114 odor
Te, delay detection row by taking the difference between the output signal and the output signal of the second delay circuit 113 of the first logic circuit 112
Will be The output signal of the phase difference calculation circuit 114, which is the differential detection output signal , is input to the data recovery circuit 115 and the clock recovery circuit 116. Clock recovery circuit 1
At 16, the data clock signal is reproduced from the differential detection output signal based on the reference clock signal generated by the oscillator 102 . The recovered data clock signal is also input to the data reproduction circuit 115 is outputted from the reproduction clock output terminal 118. The data reproducing circuit 115 reproduces data based on the delayed detection output and the reproduced clock output signal generated by the clock reproducing circuit 116,
The data is output from the reproduction data output terminal 117.

As described above in detail, according to the delay detection circuit of the first embodiment , the 1 / n frequency divider 103 and E
Dropped modulation frequency input with a first frequency converter circuit comprising the X-OR circuit 104 to a digital instantaneous phase detectable frequency band, and this first frequency converting circuit and the instantaneous phase detecting circuit 105 Is the same oscillator 102
By using a reference clock signal of al, it is possible to configure the delay detection Namikai path even if a relatively high modulation wave input frequency without using an analog circuit. Furthermore, which it has conventionally been required, since it is possible to configure only the delay detection Namikai path digital circuit all without using an analog reduction furnace filter and an analog / digital converter and the like, small circuit scale,
It is very suitable for LSI. In the first embodiment , the delay circuit 113 and the clock recovery circuit 116 are operated by the reference clock signal of the frequency f2 generated by the oscillator 102 . As an example , consider a case where the frequency f1 of the modulated wave signal input at a data clock frequency (data speed) of 384 kHz is 10.8 MHz. Since the frequency f2 of the signal input to the instantaneous phase detection circuit 105 is preferably about 1.2 MHz, considering these, f2 = N (= 50) × 384 kHz = 19.2 MHz,
When m = 16 and n = 2, the expression (1), that is, f2 / m = f1-
f2 / n can be satisfied. However, when the input modulated wave frequency f1 = 10.7 MHz, m = 1
6, in order to satisfy the expression (1) with n = 2, the frequency f2 of the signal input to the instantaneous phase detection circuit 105 is equal to 19.022.
2 MHz, which is not an integral multiple of the data rate (384 kHz). When an integral multiple of the data rate f2 is not not use the reference clock signal for the delay in the delay circuit 113 is the symbol rate component (half the data rate), even clock extraction in the clock recovery circuit 116 The processing after the instantaneous phase detection circuit 105 becomes difficult.

[0013] Here, a delay detection Namikai path of the second embodiment can solve the problem in FIG. Second Embodiment FIG. 3 is a circuit diagram of a delay detection circuit according to a second embodiment of the present invention.
It is a road map. In FIG. 3, the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. 10.7MH
Considering a modulated wave input signal of z , as described above, the frequency f2 'of the first clock signal output from the first oscillator 202 corresponding to the oscillator 102 of the first embodiment is 19.0.
222 MHz, data clock (384 kHz)
Is not an integral multiple of. Therefore, in the second embodiment, a second oscillator 219 is provided, which is, for example, f5 = 19.2 MHz.
It is assumed that a second clock signal having a frequency of z (N = 50) is output. The output terminal of the first oscillator 202 is 1 / n
Only the divider 103 and the 1 / m divider 108 are connected.
On the other hand, the output terminal of the second oscillator 219 is connected to the second delay circuit 113 and the clock recovery circuit 116. Further, in the delay detection circuit of the second embodiment , a sampling circuit 220 is provided between the output terminal of the instantaneous phase detection circuit 105 and the input terminals of the second delay circuit 113 and the phase difference calculation circuit 114. . This sampling circuit 2
20 is controlled by an output signal of a 1 / k frequency dividing circuit 221 that divides the second clock signal output by the second oscillator 219 by k.

[0014] Next, the operation of the delay detection Namikai path of the second embodiment. Until the output of the instantaneous phase detecting circuit 105 will be omitted because it is similar to the operation of the delay detection Namikai path of the first embodiment will be described focusing on the operation of the sampling circuit 220. The output signal of the instantaneous phase detecting circuit 105, which had been generated on the basis of the first clock signal of a frequency f2 ', subsequent processing is operated based on the second clock signal of the frequency f3, asynchronous Will be. Therefore , the second clock signal is divided by a 1 / k frequency dividing circuit 22.
Sampling circuit 220 by the signal divided by k by 1
To work. The output signal of the instantaneous phase detection circuit 105 is sampled by the sampling circuit 220 at a timing asynchronous with the first clock signal and synchronized with the second clock signal. Subsequent operations are the same as in the first embodiment, and a description thereof will be omitted.
Here, the output signal of the instantaneous phase detection circuit 105 is
The high frequency components have been removed by the equalizing filter circuits 110 and 111 , and the data existence frequency band is very small with respect to the output sampling rate. Therefore, even if sampling is performed asynchronously by the sampling circuit 220, there is almost no data quality deterioration due to the aliasing phenomenon.

[0015] Thus, according to the delay detection Namikai path of the second embodiment, in addition to the effects of the first embodiment, the frequency of the modulated wave signal is not an integral multiple of the data rate input It is also possible to easily reproduce the data clock signal and the data output. The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, although the moving average filter circuits 110 and 111 shown in FIG. 2 are used in the above-described embodiment , another moving average filter circuit as shown in FIG. 4 can be used instead. FIG. 4 is a circuit diagram showing another moving average filter circuit . The moving average filter circuit shown in FIG.
0 is added. Logic circuit 409, all the values of the up-down counter 407 is a first signal when it is 1, all the values of the up-down counter 407 outputs a second signal when it is zero. In the logic circuit 410, when the first signal is output from the logic circuit 409, the logic circuit 4
06 up-count signal to the up-down counter 40
7, when the second signal is output from the logic circuit 409, the output of the down-count signal of the logic circuit 406 to the up-down counter 407 is stopped. This configuration prevents the moving average filter circuit from outputting an erroneous value due to noise or the like .

[0016]

As described in detail above, the first to fourth embodiments
Of According to the present invention, down modulation frequency input using the first frequency converting circuit to a digital instantaneous phase detectable frequency band, and a first frequency conversion circuit, the second
Frequency conversion circuit, first and second moving average filter circuits,
And an instantaneous phase detection circuit constituted by the first logic circuit
By using the same reference clock signal , the delay detection circuit can be configured without using an analog circuit even when the modulation wave input frequency is relatively high. Furthermore <br/>, which have conventionally been required, since it is possible to configure only the delay detection Namikai path digital circuit all without using an analog reduction furnace filter and an analog / digital converter and the like, circuit
It is small in scale and very suitable for LSI implementation.

[Brief description of the drawings]

Circuit diagram of a delay detection Namikai path of the first embodiment of the present invention; FIG

FIG. 2 is a circuit diagram of a moving average filter circuit according to the first embodiment of the present invention .

Circuit diagram of a delay detection Namikai path of the second embodiment of the present invention; FIG

FIG. 4 is a circuit diagram of another moving average filter circuit of the present invention .

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Modulation wave input terminal 102 Oscillator 103 1 / n frequency divider 104 1st EX-OR circuit 105 Instantaneous phase detection circuit 106 2nd EX-OR circuit 107 3rd EX-OR circuit 108 1 / m frequency divider 109 π / 2 phase shifter 112 First logic circuit 110, 111 Moving average filter circuit 113 Delay circuit 114 Phase difference calculation circuit 115 Data recovery circuit 116 Clock recovery circuit 117 Reproduction data output terminal 118 Reproduction clock output terminal

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Seizo Nakamura 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Kenzo Urabe 2-3-3 Toranomon, Minato-ku, Tokyo No. 13 Inside Kokusai Denki Co., Ltd. (56) References JP-A-4-315342 (JP, A) JP-A-55-27799 (JP, A) JP-A-59-102167 (JP, A) (58) Field (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (4)

(57) [Claims] 1. A first modulated wave signal and a reference clock signal.
And the first modulation based on the reference clock signal.
Converts the frequency of the wave signal and outputs a second modulated wave signal
A first frequency conversion circuit, the second modulated wave signal and the reference clock signal are input.
And π generated from each other based on the reference clock signal.
1st and 2nd clocks of the same frequency shifted in phase by
Based on the lock signal, base the frequency of the second modulated wave signal.
The first and second modulated wave information signals dropped to the band are output.
And a second frequency conversion circuit for inputting the first and second modulated wave information signals.
Output the average value of the information of the modulated wave information signal
First and second moving average filter circuits, and output signals of the first and second moving average filter circuits
And modulates the second modulated wave signal from the output signal.
First logic circuit for outputting information in the form of a digital signal
And the digital signal output from the first logic circuit and
And a reference clock signal.
Delayed for a predetermined time based on the frequency of the reference clock signal
The second modulation is performed from the delayed signal and the digital signal.
Phase difference calculating means for calculating the phase difference of the wave signal.
For example, each of the first and second moving average filter circuit
Is composed of a plurality of stages, and the first and second modulated wave information signals are
Input each in synchronization with the reference clock signal and
Shift data for outputting the eye data and the last stage data.
And register, the first stage of the data and the final stage of data of said shift register
If the value is different from the
Count signal is output, and the data of the first stage and the final stage are output.
When the data coincides with the up-count signal,
Or a signal that does not output any of the down-count signals.
2 logic circuit and the up-count signal or the down-count signal.
Performs a counting operation to obtain the first and second modulated wave information.
A outputs an average value of the information possessed by the signal respectively Ppudau
And a delay detection circuit,
Road. 2. The delay detection circuit according to claim 1, wherein the output signal of said phase difference calculation means and said reference clock are output.
Input a clock signal, based on the frequency of the reference clock signal.
A clock for reproducing a data clock signal from the output signal
A reproduction circuit, an output signal of the phase difference calculation means and the data clock;
Input clock signal and output based on the data clock signal.
A data reproducing circuit for reproducing data from the input signal.
A delay detection circuit characterized in that: 3. The first frequency conversion circuit receives the reference clock signal and receives the reference clock signal.
1 / n frequency dividing circuit for dividing 1 / n (where n is a positive integer)
And an output signal of the 1 / n frequency dividing circuit and the first modulated wave
A signal, and exclusion of the output signal and the first modulated wave signal
A first modulating means for obtaining a logical sum and outputting the second modulated wave signal
3. The exclusive OR circuit according to claim 1, further comprising:
Delay detection circuit. 4. The second frequency conversion circuit receives the reference clock signal and receives the reference clock signal.
1 / m (where m is a positive integer) is divided by the first clock.
A 1 / m frequency dividing circuit that outputs a clock signal, and the first clock signal and the second modulated wave signal.
And input the first clock signal and the second modulated wave signal.
Outputting the first modulated wave information signal by calculating exclusive OR
A second exclusive-OR circuit for inputting the first clock signal and the first clock signal.
The phase of the second clock signal shifted by π / 2
Π / 2 phase shift circuit for outputting the second clock signal and the second modulated wave signal
And outputs the second clock signal and the second modulated wave signal.
Outputting the second modulated wave information signal by obtaining exclusive OR
And a third exclusive OR circuit that performs
Is a delay detection circuit according to 2.