JP3031300B2 - Manufacturing method of liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device, more particularly, to a method of manufacturing an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art At present, liquid crystal display devices are widely used for monitors of personal computers as displays having characteristics such as light weight and low power consumption. In particular, an active matrix type liquid crystal display device in which a thin film transistor is formed for each pixel can be used for various uses as a high-definition display because the brightness of each pixel can be finely changed by voltage control.

The structure and operating principle of a general prior art active matrix type liquid crystal display device will be described below with reference to FIGS. 5 and 6. FIG. FIG.
FIG. 6 is a cross-sectional view illustrating a general conventional active matrix type liquid crystal display device, and FIG. 6 is a plan view illustrating a configuration of a thin film transistor array formed in a matrix on an insulating substrate.

[0004] As shown in the figure, a first insulating substrate 1 and a second insulating substrate 2 are located in parallel and opposed to each other, and a liquid crystal 10 as a display material is sandwiched in a gap therebetween. Among the insulating substrates, the scanning lines (G0 to Gn) 3 and the signal lines (S1 to S1) are provided on one main surface of the first insulating substrate 1 on the side in contact with the liquid crystal.
Sn) 4 are formed, and a pixel electrode 6 made of a transparent conductive film is formed on one of the electrodes of the thin film transistors 5 arranged in a matrix at the intersections of these.

Further, a second insulating substrate 1 facing the first insulating substrate 1
One main surface of the insulating substrate 2 on the side in contact with the liquid crystal has R, G,
Color layers 7, 8, and 9 of the three primary colors B are formed on the first substrate 1 at locations corresponding to the respective pixel electrodes 6, and further thereon to shield the boundaries between the respective color layers 7, 8, and 9 from light. The black matrix 11 and a common electrode 12 made of a transparent conductive film are formed.

In the liquid crystal display device having this configuration, a voltage for turning on the thin film transistor 5 is supplied to the scanning line 3 at a constant period, and a signal voltage corresponding to an image to be displayed is supplied to the signal line 4. The thin film transistor 5 connected to the scanning line 3 operates, and a predetermined voltage is applied from the signal line 4 to the pixel electrode 6. As a result, a potential difference is generated between the pixel electrode 6 and the common electrode 12 to drive the molecules of the liquid crystal, thereby changing the amount of light transmitted through the paths of the insulating substrate 1, the liquid crystal 10, and the insulating substrate 2. An image or the like is displayed using the change in the light transmission state.

FIG. 7 shows a manufacturing process of an inverted staggered thin film transistor generally used in a conventional active matrix type liquid crystal display device, and FIG. 8 shows an active matrix formed by the manufacturing process shown in FIG. FIG. 1 shows a plan view of a thin film transistor array of the type.

A general inverted stagger type thin film transistor shown in FIG. 7 has a gate electrode 14, a gate insulating film 15 thereon, and a gate insulating film 15 facing the gate electrode 14 on a transparent insulating substrate 13 such as glass. It has a structure in which the semiconductor film 16 and the ohmic contact film 17 formed thereon, the source electrode 19 and the drain electrode 18 connected to the ohmic contact film 17, and the protective film 21 are further laminated thereon. .

The manufacturing process of the inverted staggered thin film transistor will be described below with reference to FIG. First, FIG.
As shown in FIG. 1, A is placed on a transparent insulating substrate 13 such as glass.
A first conductive film made of l, Mo, Cr or the like is deposited on the entire surface by a sputtering method or the like. Next, a photosensitive resist is applied on the entire surface of the metal film, and a predetermined pattern such as the gate electrode 14, the scanning line 3, and the scanning line input pad 22 is exposed and developed to form a predetermined pattern on the resist. Further, the first conductive film is etched using this resist as a mask to form a predetermined pattern such as a gate electrode 14 and a scanning line, and then the resist is stripped to complete the patterning of the conductive film. Hereinafter, the process from application of the resist to stripping is referred to as photolithography.

[0010] Subsequently, as shown in FIG. 7 (b), a sputtering method or a plasma CVD method is performed on a predetermined pattern of the first conductive film.
SiOx or SiNx that becomes the gate insulating film 15 by a method such as
In order to make an ohmic contact between the semiconductor film 16 made of amorphous silicon (hereinafter referred to as a-Si) or the like and the semiconductor film 16 and the source and drain electrodes, n
An ohmic contact film 17 of type a-Si or the like is sequentially and sequentially deposited on the entire surface. Next, n-type a-Si and a-Si
Is formed on the insulating film on the gate electrode by photolithography.

Next, as shown in FIG. 7C, the first conductive film and the second conductive film forming the source electrode, the drain electrode, the signal line and the like are formed by the scanning line and the signal line input pad portion. In order to establish conduction, the gate insulating film having a predetermined pattern is etched by photolithography to form an opening in the gate insulating film over the first conductive film. Then, Al and M
A second conductive film made of o, Cr, or the like is deposited on the entire surface by sputtering or the like, and the signal line 4, the source electrode 19, and the drain electrode 18 are formed by photolithography.

Further, as shown in FIG. 7D, a transparent conductive film such as ITO is deposited on the entire surface, a pixel electrode 20 is formed by photolithography, and thereafter, etching is performed using the source and drain electrodes as a mask. The n-type a-Si in the channel portion is removed. Finally, SiNx
Then, the protective film 21 is deposited on the entire surface, and the protective film on the pixel electrode and the pad for inputting a signal from the outside is removed by photolithography to complete the formation of the thin film transistor.

In the conventional thin film transistor array of the liquid crystal display device, each scanning line 3 and each signal line 4 are electrically separated one by one. In the manufacturing process of this conventional liquid crystal display device, peeling charging when an insulating substrate is removed from a tray or the like in a film forming device or an etching device in each process, or a pattern of a conductive film is charged up in a film forming process or an etching process. The phenomenon of charging occurs.

In particular, in a process of forming an insulating film or a semiconductor film using a plasma CVD method and a dry etching process,
Since the substrate is exposed to the plasma for a long time, charging tends to occur. In addition to such charging, an extremely large amount of electric charge may be momentarily applied to a specific signal line or scanning line due to abnormal discharge or the like during a film formation process. This also often occurs in a film forming process using a plasma CVD method. At this time, when adjacent scanning lines or signal lines are not electrically connected to each other, the possibility that the difference in charge amount or the charge applied due to abnormal discharge exceeds the breakdown voltage increases, and the adjacent scanning lines Sudden current flows between the lines or between the signal lines, causing defects such as disconnection of wiring, short circuit, or breakdown of insulating film. Further, even in the case where disconnection or short circuit does not occur, there is a problem that charge is injected into the gate insulating film in the transistor portion, a threshold value is shifted, and transistor characteristics are changed to cause a point defect.

In particular, like the conventional scanning line, a wiring pattern such as a scanning line or a signal line formed first on the transparent insulating substrate is passed until the formation of the thin film transistor is completed. There are many film and dry etching processes, and the pattern length is relatively long and the area is large. Therefore, the amount of charge due to charge-up is large, and there are problems such as disconnection and short-circuit failure.

[0016]

FIG. 9 shows an active matrix type thin film transistor array of a general liquid crystal display device in which all scanning lines and all signal lines are connected by a common line in order to solve the above problems. FIG. The thin film transistor has the same structure as the inverted staggered thin film transistor shown in FIG. Each signal line and scanning line are led out via the scanning signal input pad 22 or the signal line input pad 23, and are connected to the signal line side common line 29 or the scanning line side common line 28.

With such a structure, since all the scanning lines and the signal lines have the same potential, a sudden current does not flow between adjacent scanning lines or signal lines. Further, even when a large charge is applied to a specific scanning line or signal line due to abnormal discharge or the like, the electric charge is dispersed and flows to all the scanning lines or signal lines, so that the specific line is destroyed or a specific line is broken. Changes in characteristics of the thin film transistor are reduced.

In such a conventional structure, a defect detection inspection after forming a thin film transistor is performed by the following method. That is, the signal line side collective pad 27 and the scan line side collective pad 2
6, signal line side measurement pad 24, scanning line side measurement pad 25
With a needle, etc., to measure the resistance between the signal line-side batch pad and the scanning line-side batch pad, or the resistance between the scanning line-side batch pad and the scanning line-side measurement pad, and the signal line side batch pad and the signal line measurement. By measuring the resistance between the pads and the resistance between the scanning line side collective pad and the scanning line measuring pad, etc., scanning for short-circuit and disconnection of each signal line and scanning line is performed. Method)).

On the other hand, a new inspection method for inspecting a defect of a transistor or a defect of a storage capacitor of each pixel is disclosed in Japanese Patent Laid-Open No. 3-2.
No. 00121 (hereinafter, this inspection method is referred to as an array tester method). This inspection method will be described below. First, a voltage at which a transistor is turned on is sequentially applied to each scanning line, and a signal voltage is also input to a signal line in synchronization with the voltage to store a certain charge in each pixel. Next, a voltage at which the transistor is turned off is applied, this charge is held for a certain period of time, then each transistor is turned on again, and the value of the charge stored in the pixel flowing out to the signal line as a discharge current is measured. If the pixel is formed normally, the amount of charge stored in the pixel is determined by the ON current of the transistor and the time during which the transistor is ON. Since the value is constant, the value of the discharge current flowing to the signal line is also constant. If a pixel has a defective characteristic of a thin film transistor or a pattern defect such as a short circuit between a pixel electrode and a scanning line or a signal line, the electric charge stored in the pixel becomes the electric charge to be stored in a normal pixel. Since the comparison becomes smaller, the discharge current flowing to the signal line also becomes smaller, and it can be detected as a defect. That is, in the array tester method, a point defect defect can be detected in addition to a line defect defect caused by a short circuit or disconnection of each signal line or scanning line.

However, the conventional transistor array structure in which all the scanning lines and the signal lines are connected to the common line has the following problems when applying this array tester type inspection. That is, when the thin film transistor of a specific pixel is turned on and charge is stored in the pixel, even if a predetermined voltage is applied to a specific scanning line and a signal line, all the scanning lines and signal Since the lines are electrically connected, all the thin film transistors are turned on, and electric charges are stored in all the pixels. Therefore, it is not possible to measure a discharge current for each pixel, and to detect a point defect. Can not. In other words, in the conventional transistor array structure, defects due to static electricity can be reduced, but inspection can only be performed by a batch method. Therefore, point defect defects caused by characteristic defects or patterning defects of the thin film transistor flow to the next step. Problem.

Therefore, in order to prevent electrostatic breakdown and perform an inspection using an array tester, a thin film transistor array structure as shown in FIGS. 10 and 11 has been considered. FIG. 10 shows a structure in which each scanning line and each signal line are connected by two diodes 30 and a contact hole 31 for disconnection (Japanese Patent Laid-Open No. 63-106788). In FIG. 10, the occurrence of defects due to static electricity can be reduced by dispersing static electricity externally applied to the entire thin-film transistor array via a diode.
Because the etching can be performed not only during the formation process of the thin film transistor array or after completion of the formation, but also at any time when the alignment processing, the liquid crystal encapsulation work, etc. are completed,
It has a structure that does not easily cause defects due to static electricity. Also, in FIG. 11, by connecting to two common lines 32 via two diodes 30 and applying a voltage to the respective common lines to cause the diodes to be in a reverse bias state, the electrostatic capacitance can be obtained without affecting the display unit. The structure is such that inspection can be performed while preventing destruction. In the case of this structure,
Finally, the short-circuit line 29 is cut by a laser cutter or the like.

However, in the transistor array structure shown in FIGS. 10 and 11, the wiring is finally separated by a large impedance, so that the inspection using the array tester method can be performed. In FIG. 10, however, two diodes are used. There is a problem in that they are formed in an interval of about 100 μm and are close to the pixel portion, so that patterning failure or the like is likely to occur. In addition, a new etching step needs to be added in order to release an electric short circuit, which causes a problem that a process load increases. Further, in the transistor array structure of FIG. 13, the length of the common line in the outer peripheral portion is long, and short-circuit and disconnection are likely to occur. Further, the short-circuit line is cut by a laser cutter or the like. However, there are problems such as an increase in the number of steps and generation of dust at the time of cutting, which is likely to cause a defect.

Japanese Patent Application Laid-Open No. 8-262485 discloses FIG.
Such a thin film transistor array structure has been considered. (A) is a plan view showing a thin film transistor array,
(B) is a plan view showing the bidirectional transistor of (a),
(C) is a cross-sectional view taken along line CC of (b), and (d) is a diagram showing an equivalent circuit of (b). This thin-film transistor array is provided between common lines 28 and 29 for making each signal line and each scanning line the same potential, and pads 22 and 23 on a substrate for inputting signals to each signal line and each scanning line. The configuration is such that the connection is made via the bidirectional transistor 34 (FIG. 12A). This bidirectional transistor has the same structure as the thin film transistor of each pixel, and is formed the same in the step of forming the thin film transistor of each pixel (FIGS. 12B and 12C). An equivalent circuit of this bidirectional transistor is shown in FIG. The voltage (approximately several volts to 20 volts) applied to the above-described inspection of the failure of the transistor and the storage capacitor of each pixel indicates a resistance of several hundred kΩ. Point defects and the like can be detected with little accuracy and high accuracy.
Also, when a large amount of power (up to several KV) is momentarily applied to a specific scanning line or signal line, one of the bidirectional transistors is turned on to reach several KΩ.
Since the resistance is about the same level, charges can be released to the common line, and damage to a specific scanning line or signal line and shift of characteristics of the thin film transistor can be reduced. Furthermore, the resistance of this bidirectional transistor can be changed relatively easily by designing the transistor size, such as the channel length and channel width. Therefore, the resistance should be arbitrarily designed according to the conditions of the production line, such as the voltage applied by the inspection device. Can be. However, in the thin film transistor array structure shown in FIG. 12, although the inspection by the array tester method can be performed, the common line on the scanning line side is formed until the formation of the drain electrode and the source electrode is completed and before the thin film transistor is formed. And each scanning line is not electrically connected, so that each is electrically isolated as in the conventional example shown in FIG. 6, which is a sufficient measure against electrostatic breakdown. Not. Further, since two transistors are formed between the wirings, there is a problem that a defect such as a short circuit due to a pattern defect is likely to occur.

It is an object of the present invention to provide a method of manufacturing a liquid crystal display device to which an inspection by an array tester method after completion of a process of forming a thin film transistor array can be applied without reducing defects due to static electricity and without increasing a process load. is there.

[0025]

[0026]

[0027]

In order to achieve the above object,
Therefore, the manufacturing method of the liquid crystal display device according to the present invention, the liquid crystal,
A method for manufacturing a liquid crystal display device including a scanning line and a signal line, a pixel electrode, and a thin film transistor, wherein the liquid crystal includes:
The scanning lines and the signal lines are sandwiched between gaps between a first substrate and a second substrate facing each other in parallel, and the scanning lines and the signal lines are arranged on a main surface of the first substrate on a side in contact with a liquid crystal. Wherein the pixel electrode is formed at an intersection of the scanning line and the signal line, and the thin film transistor is disposed near an intersection of the scanning line and the signal line, and the scanning line and the pixel Source and drain electrodes are connected to the electrodes, a gate electrode is connected to the scanning line,
The second substrate includes a black matrix, a color filter, and a transparent conductive film formed thereon. The thin film transistor has an inverted staggered structure, and includes the scanning line and the signal line. Are made of the same material, and all the scanning lines are connected to a common line arranged in the peripheral portion of the first substrate, and at the time of forming a pattern of a contact hole connecting the scanning line and the signal line, A contact hole is formed in a separation region between a scanning line and a common line, and at the same time when a signal line pattern is formed, a scanning line exposed in the contact hole portion is etched to separate a scanning line from a peripheral common line. is there.

A method of manufacturing a liquid crystal display device according to the present invention is a method of manufacturing a liquid crystal display device having a liquid crystal, a scanning line and a signal line, a pixel electrode, and a thin film transistor, wherein the liquid crystals are parallel to each other. And the scanning lines and the signal lines are arranged on the main surface of the first substrate on the side in contact with the liquid crystal, wherein the first substrate and the second substrate are sandwiched by a gap between the first substrate and the second substrate. The pixel electrode is formed at an intersection of the scanning line and the signal line, and the thin film transistor is disposed near an intersection of the scanning line and the signal line, and the pixel electrode is formed on the scanning line and the pixel electrode. Source and drain electrodes are connected, and a gate electrode is connected to the scan line. The second substrate has a black matrix, a color filter, and a transparent conductive film formed thereon. , The thin film transistor has a forward staggered structure, wherein the scanning lines and the signal lines are made of the same material, and all the signal lines are common lines arranged around the first substrate. And forming a contact hole in a separation region between the signal line and the common line when forming a contact hole pattern for connecting a scanning line and a signal line, and simultaneously exposing the contact hole portion when forming a scanning line pattern. That is, the signal line is etched to separate the signal line from the common line.

[0029]

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing the vicinity of the outer periphery of a thin film transistor array according to Embodiment 1 of the present invention in the order of steps, and FIG. 2 is a sectional view taken along line AA of FIG. .

As shown in FIGS. 1A and 2A,
The thin-film transistor array of the present invention comprises a transparent insulating substrate 13
A first conductive film 38 made of Al, Mo, Cr or the like is formed thereon.
Is deposited by sputtering or the like to a thickness of about 1000 to 5000 °, and the gate electrode 14, the scanning line 3, the scanning line side input pad 22, and the common line 32 are deposited by photolithography.
Are formed in a predetermined pattern. Further, the gate electrode and the scanning line, the scanning line input pad, and the common line are integrally formed, and are all electrically connected.

Next, as shown in FIGS. 1 (b) and 2 (b), a gate insulating film 15 made of SiOx or SiNx, a semiconductor thin film 16 made of a-Si or the like, a semiconductor thin film and a source / drain electrode. In order to make ohmic contact, ohmic contact films 17 made of n ⁺ -type a-Si or the like are sequentially deposited at 1000 to 5000 ° and 500 °, respectively.
CV at a film thickness of about 4000 ~ and about 100 ~ 1000 ~
It is deposited on the entire surface by using the D method or the like. Thereafter, an ohmic contact film and a semiconductor film are formed in a predetermined pattern of the thin film transistor portion by photolithography.

Further, as shown in FIGS. 1C and 2C, the first conductive film is formed by photolithography.
A contact hole for establishing conduction of a second conductive film for forming a signal line or the like is formed. At this time, a contact hole 30 for separating the scanning line and the peripheral common line is also formed on the first conductive film between the scanning line input pad and the peripheral common line, thereby exposing the first conductive film.

Next, as shown in FIGS. 1D and 2D, the first conductive film 39 is formed as the second conductive film 39 by using a sputtering method or the like.
Conductive films made of the same material as the conductive film
The signal line 4, the signal line side input pad 23, the source electrode 19, the drain electrode 18 and the like are formed in a predetermined pattern by photolithography. Further, at the time of forming the pattern of the second conductive film, the stacked film of the second conductive film and the first conductive film in the separation contact hole is also removed by etching, and the scanning line and the peripheral common line are separated.

The material of the first conductive film, the material and temperature of the gate insulating film, and the surface of the second conductive film on the gate insulating film side are deteriorated by the action of heat or the like at the time of forming the gate insulating film.
Etching may be difficult. In particular, in the case where the etching for forming the pattern of the second conductive film is performed by wet etching, the surface of the deteriorated first conductive film cannot be etched or the etching rate becomes lower than the etching rate of the second conductive film. Longer than that,
Such a problem arises.

Therefore, when etching the second conductive film, it is effective to dry-etch at least the vicinity of the surface of the first conductive film. Furthermore, IT
A transparent conductive film made of O or the like is deposited in a thickness of about 100 to 1000 °, the pixel electrode 6 is formed by photolithography, and the ohmic contact film in the channel portion of the thin film transistor is removed by etching (FIG. 1).
(E) and FIG. 2 (e)).

Finally, SiOx, SiNx, or the like is deposited by about 500 to 5000 ° by sputtering or plasma CVD, and a protective film 21 is formed by photolithography to complete the process (FIGS. 1F and 2F). )).

In the thin-film transistor array according to the present embodiment described above, in the process of forming the pattern of the second conductive film and simultaneously disconnecting the connection between the scanning line and the common line, all the scanning lines are connected to the common line. To the same potential, the peripheral common line can be connected even when a very large charge is applied to a specific scanning line due to charge-up or abnormal discharge caused by peeling charge generated in the manufacturing equipment. Since the electric charges are dispersed and flow to all the lines, a sudden excessive current does not flow to a specific scanning line, and the disconnection and short circuit of the scanning line, the breakdown of the insulating film, the change in the characteristics of the transistor, and the like are reduced. be able to.

In particular, since the thin film transistor is exposed to the plasma for the longest time during the formation thereof, all the scanning lines are connected to the common line in the gate insulating film forming step or the etching step in which a defect due to charge-up or abnormal discharge is likely to occur. , So that defects can be significantly reduced. further,
Since the connection between the common line and the scanning line can be separated at the same time when the signal line pattern is formed, each scanning line can be separated without adding a new etching step and without increasing the process load. .

Therefore, when the formation of the thin film transistor is completed, since each scanning line is electrically separated one by one, it is possible to carry out the inspection by the array tester system, and the defective thin film transistor array is replaced by the next one. It can be prevented from flowing out to the process.

(Embodiment 2) Next, Embodiment 2 in which the present invention is applied to a forward staggered thin film transistor array will be described in detail with reference to FIGS.

FIG. 3 is a plan view showing the vicinity of the outer periphery of the thin film transistor array according to the second embodiment of the present invention in the order of steps, and FIG. 4 is a sectional view taken along line BB of FIG.

As shown in FIGS. 3A and 4A,
The thin-film transistor array of the present invention comprises a transparent insulating substrate 13
A metal such as Al, Mo, or Cr, or an organic material is deposited thereon to a thickness of about 1000 to 5000 mm, and a pattern is formed as a light shielding film 36 at a position corresponding to a channel portion of the thin film transistor by photolithography or the like.

Next, as shown in FIGS. 3 (b) and 4 (b), an interlayer insulating film 37 made of SiNx, an organic material, or the like is formed.
A pixel electrode, a drain electrode and the like are formed by photolithography.

Thereafter, as shown in FIG. 3C and FIG. 4C, a first conductive film made of Al, Mo, Cr, or the like is formed on the entire surface by a sputtering method or the like to a thickness of about 1,000 to 5,000. The signal line 4, the signal line side input pad 23, the common line 32 and the like are formed in a predetermined pattern by photolithography. The signal line, the signal line input pad, and the common line are integrally formed, and are all electrically connected.

Next, as shown in FIGS. 3D and 4D, a semiconductor thin film 16 made of a-Si or the like and SiOx
A gate insulating film 15 made of, for example, SiNx or the like is deposited on the entire surface in a thickness of about 1000 to 5000 ° by a sputtering method, a CVD method, or the like, and formed into a predetermined pattern of a thin film transistor portion by photolithography.

Thereafter, as the protective film 21, SiOx or Si
Nx or the like is deposited on the entire surface by sputtering or CVD, etc.
A predetermined pattern is formed by photolithography to establish conduction between the first conductive film and a second conductive film forming a scanning line and the like and to remove a protective film on an input pad on a signal line side and a pixel electrode. I do. At this time, a contact hole 30 for separating the signal line and the common line is also formed on the first conductive film between the signal line-side input pad and the common line to expose the first conductive film.

Next, as shown in FIGS. 3F and 4F, a conductive film made of the same material as that of the first conductive film is used as the second conductive film 39 by sputtering or the like. 30
The film is deposited on the entire surface with a thickness of about 00 °, and the scanning line 3, the scanning line side input pad 22, the gate electrode 14 and the like are formed in a predetermined pattern by photolithography. Further, at the time of forming the pattern of the second conductive film, the separation contact hole is removed by etching the laminated film of the second conductive film and the first conductive film, and the scanning line and the peripheral common line are separated. Complete array formation.

Further, as for the etching at the time of forming the pattern of the second conductive film, the surface of the first conductive film on the side of the protective film is deteriorated so that wet etching cannot be performed or a relatively long period of time. Due to such problems, it is preferable to dry-etch at least the vicinity of the surface of the first conductive film on the protective film side.

In the thin-film transistor array according to the second embodiment of the present invention described above, all the signal lines are connected to the common line during the process until the etching of the second conductive film is completed. Defects due to discharge can be significantly reduced. Also, since the connection between the common line and the signal line is separated at the same time as the formation of the scanning line pattern, each signal line can be separated without increasing the process load, and the inspection by the array tester method can be performed. In addition, it is possible to prevent the defective thin film transistor array from flowing out to the next step.

[0052]

As described above, according to the present invention, all the scanning lines or signal lines which are the patterns of the first conductive film formed first on the transparent insulating substrate such as glass are connected to the common line. The same potential is applied to the peripheral common line even when a very large charge is applied to a specific scanning line or signal line due to charge-up or abnormal discharge caused by peeling charge generated in the manufacturing equipment. The charge is dispersed and flows to all the lines through the circuit, so that a sudden excess current does not flow to a specific scanning line or signal line, and the scanning line or the signal line is disconnected or short-circuited, the insulating film is broken, and the transistor is damaged. Characteristic changes, etc. can be reduced.

Further, the connection between the common line and the scanning line or the signal line can be separated at the same time when the signal line or the scanning line is formed by the second conductive film. Therefore, each scanning line or signal line can be separated without adding a new etching step, and inspection can be performed by an array tester method, thereby preventing a defective thin film transistor array from flowing to the next step. can do.

[Brief description of the drawings]

FIG. 1 is a plan view showing one display pixel portion including an inverted staggered thin film transistor according to a first embodiment of the present invention and the vicinity of the periphery of a substrate in the order of steps.

FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1 and shown in a process order.

FIG. 3 is a plan view showing one display pixel portion including a forward stagger type thin film transistor according to a second embodiment of the present invention and the vicinity of the outer periphery of a substrate in order of process.

4 is a cross-sectional view taken along a line BB in FIG. 3 and shown in the order of steps.

FIG. 5 is a cross-sectional view showing a liquid crystal display device according to a conventional example.

FIG. 6 is a plan view showing a thin film transistor array according to a conventional example.

FIG. 7 is a cross-sectional view showing the order of manufacturing steps of an inverted staggered thin film transistor according to a conventional example.

FIG. 8 is a plan view showing a thin film transistor array according to a conventional example.

FIG. 9 is a plan view showing a thin film transistor array according to a conventional example.

FIG. 10 is a plan view showing a thin film transistor array according to a conventional example.

FIG. 11 is a plan view showing a thin film transistor array according to a conventional example.

12A is a plan view illustrating a thin film transistor array according to a conventional example, FIG. 12B is a plan view illustrating a resistor structure, FIG. 12C is a cross-sectional view illustrating the resistor structure, and FIG. FIG. 4 is an equivalent circuit diagram of a resistor unit structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st insulating substrate 2 2nd insulating substrate 3 scanning line 4 signal line 5 thin film transistor 6 pixel electrode 7 color layer (R) 8 color layer (G) 9 color layer (B) 10 liquid crystal 11 black matrix 12 common Electrode 13 Transparent insulating substrate 14 Gate electrode 15 Gate insulating film 16 Semiconductor film 17 Ohmic contact film 18 Drain electrode 19 Source electrode 20 Pixel electrode 21 Protective film 22 Scan line side input pad 23 Signal line side input pad 24 Signal line side measurement pad 25 Scan line side measurement pad 26 Scan line side batch pad 27 Signal line side batch pad 28 Scan line side common line 29 Signal line side common line 30 Separation contact hole resistance 31 Diode 32 Common line 33 Short circuit line 34 Resistance 35 Cutting line 36 Light shielding Film 37 interlayer insulating film 38 first conductive film 39 second conductive film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/136 G02F 1/1343 G02F 1/1345 G02F 1/13 101 H01L 29/78

Claims (2)

(57) [Claims] 1. A method of manufacturing a liquid crystal display device including a liquid crystal, a scanning line and a signal line, a pixel electrode, and a thin film transistor, wherein the liquid crystal is opposed to a first substrate and a second substrate in parallel with each other. The scanning lines and the signal lines are disposed on a main surface of the first substrate on the side in contact with the liquid crystal, and the pixel electrode is disposed between the scanning lines and the signal lines. The thin film transistor is disposed close to the intersection of the scanning line and the signal line, a source and a drain electrode are connected to the scanning line and the pixel electrode, and the thin film transistor is connected to the scanning line. A gate electrode connected thereto; the second substrate has a black matrix, a color filter, and a transparent conductive film formed thereon; and the thin film transistor has an inverted staggered structure. Wherein the scanning line and the signal line are made of the same material, and all of the scanning lines are connected to a common line arranged around the first substrate. At the time of forming a pattern of a contact hole for connecting the signal line, a contact hole is formed in a separation region between a scanning line and a common line, and simultaneously with the formation of a signal line pattern, a scanning line exposed at the contact hole portion is etched. Wherein the scanning line and the peripheral common line are separated from each other. 2. A method for manufacturing a liquid crystal display device including a liquid crystal, a scanning line and a signal line, a pixel electrode, and a thin film transistor, wherein the liquid crystal is provided in parallel with a first substrate and a second substrate. The scanning lines and the signal lines are disposed on a main surface of the first substrate on the side in contact with the liquid crystal; and the pixel electrode is disposed between the scanning lines. The thin film transistor is formed at an intersection of a signal line, the thin film transistor is arranged near an intersection of the scanning line and the signal line, and a source and a drain electrode are connected to the scanning line and a pixel electrode, and the scanning line The second substrate has a black matrix, a color filter, and a transparent conductive film formed thereon, and the thin film transistor has a forward stagger type. Wherein the scanning line and the signal line are made of the same material, and all of the signal lines are connected to a common line arranged around the first substrate. A contact hole is formed in a separation region between a signal line and a common line when a pattern of a contact hole connecting a line is formed, and simultaneously, when a pattern of a scanning line is formed, a signal line exposed in the contact hole portion is etched to form a signal. A method for manufacturing a liquid crystal display device, wherein a line and a common line are separated.