JP3005918B2 - Active matrix panel - Google Patents
Active matrix panelInfo
- Publication number
- JP3005918B2 JP3005918B2 JP16518591A JP16518591A JP3005918B2 JP 3005918 B2 JP3005918 B2 JP 3005918B2 JP 16518591 A JP16518591 A JP 16518591A JP 16518591 A JP16518591 A JP 16518591A JP 3005918 B2 JP3005918 B2 JP 3005918B2
- Authority
- JP
- Japan
- Prior art keywords
- active matrix
- tft
- film
- silicon oxide
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011159 matrix material Substances 0.000 title claims description 59
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 33
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 31
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 11
- 239000010408 film Substances 0.000 description 93
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 33
- 229920005591 polysilicon Polymers 0.000 description 33
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は駆動回路部を備えたア
クティブマトリクスパネルに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix panel having a driving circuit.
【０００２】[0002]
【従来の技術】例えばアクティブマトリクス型の液晶デ
ィスプレイ装置には、ガラス等からなる透明基板上にア
クティブマトリクス部用ＴＦＴ（薄膜トランジスタ）の
ほかに駆動回路部用ＴＦＴを形成してなるアクティブマ
トリクスパネルを備えたものがある。図８は従来のこの
ようなアクティブマトリクスパネルの回路構成の一例を
示したものである。このアクティブマトリクスパネルで
は、行方向に走査電極１が列方向に表示電極２がそれぞ
れ設けられ、走査電極１と表示電極２との各交点に対応
する各画素（液晶）３ごとにアクティブマトリクス部用
ＴＦＴ４が設けられ、走査電極１の一端部にゲート駆動
回路部用ＴＦＴ５が設けられ、１本おきの表示電極２の
一端部および残りの表示電極２の他端部にデータ駆動回
路部用ＴＦＴ６、７がそれぞれ設けられ、そしてアクテ
ィブマトリクス部用ＴＦＴ４がオンになると、画素３の
静電容量部に表示データが電荷の形で書き込まれ、アク
ティブマトリクス部用ＴＦＴ４がオフになると、書き込
まれた電荷により画素３が駆動されるようになってい
る。ところで、アクティブマトリクス部用ＴＦＴ４およ
び駆動回路部用ＴＦＴ５〜７は、半導体層を構成するポ
リシリコンの下地として酸化シリコンが設けられてい
る。2. Description of the Related Art For example, an active matrix type liquid crystal display device is provided with an active matrix panel formed by forming a TFT for a driving circuit portion in addition to a TFT (thin film transistor) for an active matrix portion on a transparent substrate made of glass or the like. There are things. FIG. 8 shows an example of a circuit configuration of such a conventional active matrix panel. In this active matrix panel, a scanning electrode 1 is provided in a row direction and a display electrode 2 is provided in a column direction, and each pixel (liquid crystal) 3 corresponding to each intersection of the scanning electrode 1 and the display electrode 2 has an active matrix portion. A TFT 4 is provided, a gate drive circuit unit TFT 5 is provided at one end of the scanning electrode 1, and a data drive circuit unit TFT 6 is provided at one end of every other display electrode 2 and the other end of the remaining display electrodes 2. 7 are provided, and when the active matrix portion TFT 4 is turned on, display data is written in the form of electric charges in the capacitance portion of the pixel 3, and when the active matrix portion TFT 4 is turned off, the written electric charges The pixel 3 is driven. Incidentally, the active matrix portion TFT 4 and the drive circuit portion TFTs 5 to 7 are provided with silicon oxide as a base of polysilicon constituting a semiconductor layer.
【０００３】[0003]
【発明が解決しようとする課題】しかるに、従来のこの
ようなアクティブマトリクスパネルでは、アクティブマ
トリクス部用ＴＦＴ４と駆動回路部用ＴＦＴ５〜７とで
要求される特性に違いがあり、駆動回路部用ＴＦＴ５〜
７の場合、移動度を高めるためにオン電流を十分高くし
なければならないが、カットオフ電流についてはアクテ
ィブマトリクス部用ＴＦＴ４ほど低くする必要はなく、
一方、アクティブマトリクス部用ＴＦＴ４の場合、リー
ク電流を小さくするためにカットオフ電流を十分低くし
なければならないが、オン電流については駆動回路部用
ＴＦＴ５〜７ほど高くする必要はない。しかしながら、
ＴＦＴの半導体層がポリシリコンでその下地が酸化シリ
コンであると、駆動回路部用ＴＦＴ５〜７のオン電流を
十分に高くすることができるが、アクティブマトリクス
部用ＴＦＴ４のカットオフ電流を十分に低くすることが
できず、このため表示品質が低下するという問題があっ
た。この発明の目的は、駆動回路部用ＴＦＴのオン電流
を低下させることなく、アクティブマトリクス部用ＴＦ
Ｔのカットオフ電流を十分に低くすることのできるアク
ティブマトリクスパネルを提供することにある。However, in such a conventional active matrix panel, there is a difference in characteristics required between the active matrix portion TFT 4 and the drive circuit portion TFTs 5 to 7, and the drive circuit portion TFT 5 ~
In the case of 7, the on-current must be sufficiently high to increase the mobility, but the cut-off current does not need to be as low as that of the TFT 4 for the active matrix portion.
On the other hand, in the case of the TFT 4 for the active matrix portion, the cutoff current must be sufficiently reduced in order to reduce the leakage current, but the ON current does not need to be as high as the TFTs 5 to 7 for the drive circuit portion. However,
When the semiconductor layer of the TFT is made of polysilicon and the underlying layer is made of silicon oxide, the on-currents of the driving circuit portion TFTs 5 to 7 can be made sufficiently high, but the cut-off current of the active matrix portion TFT 4 is made sufficiently low. Therefore, there is a problem that display quality is deteriorated. An object of the present invention is to provide a TFT for an active matrix unit without reducing the on-state current of a TFT for a drive circuit unit.
An object of the present invention is to provide an active matrix panel capable of sufficiently reducing the cutoff current of T.
【０００４】[0004]
【課題を解決するための手段】この発明は、ＴＦＴのオ
ン電流およびカットオフ電流が共に下地が酸化シリコン
の場合よりも窒化シリコンの場合の方が低くなることに
着目し、アクティブマトリクス部用ＴＦＴの下地を窒化
シリコン膜とし、且つ駆動回路部用ＴＦＴの下地を酸化
シリコン膜としたものである。SUMMARY OF THE INVENTION The present invention focuses on the fact that both the on-current and the cut-off current of a TFT are lower in the case of silicon nitride than in the case of silicon oxide as an underlayer, Is a silicon nitride film, and a TFT for the drive circuit portion is a silicon oxide film.
【０００５】[0005]
【作用】この発明によれば、アクティブマトリクス部用
ＴＦＴの下地を窒化シリコン膜としているので、アクテ
ィブマトリクス部用ＴＦＴのカットオフ電流を下地が酸
化シリコン膜の場合と比較して十分に低くすることがで
き、しかも駆動回路部用ＴＦＴの下地を酸化シリコン膜
としているので、駆動回路部用ＴＦＴのオン電流が低下
しないようにすることができる。According to the present invention, the base of the active matrix TFT is made of a silicon nitride film, so that the cut-off current of the active matrix TFT is made sufficiently lower than that of the case where the base is a silicon oxide film. In addition, since the base of the TFT for the drive circuit portion is made of a silicon oxide film, the ON current of the TFT for the drive circuit portion can be prevented from decreasing.
【０００６】[0006]
【実施例】図１〜図６はそれぞれこの発明の一実施例に
おけるアクティブマトリクスパネルの各製造工程を示し
たものである。そこで、これらの図を順に参照しなが
ら、アクティブマトリクスパネルの構造についてその製
造方法と併せ説明する。1 to 6 show respective steps of manufacturing an active matrix panel according to an embodiment of the present invention. Therefore, the structure of the active matrix panel will be described together with the manufacturing method thereof with reference to these drawings in order.
【０００７】まず、図１に示すように、ガラス等からな
る透明基板１１の上面にスパッタリング装置を用いて下
地用酸化シリコン膜１２を１０００Å程度の厚さに形成
する。次に、下地用酸化シリコン膜１２の上面にプラズ
マＣＶＤ法により下地用窒化シリコン膜１３を１０００
Å程度の厚さに形成する。First, as shown in FIG. 1, an underlying silicon oxide film 12 is formed to a thickness of about 1000.degree. Next, an underlying silicon nitride film 13 is deposited on the upper surface of the underlying silicon oxide film 12 by a plasma CVD method.
It is formed to a thickness of about Å.
【０００８】次に、図２に示すように、フォトリソグラ
フィ技術により、アクティブマトリクス部用ＴＦＴ形成
領域に対応する部分以外の不要な部分の下地用窒化シリ
コン膜１３をエッチングして除去する。次に、全表面に
プラズマＣＶＤ法によりアモルファスシリコン膜１４を
１０００Å程度の厚さに形成する。次に、ＸｅＣｌエキ
シマレーザを照射することによりアモルファスシリコン
膜１４を結晶化してポリシリコン膜１５とする。この場
合、高いエネルギ密度でいきなりレーザ照射すると膜破
壊が生じるので、これを避けるために、３段階に分け
て、すなわちまず１８０ｍＪ／ｃｍ2のエネルギ密度
で、次いで２２０ｍＪ／ｃｍ2のエネルギ密度で、最後
に２７０ｍＪ／ｃｍ2のエネルギ密度でレーザ照射を行
う。Next, as shown in FIG. 2, unnecessary portions of the underlying silicon nitride film 13 other than the portion corresponding to the active matrix portion TFT forming region are etched and removed by photolithography. Next, an amorphous silicon film 14 is formed on the entire surface to a thickness of about 1000 ° by a plasma CVD method. Next, the amorphous silicon film 14 is crystallized by irradiation with a XeCl excimer laser to form a polysilicon film 15. In this case, since the sudden laser irradiation at a higher energy density membrane disruption occurs, in order to avoid this, in three phases, i.e. first an energy density of 180 mJ / cm 2, then with energy density of 220 mJ / cm 2, Finally, laser irradiation is performed at an energy density of 270 mJ / cm 2 .
【０００９】次に、図３に示すように、フォトリソグラ
フィ技術により、駆動回路部用の各ＴＦＴのチャネル領
域２１およびアクティブマトリクス部用の各ＴＦＴのチ
ャネル領域２２に対応する部分のポリシリコン膜１５の
上面にフォトレジスト膜２３、２４をパターン形成す
る。次に、フォトレジスト膜２３、２４をマスクとして
イオンインプラ装置またはイオンシャワ装置によりリン
イオンを注入し、各チャネル領域２１、２２に対応する
部分以外のポリシリコン膜１５を不純物領域化する。次
に、フォトレジスト膜２３、２４を剥離し、この後Ｘｅ
Ｃｌエキシマレーザを２２０ｍＪ／ｃｍ2のエネルギ密
度で照射し、活性化を行う。Next, as shown in FIG. 3, a portion of the polysilicon film 15 corresponding to the channel region 21 of each TFT for the drive circuit portion and the channel region 22 of each TFT for the active matrix portion is formed by photolithography. The photoresist films 23 and 24 are patterned on the upper surface of the substrate. Next, using the photoresist films 23 and 24 as masks, phosphorus ions are implanted by an ion implantation device or an ion shower device, and the polysilicon film 15 other than portions corresponding to the respective channel regions 21 and 22 is converted into an impurity region. Next, the photoresist films 23 and 24 are peeled off, and then Xe
Activation is performed by irradiating a Cl excimer laser with an energy density of 220 mJ / cm 2 .
【００１０】次に、フォトリソグラフィ技術により、駆
動回路部用ＴＦＴ形成領域およびアクティブマトリクス
部用ＴＦＴ形成領域に対応する部分以外の不要な部分の
ポリシリコン膜１５をエッチングして除去し、図４に示
すように、下地用酸化シリコン膜１２の上面に駆動回路
部用ポリシリコン膜３１を形成すると共に、下地用窒化
シリコン膜１３の上面にアクティブマトリクス部用ポリ
シリコン膜３２を形成する。この状態では、既に説明し
たように、図３に示す工程においてリンイオンを注入し
ているので、駆動回路部用ポリシリコン膜３１のチャネ
ル領域２１の両側にソース・ドレイン領域３４が形成さ
れ、またアクティブマトリクス部用ポリシリコン膜３２
のチャネル領域２２の両側にソース・ドレイン領域３５
が形成されている。Next, unnecessary portions of the polysilicon film 15 other than the portions corresponding to the TFT forming region for the drive circuit portion and the TFT forming region for the active matrix portion are removed by etching by photolithography. As shown, a polysilicon film 31 for a drive circuit portion is formed on the upper surface of the silicon oxide film 12 for the base, and a polysilicon film 32 for the active matrix portion is formed on the upper surface of the silicon nitride film 13 for the base. In this state, as already described, since phosphorus ions are implanted in the step shown in FIG. 3, source / drain regions 34 are formed on both sides of the channel region 21 of the drive circuit portion polysilicon film 31, and the active region is formed. Polysilicon film 32 for matrix part
Source / drain regions 35 on both sides of the channel region 22 of FIG.
Are formed.
【００１１】次に、図５に示すように、全表面にスパッ
タリング装置を用いて酸化シリコンからなるゲート絶縁
膜４１を１０００Å程度の厚さに形成する。次に、駆動
回路部用ポリシリコン膜３１のチャネル領域２１に対応
する部分のゲート絶縁膜４１の上面およびアクティブマ
トリクス部用ポリシリコン膜３２のチャネル領域２２に
対応する部分のゲート絶縁膜４１の上面にスパッタリン
グ装置を用いてアルミニウムからなるゲート電極４２、
４３を２０００Å程度の厚さにパターン形成する。Next, as shown in FIG. 5, a gate insulating film 41 made of silicon oxide is formed to a thickness of about 1000.degree. Next, the upper surface of the gate insulating film 41 corresponding to the channel region 21 of the polysilicon film 31 for the drive circuit portion and the upper surface of the gate insulating film 41 corresponding to the channel region 22 of the polysilicon film 32 for the active matrix portion. A gate electrode 42 made of aluminum by using a sputtering device,
43 is patterned to a thickness of about 2000 °.
【００１２】次に、図６に示すように、全表面にプラズ
マＣＶＤ法により窒化シリコンからなる層間絶縁膜５１
を５０００Å程度の厚さに形成する。次に、層間絶縁膜
５１の上面にスパッタリング装置を用いてＩＴＯからな
る透明電極（走査電極および表示電極）５２を１０００
Å程度の厚さにパターン形成する。次に、駆動回路部用
ポリシリコン膜３１のソース・ドレイン領域３４に対応
する部分の層間絶縁膜５１およびゲート絶縁膜４１にコ
ンタクトホール５３を形成すると共に、アクティブマト
リクス部用ポリシリコン膜３２のソース・ドレイン領域
３５に対応する部分の層間絶縁膜５１およびゲート絶縁
膜４１にコンタクトホール５４を形成する。次に、コン
タクトホール５３を通して駆動回路部用ポリシリコン膜
３１のソース・ドレイン領域３４と接続されるアルミニ
ウムからなるソース・ドレイン電極５５を層間絶縁膜５
１等の上面に６０００Å程度の厚さにパターン形成する
と共に、コンタクトホール５４を通してアクティブマト
リクス部用ポリシリコン膜３２のソース・ドレイン領域
３５と接続される同じくアルミニウムからなるソース・
ドレイン電極５６を層間絶縁膜５１等の上面に６０００
Å程度の厚さにパターン形成する。かくして、駆動回路
部を備えたアクティブマトリクスパネルが製造される。Next, as shown in FIG. 6, an interlayer insulating film 51 made of silicon nitride is formed on the entire surface by plasma CVD.
Is formed to a thickness of about 5000 °. Next, a transparent electrode (scanning electrode and display electrode) 52 made of ITO is formed on the upper surface of the interlayer insulating film 51 by using a sputtering apparatus.
A pattern is formed to a thickness of about Å. Next, a contact hole 53 is formed in a portion of the interlayer insulating film 51 and the gate insulating film 41 corresponding to the source / drain region 34 of the drive circuit portion polysilicon film 31, and the source of the active matrix portion polysilicon film 32 is formed. A contact hole 54 is formed in the portion of the interlayer insulating film 51 and the gate insulating film 41 corresponding to the drain region 35. Next, a source / drain electrode 55 made of aluminum connected to the source / drain region 34 of the drive circuit portion polysilicon film 31 through the contact hole 53 is formed on the interlayer insulating film 5.
1 and the like, and a pattern is formed to a thickness of about 6000.degree. And a source / drain region made of aluminum which is connected to the source / drain region 35 of the polysilicon film 32 for the active matrix portion through the contact hole 54.
The drain electrode 56 is formed on the upper surface of the interlayer insulating film 51 or the like by 6000.
A pattern is formed to a thickness of about Å. Thus, an active matrix panel having a drive circuit section is manufactured.
【００１３】ところで、アモルファスシリコンを結晶化
してなるポリシリコンを用いたＴＦＴにおいては、オン
電流およびカットオフ電流は共に下地が酸化シリコンの
場合よりも窒化シリコンの場合の方が低くなる。しかる
に、このアクティブマトリクスパネルでは、駆動回路部
用ポリシリコン膜３１の下地を酸化シリコン膜１２とし
ているので、駆動回路部用ＴＦＴのオン電流を下地が窒
化シリコン膜の場合と比較して十分に高くすることがで
き、一方、アクティブマトリクス部用ポリシリコン膜３
２の下地を窒化シリコン膜１３としているので、アクテ
ィブマトリクス部用ＴＦＴのカットオフ電流を下地が酸
化シリコン膜の場合と比較して十分に低くすることがで
きる。By the way, in a TFT using polysilicon obtained by crystallizing amorphous silicon, both the on-current and the cut-off current are lower in the case of silicon nitride than in the case of silicon oxide as the base. However, in this active matrix panel, the underlying silicon of the driving circuit portion polysilicon film 31 is the silicon oxide film 12, so that the on-state current of the driving circuit portion TFT is sufficiently higher than that in the case where the underlying silicon nitride film is used. On the other hand, the polysilicon film 3 for the active matrix portion can be formed.
Since the base 2 is made of the silicon nitride film 13, the cut-off current of the TFT for the active matrix portion can be sufficiently reduced as compared with the case where the base is a silicon oxide film.
【００１４】ちなみに、透明基板の上面に酸化シリコン
膜を形成し、この酸化シリコン膜の上面にＴＦＴを形成
した下地酸化シリコンＴＦＴと、透明基板の上面に窒化
シリコン膜を形成し、この窒化シリコン膜の上面にＴＦ
Ｔを形成した下地窒化シリコンＴＦＴとをそれぞれ数十
個用意し、オン電流およびカットオフ電流を測定したと
ころ、次のような結果が得られた。なお、ＴＦＴのチャ
ネルの幅および長さをそれぞれ１００μｍ、１０μｍと
した。まず、オン電流については、ゲート電圧が２０Ｖ
でドレイン電圧が５Ｖのときのドレイン電流を測定した
ところ、下地酸化シリコンＴＦＴのオン電流の平均値が
１６６μＡであり、下地窒化シリコンＴＦＴのオン電流
の平均値が１１９μＡであった。したがって、駆動回路
部用ポリシリコン膜３１の下地を酸化シリコン膜１２と
すると、駆動回路部用ＴＦＴのオン電流を下地が窒化シ
リコン膜の場合と比較して十分に高くすることができ
る。次に、カットオフ電流については、２種類の測定を
行った。第１のカットオフ電流については、ゲート電圧
が０Ｖでドレイン電圧が１０Ｖのときのドレイン電流を
測定したところ、下地酸化シリコンＴＦＴのオン電流の
平均値が４５９ｐＡであり、下地窒化シリコンＴＦＴの
オン電流の平均値が９３．１ｐＡであった。第２のカッ
トオフ電流については、ゲート電圧が０Ｖでドレイン電
圧が２０Ｖのときのドレイン電流を測定したところ、下
地酸化シリコンＴＦＴのオン電流の平均値が３０．８ｎ
Ａであり、下地窒化シリコンＴＦＴのオン電流の平均値
が３．２４ｎＡであった。したがって、アクティブマト
リクス部用ポリシリコン膜３２の下地を窒化シリコン膜
１３とすると、アクティブマトリクス部用ＴＦＴのカッ
トオフ電流を下地が酸化シリコン膜の場合と比較して十
分に低くすることができる。Incidentally, a silicon oxide film is formed on the upper surface of the transparent substrate, a base silicon oxide TFT in which a TFT is formed on the upper surface of the silicon oxide film, and a silicon nitride film is formed on the upper surface of the transparent substrate. TF on top of
Dozens of base silicon nitride TFTs each having T formed thereon were prepared, and the on-current and cut-off current were measured. The following results were obtained. The width and length of the channel of the TFT were 100 μm and 10 μm, respectively. First, as for the on-state current, the gate voltage is 20 V
When the drain current was measured when the drain voltage was 5 V, the average value of the on-state current of the underlying silicon oxide TFT was 166 μA, and the average value of the on-state current of the underlying silicon nitride TFT was 119 μA. Therefore, when the silicon oxide film 12 is used as the base of the polysilicon film 31 for the drive circuit portion, the on-state current of the TFT for the drive circuit portion can be sufficiently increased as compared with the case where the base is a silicon nitride film. Next, two types of measurements were performed for the cutoff current. Regarding the first cutoff current, when the drain current was measured when the gate voltage was 0 V and the drain voltage was 10 V, the average value of the on-state current of the underlying silicon oxide TFT was 459 pA, and the on-state current of the underlying silicon nitride TFT was 459 pA. Was 93.1 pA. As for the second cut-off current, when the drain current was measured when the gate voltage was 0 V and the drain voltage was 20 V, the average value of the ON current of the base silicon oxide TFT was 30.8 n
A, and the average value of the ON current of the base silicon nitride TFT was 3.24 nA. Therefore, when the silicon nitride film 13 is used as the base of the polysilicon film 32 for the active matrix part, the cut-off current of the TFT for the active matrix part can be sufficiently reduced as compared with the case where the base is a silicon oxide film.
【００１５】なお、上記実施例では、例えば図４に示す
ように、透明基板１１の上面に下地用酸化シリコン膜１
２を設け、この下地用酸化シリコン膜１２の上面の必要
な部分に下地用窒化シリコン膜１３を設け、そして下地
用酸化シリコン膜１２の上面に駆動回路部用ポリシリコ
ン膜３１を設けると共に、下地用窒化シリコン膜１３の
上面にアクティブマトリクス部用ポリシリコン膜３２を
設けているが、これに限定されるものではない。例え
ば、図７に示すように、透明基板１１の上面に下地用窒
化シリコン膜１３を設け、この下地用窒化シリコン膜１
３の上面の必要な部分に下地用酸化シリコン膜１２を設
け、そして下地用酸化シリコン膜１２の上面に駆動回路
部用ポリシリコン膜３１を設けると共に、下地用窒化シ
リコン膜１３の上面にアクティブマトリクス部用ポリシ
リコン膜３２を設けるようにしてもよい。また、図示し
ていないが、透明基板の上面の駆動回路部用ＴＦＴ形成
領域に下地用酸化シリコン膜を設けると共に、透明基板
の上面のアクティブマトリクス部用ＴＦＴ形成領域に下
地用窒化シリコン膜を設け、そして下地用酸化シリコン
膜の上面に駆動回路部用ポリシリコン膜を設けると共
に、下地用窒化シリコン膜の上面にアクティブマトリク
ス部用ポリシリコン膜を設けるようにしてもよい。ま
た、この発明は液晶表示パネルに限らず、ＴＦＴメモリ
やイメージセンサ等のマトリクスパネルに幅広く適用で
きるものである。In the above embodiment, for example, as shown in FIG.
2, an underlying silicon nitride film 13 is provided on a necessary portion of the upper surface of the underlying silicon oxide film 12, and a drive circuit portion polysilicon film 31 is provided on the upper surface of the underlying silicon oxide film 12. Although the active matrix portion polysilicon film 32 is provided on the upper surface of the silicon nitride film 13 for use, the present invention is not limited to this. For example, as shown in FIG. 7, an underlying silicon nitride film 13 is provided on an upper surface of a transparent substrate 11, and the underlying silicon nitride film 1 is provided.
3 is provided on a necessary portion of the upper surface of the substrate 3, a polysilicon film 31 for a drive circuit portion is provided on the upper surface of the silicon oxide film 12 for the base, and an active matrix is formed on the upper surface of the silicon nitride film 13 for the base. The component polysilicon film 32 may be provided. Although not shown, a base silicon oxide film is provided in the drive circuit portion TFT formation region on the upper surface of the transparent substrate, and a base silicon nitride film is provided in the active matrix portion TFT formation region on the upper surface of the transparent substrate. Then, a polysilicon film for the drive circuit portion may be provided on the upper surface of the silicon oxide film for the base, and a polysilicon film for the active matrix portion may be provided on the upper surface of the silicon nitride film for the base. The present invention is not limited to a liquid crystal display panel, but can be widely applied to a matrix panel such as a TFT memory or an image sensor.
【００１６】[0016]
【発明の効果】以上説明したように、この発明によれ
ば、アクティブマトリクス部用ＴＦＴの下地を窒化シリ
コン膜としているので、アクティブマトリクス部用ＴＦ
Ｔのカットオフ電流を下地が酸化シリコン膜の場合と比
較して十分に低くすることができ、しかも駆動回路部用
ＴＦＴの下地を酸化シリコン膜としているので、駆動回
路部用ＴＦＴのオン電流が低下しないようにすることが
でき、ひいては表示品質を向上させることができる。As described above, according to the present invention, the TFT for the active matrix portion is formed of a silicon nitride film, so that the TF for the active matrix portion is formed.
The cut-off current of T can be sufficiently reduced as compared with the case where the underlying layer is a silicon oxide film, and since the underlying layer of the driving circuit section TFT is a silicon oxide film, the ON current of the driving circuit section TFT is reduced. It can be prevented from lowering, and the display quality can be improved.
【図１】この発明の一実施例におけるアクティブマトリ
クスパネルの製造に際し、透明基板の上面に下地用酸化
シリコン膜および下地用窒化シリコン膜を形成した状態
の断面図。FIG. 1 is a cross-sectional view showing a state in which an underlying silicon oxide film and an underlying silicon nitride film are formed on an upper surface of a transparent substrate in manufacturing an active matrix panel in one embodiment of the present invention.
【図２】同アクティブマトリクスパネルの製造に際し、
不要な部分の下地用窒化シリコン膜を除去し、次いでア
モルファスシリコン膜を形成した後このアモルファスシ
リコン膜をレーザ照射によりポリシリコン膜化した状態
の断面図。FIG. 2 is a cross-sectional view of the manufacturing of the active matrix panel.
FIG. 4 is a cross-sectional view showing a state in which an unnecessary portion of the base silicon nitride film is removed, an amorphous silicon film is formed, and the amorphous silicon film is converted into a polysilicon film by laser irradiation.
【図３】同アクティブマトリクスパネルの製造に際し、
イオン注入マスク用のフォトレジスト膜を形成した後リ
ンイオン注入により不純物領域を形成した状態の断面
図。FIG. 3 is a cross-sectional view of the manufacturing of the active matrix panel.
FIG. 4 is a cross-sectional view showing a state in which a photoresist film for an ion implantation mask is formed and impurity regions are formed by phosphorus ion implantation.
【図４】同アクティブマトリクスパネルの製造に際し、
不要な部分のポリシリコン膜を除去して駆動回路部用ポ
リシリコン膜とアクティブマトリクス部用ポリシリコン
膜を形成した状態の断面図。FIG. 4 is a diagram showing the manufacturing process of the active matrix panel.
FIG. 4 is a cross-sectional view showing a state in which an unnecessary portion of the polysilicon film is removed to form a polysilicon film for a drive circuit portion and a polysilicon film for an active matrix portion.
【図５】同アクティブマトリクスパネルの製造に際し、
ゲート絶縁膜およびゲート電極を形成した状態の断面
図。FIG. 5 is a cross-sectional view of the production of the active matrix panel.
FIG. 4 is a cross-sectional view illustrating a state where a gate insulating film and a gate electrode are formed.
【図６】同アクティブマトリクスパネルの製造に際し、
層間絶縁膜、透明電極およびコンタクトホールを形成し
た後ソース・ドレイン電極を形成した状態の断面図。FIG. 6 is a cross-sectional view of the manufacturing of the active matrix panel.
FIG. 4 is a cross-sectional view showing a state where a source / drain electrode is formed after an interlayer insulating film, a transparent electrode, and a contact hole are formed.
【図７】この発明の他の実施例におけるアクティブマト
リクスパネルの図４同様の状態の断面図。FIG. 7 is a sectional view of an active matrix panel according to another embodiment of the present invention, in a state similar to FIG. 4;
【図８】従来のアクティブマトリクスパネルの回路構成
の一例を示す図。FIG. 8 is a diagram showing an example of a circuit configuration of a conventional active matrix panel.
１１ 透明基板 １２ 下地用酸化シリコン膜 １３ 下地用窒化シリコン膜 ２１ 駆動回路部用ポリシリコン膜 ２２ アクティブマトリクス部用ポリシリコン膜 DESCRIPTION OF SYMBOLS 11 Transparent substrate 12 Silicon oxide film for base 13 Silicon nitride film for base 21 Polysilicon film for drive circuit part 22 Polysilicon film for active matrix part
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) G02F 1/136 G02F 1/1345 G09F 9/30 G02F 1/1333 G02F 1/133 H01L 29/78 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) G02F 1/136 G02F 1/1345 G09F 9/30 G02F 1/1333 G02F 1/133 H01L 29/78
Claims (3)
回路部とを設けたアクティブマトリクスパネルにおい
て、前記アクティブマトリクス部をＴＦＴで構成すると
共にその下地を窒化シリコン膜とし、且つ前記駆動回路
部をＴＦＴで構成すると共にその下地を酸化シリコン膜
としたことを特徴とするアクティブマトリクスパネル。1. An active matrix panel having an active matrix portion and a drive circuit portion provided on a substrate, wherein the active matrix portion is formed of a TFT, a base thereof is formed of a silicon nitride film, and the drive circuit portion is formed of a TFT. An active matrix panel comprising a silicon oxide film as a base.
膜上に形成されていることを特徴とする請求項１記載の
アクティブマトリクスパネル。2. The active matrix panel according to claim 1, wherein said silicon nitride film is formed on said silicon oxide film.
膜上に形成されていることを特徴とする請求項１記載の
アクティブマトリクスパネル。3. The active matrix panel according to claim 1, wherein said silicon oxide film is formed on said silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16518591A JP3005918B2 (en) | 1991-06-11 | 1991-06-11 | Active matrix panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16518591A JP3005918B2 (en) | 1991-06-11 | 1991-06-11 | Active matrix panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04362616A JPH04362616A (en) | 1992-12-15 |
| JP3005918B2 true JP3005918B2 (en) | 2000-02-07 |
Family
ID=15807459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16518591A Expired - Lifetime JP3005918B2 (en) | 1991-06-11 | 1991-06-11 | Active matrix panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3005918B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5633176A (en) * | 1992-08-19 | 1997-05-27 | Seiko Instruments Inc. | Method of producing a semiconductor device for a light valve |
| JP3526058B2 (en) * | 1992-08-19 | 2004-05-10 | セイコーインスツルメンツ株式会社 | Semiconductor device for light valve |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| TW232751B (en) | 1992-10-09 | 1994-10-21 | Semiconductor Energy Res Co Ltd | Semiconductor device and method for forming the same |
| US6323071B1 (en) | 1992-12-04 | 2001-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a semiconductor device |
| US5403762A (en) | 1993-06-30 | 1995-04-04 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a TFT |
| JPH0792500A (en) * | 1993-06-29 | 1995-04-07 | Toshiba Corp | Semiconductor device |
| JPH07111334A (en) * | 1993-08-20 | 1995-04-25 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
| JPH07135323A (en) * | 1993-10-20 | 1995-05-23 | Semiconductor Energy Lab Co Ltd | Thin film semiconductor integrated circuit and manufacturing method thereof |
| EP1465257A1 (en) * | 1996-09-26 | 2004-10-06 | Seiko Epson Corporation | Display apparatus |
| JP4059292B2 (en) * | 1996-09-26 | 2008-03-12 | セイコーエプソン株式会社 | Display device |
-
1991
- 1991-06-11 JP JP16518591A patent/JP3005918B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04362616A (en) | 1992-12-15 |
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