[go: up one dir, main page]

JP2987405B2 - Method for manufacturing compound semiconductor device - Google Patents

Method for manufacturing compound semiconductor device

Info

Publication number
JP2987405B2
JP2987405B2 JP9873792A JP9873792A JP2987405B2 JP 2987405 B2 JP2987405 B2 JP 2987405B2 JP 9873792 A JP9873792 A JP 9873792A JP 9873792 A JP9873792 A JP 9873792A JP 2987405 B2 JP2987405 B2 JP 2987405B2
Authority
JP
Japan
Prior art keywords
substrate
temperature
compound semiconductor
thin film
schottky
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP9873792A
Other languages
Japanese (ja)
Other versions
JPH05275470A (en
Inventor
広信 澤渡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Japan Energy Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Energy Corp filed Critical Japan Energy Corp
Priority to JP9873792A priority Critical patent/JP2987405B2/en
Publication of JPH05275470A publication Critical patent/JPH05275470A/en
Application granted granted Critical
Publication of JP2987405B2 publication Critical patent/JP2987405B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、化合物半導体を基体と
する電子デバイスおよびその製造方法に関し、特にIn
P単結晶およびその三元、四元混晶の基板上にショット
キ・ダイオード、MESFET(MES型電界効果トラ
ンジスタ)等のショットキ電極を有する化合物半導体装
置を製造する場合に利用して最も効果のある技術に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device based on a compound semiconductor and a method of manufacturing the same.
The most effective technique to use when manufacturing a compound semiconductor device having a P single crystal and a Schottky electrode such as a Schottky diode and a MESFET (MES field effect transistor) on a ternary or quaternary mixed crystal substrate. About.

【0002】[0002]

【従来の技術】GaAs,InPなどの化合物半導体は
電子の移動度がSiよりも高く、また耐放射線性、耐熱
性などに優れ、Siに代わる高周波、高速の電子デバイ
スとしてその将来性が見込まれ、数多くの研究がなされ
てきたが、界面準位密度の小さな安定な酸化膜が得られ
ないためMOSFETはまだ実用化されるに至っていな
い。そこで、GaAsにおいては、ショットキ電極を用
いたMESFET(金属−半導体接合型FET)が実用
化され、ディスクリートの高周波FETや、小規模のデ
ィジタルICが実用化されている。しかし、GaAsM
ESFETはショットキ障壁電位が小さいために、論理
振幅が大きくとれず、大規模のディジタルICを高歩留
りで製造することができないという欠点を有している。
一方、InPは、電子飽和速度が大きく、また熱伝導率
がGaAsの1.5倍と大きいとともに、ブレークダウ
ン電圧も大きいことから超高速素子、特に高出力の超高
周波素子の材料として期待され、FETへの応用が検討
されている。
2. Description of the Related Art Compound semiconductors such as GaAs and InP have higher electron mobility than Si, and are excellent in radiation resistance and heat resistance, and are expected to be used as high-frequency, high-speed electronic devices replacing Si. Although many studies have been made, MOSFETs have not yet been put to practical use because a stable oxide film having a low interface state density cannot be obtained. Therefore, in GaAs, a MESFET (metal-semiconductor junction type FET) using a Schottky electrode has been put to practical use, and a discrete high-frequency FET and a small-scale digital IC have been put to practical use. However, GaAsM
Since the Schottky barrier potential is small, the ESFET has a drawback that a large logic amplitude cannot be obtained and a large-scale digital IC cannot be manufactured with a high yield.
On the other hand, InP is expected to be used as a material for ultra-high-speed devices, particularly high-power ultra-high-frequency devices, because it has a high electron saturation speed, a thermal conductivity as large as 1.5 times that of GaAs, and a large breakdown voltage. Application to FETs is under consideration.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、InP
はショットキ障壁高さが、GaAs(0.8eV)に比
べて小さい(0.3〜0.4eV)ため、逆方向リーク
電流が大きく、ゲート耐圧が小さいなど実用上大きな欠
点を有していた。そこで、InPでは、SiO2,Si
Nx,Al23,PNxのような絶縁膜をCVD法、プ
ラズマCVD法、光励起CVD法、スパッタ法、蒸着法
などにより低温堆積させるMISFETの研究が数多く
なされてきた。しかるに、低温堆積された絶縁膜を有す
るMISFETにあっては、絶縁膜と基板との界面準位
密度がかなり大きくなってしまうため、良好な特性を有
するMISFETが得られていない。
SUMMARY OF THE INVENTION However, InP
Since the Schottky barrier height is smaller (0.3 to 0.4 eV) than GaAs (0.8 eV), it has a large practical disadvantage such as a large reverse leakage current and a small gate breakdown voltage. Therefore, InP uses SiO 2 , Si
Nx, Al 2 O 3, a CVD method an insulating film such as PNx, plasma CVD, photo-excited CVD method, a sputtering method, have been many studies of the MISFET for low temperature deposition by vapor deposition or the like. However, in the case of a MISFET having an insulating film deposited at a low temperature, the interface state density between the insulating film and the substrate becomes considerably large, and a MISFET having good characteristics has not been obtained.

【0004】また、InP基板やInGaAs基板の上
に金属Cdを200Å積んでその上にショットキ電極を
形成することにより、ショットキ障壁高さの向上を図っ
たダイオードとMESFETに関する技術が、Lica
taらによって報告されている(American I
nstitute of Physics Appl.
Phys.Lett.58(8),25 Februa
ry 1991)。しかし、この技術によればショット
キ障壁高さをかなり高くすることができるものの、0.
55〜0.70eV程度である。
Further, a technique related to a diode and a MESFET in which a metal Cd is stacked on an InP substrate or an InGaAs substrate by 200 mm and a Schottky electrode is formed thereon to improve the Schottky barrier height is disclosed in Lica.
(American I.
nstate of Physics Appl.
Phys. Lett. 58 (8), 25 February
ry 1991). However, according to this technique, although the height of the Schottky barrier can be considerably increased, the height of the Schottky barrier can be increased.
It is about 55 to 0.70 eV.

【0005】この発明は上記のような背景の下になされ
たもので、その目的とするところはIII−V族化合物半
導体基板において、逆方向リーク電流が小さくゲート耐
圧の高いショットキゲート電極を有する特性の良好なM
ESFETおよびショットキ・ダイオードの製造方法を
提供することにある。この発明の他の目的は、ショット
キ障壁高さがGaAsに匹敵するショットキゲート電極
を有するInP MESFETおよびInP ショット
キ・ダイオードの製造方法を提供することにある。
The present invention has been made in view of the above background, and has as its object to provide a III-V compound semiconductor substrate having a Schottky gate electrode having a small reverse leakage current and a high gate breakdown voltage. Good M
An object of the present invention is to provide a method for manufacturing an ESFET and a Schottky diode. It is another object of the present invention to provide a method of manufacturing an InP MESFET and an InP Schottky diode having a Schottky gate electrode having a Schottky barrier height comparable to that of GaAs.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するた
め、本発明は、例えばInPのようなIII−V族化合物
半導体層がその表面にエピタキシャル成長されてなる基
板、またはIII−V族化合物半導体基板上に、基板設置
部の温度を250〜450℃としかつ原料設置部の温度
よりも基板設置部の温度の方が0.1℃以上10℃以下
高くなるように温度を制御しながら、キャリアガスを原
料設置部側から基板設置部側へ流して原料のCdを輸送
して基板上にCd薄膜を10原子層以下に被着させた
後、上記Cd薄膜を酸化させ、このCd酸化物層の上に
ショットキ電極を形成するようにしたものである。
In order to achieve the above object, the present invention relates to a substrate having a group III-V compound semiconductor layer such as InP epitaxially grown on its surface, or a group III-V compound semiconductor substrate. The carrier gas is controlled such that the temperature of the substrate installation section is 250 to 450 ° C. and the temperature of the substrate installation section is higher than the temperature of the raw material installation section by 0.1 ° C. to 10 ° C. Is flowed from the raw material installation part side to the substrate installation part side to transport Cd as a raw material and deposit a Cd thin film on the substrate in a thickness of 10 atomic layers or less, and then oxidize the Cd thin film to form a Cd oxide layer. A Schottky electrode is formed thereon.

【0007】[0007]

【作用】上記した手段によれば、半導体基板とショット
キ電極との間にCd酸化物層が介在されそれが10原子
層以下と薄いため、基板と酸化物層との間に働く弾性歪
によって界面での不対結合の発生が防止され、ショット
キ障壁高さが充分に高いショットキ電極が得られ、これ
によって、逆方向リーク電流が小さく耐圧の高いショッ
トキゲート電極を有する特性の良好なMESFETおよ
びショットキ・ダイオードを製造することが可能とな
る。10原子層を超える厚みのCd酸化物層では、その
弾性限界を超えてしまい、界面へ応力が働き、界面で不
対結合が生じて欠陥準位ができてしまう。
According to the above-mentioned means, the Cd oxide layer is interposed between the semiconductor substrate and the Schottky electrode and is as thin as 10 atomic layers or less. And a Schottky electrode having a sufficiently high Schottky barrier height is obtained, whereby a MESFET and a Schottky electrode having good characteristics having a Schottky gate electrode having a small reverse leakage current and a high withstand voltage are obtained. A diode can be manufactured. With a Cd oxide layer having a thickness exceeding 10 atomic layers, its elastic limit is exceeded, stress acts on the interface, and unpaired bonding occurs at the interface, resulting in a defect level.

【0008】また、CVD法、プラズマCVD法、光励
起CVD法、スパッタ法、蒸着法などにより絶縁膜を強
制的に堆積させる従来の方法では、基板表面に格子乱れ
による欠陥を生じさせるため、界面準位密度が高い絶縁
膜しか形成できなかったが、上記した手段によれば、C
dの薄膜を被着させ、このCd薄膜を酸化させるように
したので、表面欠陥を生じさせることなく10原子層以
下の厚みの酸化物層を形成し、界面準位密度が低くかつ
ショットキ障壁高さが充分に高いショットキ電極を得る
ことができる。さらに、Cd薄膜の被着方法として、原
料設置部の温度よりも基板設置部の温度が0.1℃以上
10℃以下高くなるように温度を制御してCd薄膜を被
着するようにしたので、Cdは被着時間に依存せず高々
2〜3原子層、通常は1原子層が基板に化学吸着され、
それ以上は被着されず、安定して10原子層以下のCd
薄膜を被着させることできる。また、基板への密着力も
強くなる。また、基板設置部の温度を250〜450℃
とすることでショットキー障壁高さを従来より高くする
ことができる。
In a conventional method of forcibly depositing an insulating film by a CVD method, a plasma CVD method, a photo-excited CVD method, a sputtering method, a vapor deposition method, or the like, a defect due to lattice disorder is generated on a substrate surface. Although only an insulating film having a high potential density could be formed, according to the means described above, C
Since a thin film of d is deposited and this Cd thin film is oxidized, an oxide layer having a thickness of 10 atomic layers or less is formed without causing surface defects, and the interface state density is low and the Schottky barrier height is low. It is possible to obtain a Schottky electrode having a sufficiently high resistance. Further, as a method of depositing a Cd thin film, the temperature is controlled so that the temperature of the substrate installation portion is higher than the temperature of the raw material installation portion by 0.1 ° C. or more and 10 ° C. or less, so that the Cd thin film is applied. , Cd is chemisorbed on the substrate at most 2-3 atomic layers, usually 1 atomic layer, independent of the deposition time,
Cd of 10 atomic layer or less is not stably deposited
A thin film can be applied. Further, the adhesion to the substrate is also increased. Further, the temperature of the substrate installation part is set to 250 to 450 ° C.
By doing so, the height of the Schottky barrier can be made higher than before.

【0009】[0009]

【実施例】以下、InP基板上にショットキ電極を形成
する場合を例にとって説明する。 (実施例1)まず、裏面にAuGe/Ni/Au等から
なるオーミック電極を形成したノンドープn型InP基
板(N=5×1015cm-3)を用意する。次に、上記基
板表面をエッチングした後、図1に示すような装置を用
いてCd薄膜を形成する。図1において、1は円筒状の
石英反応管で、この石英反応管1の一端(図では左端)
にはガス導入管2が、また石英反応管1の他端(図では
右端)にはガス排気管3が接続されている。上記ガス導
入管2の途中には、マスフローコントローラ4が設けら
れ、石英反応管1内に流すガスの流量を調整できるよう
に構成されているとともに、石英反応管1の外側には、
ヒーター5a,5bが配置され、反応管内の温度を制御
できるように構成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a case where a Schottky electrode is formed on an InP substrate will be described as an example. Example 1 First, a non-doped n-type InP substrate (N = 5 × 10 15 cm −3 ) having an ohmic electrode made of AuGe / Ni / Au or the like on its back surface is prepared. Next, after etching the substrate surface, a Cd thin film is formed using an apparatus as shown in FIG. In FIG. 1, reference numeral 1 denotes a cylindrical quartz reaction tube, and one end of the quartz reaction tube 1 (the left end in the figure).
Is connected to a gas introduction pipe 2, and the other end (right end in the figure) of the quartz reaction pipe 1 is connected to a gas exhaust pipe 3. A mass flow controller 4 is provided in the middle of the gas introduction pipe 2 so as to be able to adjust the flow rate of the gas flowing into the quartz reaction tube 1.
The heaters 5a and 5b are arranged so that the temperature in the reaction tube can be controlled.

【0010】この実施例では、上記石英反応管1の上流
側に原料としてのカドミウム6を入れたボート7を設置
し、石英反応管1の下流側にn型InP基板8を設置す
る。それから、上記ヒーター5a,5bに給電して、基
板設置部の温度T2が上記原料ボート部の温度T1より
も0.1℃以上10℃以下高くなるように制御する。ま
た、ガス導入管2より水素もしくはアルゴンのような不
活性ガスを供給し、ボート7内のCdの蒸気を下流側へ
運んで、InP基板8上に化学吸着させて、10原子層
以下のCd薄膜を成長させる。
In this embodiment, a boat 7 containing cadmium 6 as a raw material is installed upstream of the quartz reaction tube 1 and an n-type InP substrate 8 is installed downstream of the quartz reaction tube 1. Then, power is supplied to the heaters 5a and 5b so as to control the temperature T2 of the substrate installation portion to be higher than the temperature T1 of the raw material boat portion by 0.1 ° C. or more and 10 ° C. or less. In addition, an inert gas such as hydrogen or argon is supplied from the gas introduction pipe 2, and the vapor of Cd in the boat 7 is carried to the downstream side, and is chemically adsorbed on the InP substrate 8, and Cd of 10 atomic layers or less is formed. Grow a thin film.

【0011】このように、基板設置部の温度T2が上記
原料ボート部の温度T1よりも0.1℃以上10℃以下
高くなるように制御し、Cdの蒸気をキャリアガスで基
板側へ運んでやることにより、InP基板8上に10原
子層以下のCd薄膜を成長させることができる。すなわ
ち、基板設置部の温度T2が上記原料ボート部の温度T
1よりも低い(T2<T1)と、基板上への原料Cdの
堆積反応が一方的に進行するため、数原子層単位での厚
みの制御が行なえないとともに、温度T2とT1との差
が0.1℃未満であると、温度揺らぎによって堆積の速
度にむらが生じるため数原子層単位での厚みの制御が行
なえない。また、温度T2とT1との差が10℃を越え
ると、基板上へのCdの堆積反応が進行しない。
As described above, the temperature T2 of the substrate setting part is controlled so as to be higher than the temperature T1 of the raw material boat part by 0.1 ° C. or more and 10 ° C. or less, and the Cd vapor is carried to the substrate side by the carrier gas. By doing so, a Cd thin film having 10 atomic layers or less can be grown on the InP substrate 8. That is, the temperature T2 of the substrate setting part is equal to the temperature T of the raw material boat part.
When the temperature is lower than 1 (T2 <T1), the deposition reaction of the raw material Cd on the substrate proceeds unilaterally, so that the thickness cannot be controlled in a unit of several atomic layers, and the difference between the temperatures T2 and T1 is reduced. When the temperature is lower than 0.1 ° C., the fluctuation of temperature causes unevenness in the deposition rate, so that the thickness cannot be controlled in units of several atomic layers. Further, if the difference between the temperatures T2 and T1 exceeds 10 ° C., the deposition reaction of Cd on the substrate does not proceed.

【0012】一方、基板上への数原子層のCd薄膜形成
後は、上記ガス導入管2からの導入ガスを酸素に切換え
て、同一の温度条件下でInP基板8上のCd薄膜を酸
化させてCd酸化物層12を形成した後、電子ビーム蒸
着装置等により上記Cd酸化物層12上にショットキ電
極13を形成する(図2参照)。14は予め形成してお
いたオーミック電極である。
On the other hand, after forming a Cd thin film of several atomic layers on the substrate, the gas introduced from the gas introduction pipe 2 is switched to oxygen, and the Cd thin film on the InP substrate 8 is oxidized under the same temperature conditions. After the formation of the Cd oxide layer 12, a Schottky electrode 13 is formed on the Cd oxide layer 12 by an electron beam evaporation apparatus or the like (see FIG. 2). 14 is an ohmic electrode formed in advance.

【0013】一例として、基板設置部の温度T2と原料
ボート部の温度T1との温度差ΔTを2℃(ただし、T
2>T1)として、InP基板の表面上に、Cdを10
原子層以下となるように吸着させてから、これを酸化さ
せた後、このCd酸化物層12上に金電極13を150
0Å形成して、図2に示すようなショットキダイオード
を作製した。基板設置部の温度T2を200〜500℃
の範囲で変化させて得られたデバイスについて、電極1
3,14間に印加する電圧を変えながら、電圧−電流特
性を測定した。その結果を図3に示す。同図より、基板
設置部の温度T2が250〜450℃の範囲のときにシ
ョットキ障壁は一般のInPショットキ電極の0.5e
Vを上回り、最高は0.80eVであることがわかる。
また、逆方向電圧2Vでのリーク電流は1×10-6A/
cm2で、耐圧は約90Vと良好であった。
As an example, the temperature difference ΔT between the temperature T2 of the substrate installation part and the temperature T1 of the raw material boat part is 2 ° C. (where T
2> T1), Cd is 10 on the surface of the InP substrate.
After being adsorbed so as to have an atomic layer or less and then being oxidized, a gold electrode 13 is placed on the Cd oxide layer 12 by 150 nm.
0 ° was formed to produce a Schottky diode as shown in FIG. The temperature T2 of the substrate installation part is 200 to 500 ° C.
About the device obtained by changing in the range of
The voltage-current characteristics were measured while changing the voltage applied between 3 and 14. The result is shown in FIG. As shown in the figure, when the temperature T2 of the substrate installation part is in the range of 250 to 450 ° C., the Schottky barrier is 0.5 e of the general InP Schottky electrode.
V, and the maximum is 0.80 eV.
Also, the leakage current in the reverse direction voltage 2V is 1 × 10- 6 A /
cm 2 , the withstand voltage was as good as about 90V.

【0014】さらに、上記のようにして基板表面にCd
薄膜を吸着させて酸化させたCd酸化膜の形成後の基板
表面を、オージェ(Auger)電子分光装置によって
測定したところ、数原子層のCd酸化膜が形成されてい
ることが分かった。また、上記実施例では、一例として
InP基板上へのショットキ電極の形成を例にとって説
明したが、この発明はInGaAs基板その他III−V
族化合物半導体基板または表面にIII−V族化合物半導
体層がエピタキシャル成長されてなる基板上にショット
キ電極を形成する場合に適用することができる。
Further, Cd is applied to the substrate surface as described above.
When the surface of the substrate after the formation of the Cd oxide film formed by adsorbing and oxidizing the thin film was measured by an Auger electron spectrometer, it was found that a Cd oxide film of several atomic layers was formed. Further, in the above embodiment, the formation of the Schottky electrode on the InP substrate has been described as an example. However, the present invention is not limited to the InGaAs substrate and other III-V substrates.
The present invention can be applied to a case where a Schottky electrode is formed on a group III compound semiconductor substrate or a substrate on which a III-V group compound semiconductor layer is epitaxially grown.

【0015】[0015]

【発明の効果】以上説明したように本発明は、その表面
にIII−V族化合物半導体層がエピタキシャル成長され
てなる基板またはIII−V族化合物半導体基板上に、基
板設置部の温度を250〜450℃としかつ原料設置部
の温度よりも基板設置部の温度の方が0.1℃以上10
℃以下高くなるように温度を制御しながら、キャリアガ
スを原料設置部側から基板設置部側へ流して原料のCd
を輸送して基板上にCd薄膜を10原子層以下に被着さ
せた後、上記Cd薄膜を酸化させ、このCd酸化物層の
上にショットキ電極を形成するようにしたので、半導体
基板とショットキ電極との間に薄いCd酸化物層が介在
されそれが10原子層以下と薄いため、基板とCd酸化
物層との間に働く弾性歪によって界面での不対結合が発
生するのが防止され、ショットキ障壁高さが充分に高い
ショットキ電極が得られ、これによって、逆方向リーク
電流が小さく耐圧の高いショットキゲート電極を有する
特性の良好なMESFETおよびショットキ・ダイオー
ドを製造することが可能となる。また、化合物半導体基
板表面にCdの薄膜を被着させ、このCd薄膜を酸化さ
せるようにしたので、表面欠陥を生じさせることなく1
0原子層以下の厚みのCd酸化物層を形成し、界面準位
密度が低くかつショットキ障壁高さが充分に高いショッ
トキ電極を得ることができるという効果がある。
As described above, according to the present invention, the temperature of the substrate mounting portion is set at 250 to 450 on a substrate having a III-V compound semiconductor layer epitaxially grown on its surface or a III-V compound semiconductor substrate. ° C and the temperature of the substrate installation part is 0.1 ° C or more than that of the raw material installation part.
While controlling the temperature so as to be higher than ℃, the carrier gas flows from the raw material installation part side to the substrate installation part side, and the Cd of the raw material is changed.
Was transported to deposit a Cd thin film on the substrate in a thickness of 10 atomic layers or less, and then the Cd thin film was oxidized to form a Schottky electrode on the Cd oxide layer. Since a thin Cd oxide layer is interposed between the electrodes and is as thin as 10 atomic layers or less, the occurrence of unpaired coupling at the interface due to elastic strain acting between the substrate and the Cd oxide layer is prevented. Thus, a Schottky electrode having a sufficiently high Schottky barrier height can be obtained, thereby making it possible to manufacture a MESFET and a Schottky diode having good characteristics having a Schottky gate electrode having a small reverse leakage current and a high withstand voltage. Further, since a Cd thin film is deposited on the surface of the compound semiconductor substrate and the Cd thin film is oxidized, the Cd thin film can be oxidized without causing surface defects.
By forming a Cd oxide layer having a thickness of 0 atomic layer or less, a Schottky electrode having a low interface state density and a sufficiently high Schottky barrier height can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明方法におけるCd薄膜形成に使用して好
適な装置の一例を示す断面正面図である。
FIG. 1 is a sectional front view showing an example of an apparatus suitable for use in forming a Cd thin film in the method of the present invention.

【図2】実施例において製造したデバイスの構造を示す
断面図である。
FIG. 2 is a cross-sectional view showing a structure of a device manufactured in an example.

【図3】実施例の方法により製造したデバイス(ダイオ
ード)のショットキ障壁高さの測定値を酸化温度との関
係で示すグラフである。
FIG. 3 is a graph showing a measured value of a Schottky barrier height of a device (diode) manufactured by a method of an example in relation to an oxidation temperature.

【符号の説明】[Explanation of symbols]

1 石英反応管 2 ガス導入管 3 ガス排気管 4 マスフローコントローラ 5a,5b ヒーター 6 Cd原料 7 ボート 8 成長用基板(InP基板) 12 Cd酸化物層 13 ショットキ電極(金電極) 14 オーミック電極 DESCRIPTION OF SYMBOLS 1 Quartz reaction tube 2 Gas introduction tube 3 Gas exhaust tube 4 Mass flow controller 5a, 5b Heater 6 Cd raw material 7 Boat 8 Growth substrate (InP substrate) 12 Cd oxide layer 13 Schottky electrode (gold electrode) 14 Ohmic electrode

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/338 C23C 16/46 H01L 21/205 H01L 29/812 H01L 29/872 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/338 C23C 16/46 H01L 21/205 H01L 29/812 H01L 29/872

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 その表面にIII−V族化合物半導体層が
エピタキシャル成長されてなる基板またはIII−V族化
合物半導体基板上に、基板設置部の温度を250〜45
0℃としかつ原料設置部の温度よりも基板設置部の温度
の方が0.1℃以上10℃以下高くなるように温度を制
御しながら、キャリアガスを原料設置部側から基板設置
部側へ流して原料のCd(カドミウム)を輸送し基板上
にCd薄膜を10原子層以下に被着させた後、上記Cd
薄膜を酸化させ、このCd酸化物層の上にショットキ電
極を形成するようにしたことを特徴とする化合物半導体
装置の製造方法。
1. A substrate having a III-V group compound semiconductor layer epitaxially grown on its surface or a III-V group compound semiconductor substrate, wherein the temperature of the substrate setting part is 250-45.
While controlling the temperature so that the temperature is 0 ° C. and the temperature of the substrate installation portion is higher than the temperature of the material installation portion by 0.1 ° C. or more and 10 ° C. or less, the carrier gas is transferred from the material installation portion side to the substrate installation portion side. Cd (cadmium) as a raw material is transported and a Cd thin film is deposited on the substrate in a thickness of 10 atomic layers or less.
A method for manufacturing a compound semiconductor device, comprising oxidizing a thin film and forming a Schottky electrode on the Cd oxide layer.
JP9873792A 1992-03-24 1992-03-24 Method for manufacturing compound semiconductor device Expired - Lifetime JP2987405B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9873792A JP2987405B2 (en) 1992-03-24 1992-03-24 Method for manufacturing compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9873792A JP2987405B2 (en) 1992-03-24 1992-03-24 Method for manufacturing compound semiconductor device

Publications (2)

Publication Number Publication Date
JPH05275470A JPH05275470A (en) 1993-10-22
JP2987405B2 true JP2987405B2 (en) 1999-12-06

Family

ID=14227819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9873792A Expired - Lifetime JP2987405B2 (en) 1992-03-24 1992-03-24 Method for manufacturing compound semiconductor device

Country Status (1)

Country Link
JP (1) JP2987405B2 (en)

Also Published As

Publication number Publication date
JPH05275470A (en) 1993-10-22

Similar Documents

Publication Publication Date Title
US4897710A (en) Semiconductor device
US5229625A (en) Schottky barrier gate type field effect transistor
JP3439111B2 (en) High mobility transistor
JPH01196873A (en) silicon carbide semiconductor device
US5285089A (en) Diamond and silicon carbide heterojunction bipolar transistor
JP2750330B2 (en) Method for manufacturing compound semiconductor device
JPH0786311A (en) Highly oriented diamond thin film field effect transistor
JP2987405B2 (en) Method for manufacturing compound semiconductor device
JP3934822B2 (en) Schottky diode and manufacturing method thereof
JPH05275468A (en) Manufacture of compound semiconductor device
CN116130336A (en) A two-dimensional electron gas heterojunction structure based on nitride material and nitrogen-terminated diamond and its preparation method
JP2000174261A (en) Compound semiconductor device
JPH05275469A (en) Method for manufacturing compound semiconductor device
CN113871473A (en) Device and method for controlling van der Waals epitaxy and remote epitaxy growth modes
JPH05275467A (en) Compound semiconductor device and manufacturing method thereof
US20060060132A1 (en) Production method for thin-film crystal wafer, semiconductor device using it and production method therefor
JPH05275466A (en) Manufacture of compound semiconductor device
US4811070A (en) Heterojunction bipolar transistor with inversion layer base
JP3326378B2 (en) Semiconductor device
Shao et al. Low resistance ohmic contacts to p-Ge/sub 1-x/C x on Si
JP3275483B2 (en) Method for manufacturing epitaxial wafer for field effect transistor
JP3768348B2 (en) Semiconductor device and manufacturing method thereof
JPH07111348A (en) Gunn diode
JPH0888235A (en) FET using hydrogen-terminated homoepitaxial diamond and manufacturing method thereof
JP3338911B2 (en) Semiconductor device and manufacturing method thereof