JP2750330B2 - Method for manufacturing compound semiconductor device - Google Patents
Method for manufacturing compound semiconductor deviceInfo
- Publication number
- JP2750330B2 JP2750330B2 JP4098733A JP9873392A JP2750330B2 JP 2750330 B2 JP2750330 B2 JP 2750330B2 JP 4098733 A JP4098733 A JP 4098733A JP 9873392 A JP9873392 A JP 9873392A JP 2750330 B2 JP2750330 B2 JP 2750330B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- metal
- compound semiconductor
- temperature
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 150000001875 compounds Chemical class 0.000 title claims description 16
- 238000000034 method Methods 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 56
- 229910052751 metal Inorganic materials 0.000 claims description 38
- 239000002184 metal Substances 0.000 claims description 38
- 238000009434 installation Methods 0.000 claims description 21
- 239000010409 thin film Substances 0.000 claims description 21
- 229910044991 metal oxide Inorganic materials 0.000 claims description 14
- 150000004706 metal oxides Chemical class 0.000 claims description 14
- 239000002994 raw material Substances 0.000 claims description 14
- 239000012159 carrier gas Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 9
- 238000000151 deposition Methods 0.000 description 9
- 239000007789 gas Substances 0.000 description 9
- 230000008021 deposition Effects 0.000 description 8
- 239000010453 quartz Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000010408 film Substances 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- -1 Si Nx Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- 229910052793 cadmium Inorganic materials 0.000 description 2
- 229910052791 calcium Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- LPVJWXJBZPCDLM-HUWNQDJBSA-N 7-boat Chemical compound O([C@H]1\C(C)=C/[C@]23O[C@@]2(C([C@H](C)[C@@H](OC(C)=O)[C@H]2[C@H](C2(C)C)[C@@H]1OC(C)=O)=O)C[C@H]([C@H]3OC(C)=O)C)C(=O)C1=CC=CC=C1 LPVJWXJBZPCDLM-HUWNQDJBSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28581—Deposition of Schottky electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は、化合物半導体を基体と
する電子デバイスおよびその製造方法に関し、特にＩｎ
Ｐ単結晶およびその三元、四元混晶の基板上にショット
キ・ダイオード、ＭＥＳＦＥＴ（ＭＥＳ型電界効果トラ
ンジスタ）等のショットキ電極を有する化合物半導体装
置を製造する場合に利用して最も効果のある技術に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device based on a compound semiconductor and a method of manufacturing the same.
The most effective technique to use when manufacturing a compound semiconductor device having a P single crystal and a Schottky electrode such as a Schottky diode and a MESFET (MES field effect transistor) on a ternary or quaternary mixed crystal substrate. About.
【０００２】[0002]
【従来の技術】ＧａＡｓ，ＩｎＰなどの化合物半導体は
電子の移動度がＳｉよりも高く、また耐放射線性、耐熱
性などに優れ、Ｓｉに代わる高周波、高速の電子デバイ
スとしてその将来性が見込まれ、数多くの研究がなされ
てきたが、界面準位密度の小さな安定な酸化膜が得られ
ないためＭＯＳＦＥＴはまだ実用化されるに至っていな
い。そこで、ＧａＡｓにおいては、ショットキ電極を用
いたＭＥＳＦＥＴ（金属−半導体接合型ＦＥＴ）が実用
化され、ディスクリートの高周波ＦＥＴや、小規模のデ
ィジタルＩＣが実用化されている。しかし、ＧａＡｓＭ
ＥＳＦＥＴはショットキ障壁電位が小さいために、論理
振幅が大きくとれず、大規模のディジタルＩＣを高歩留
りで製造することができないという欠点を有している。
一方、ＩｎＰは、電子飽和速度が大きく、また熱伝導率
がＧａＡｓの１．５倍と大きいとともに、ブレークダウ
ン電圧も大きいことから超高速素子、特に高出力の超高
周波素子の材料として期待され、ＦＥＴへの応用が検討
されている。2. Description of the Related Art Compound semiconductors such as GaAs and InP have higher electron mobility than Si, and are excellent in radiation resistance and heat resistance, and are expected to be used as high-frequency, high-speed electronic devices replacing Si. Although many studies have been made, MOSFETs have not yet been put to practical use because a stable oxide film having a low interface state density cannot be obtained. Therefore, in GaAs, a MESFET (metal-semiconductor junction type FET) using a Schottky electrode has been put to practical use, and a discrete high-frequency FET and a small-scale digital IC have been put to practical use. However, GaAsM
Since the Schottky barrier potential is small, the ESFET has a drawback that a large logic amplitude cannot be obtained and a large-scale digital IC cannot be manufactured with a high yield.
On the other hand, InP is expected to be used as a material for ultra-high-speed devices, particularly high-power ultra-high-frequency devices, because it has a high electron saturation speed, a thermal conductivity 1.5 times that of GaAs, and a large breakdown voltage. Application to FETs is under consideration.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、ＩｎＰ
はショットキ障壁高さが、ＧａＡｓ（０．８ｅＶ）に比
べて小さい（０．３〜０．４ｅＶ）ため、逆方向リーク
電流が大きく、ゲート耐圧が小さいなど実用上大きな欠
点を有していた。そこで、ＩｎＰでは、ＳｉＯ2，Ｓｉ
Ｎｘ，Ａｌ2Ｏ3，ＰＮｘのような絶縁膜をＣＶＤ法、プ
ラズマＣＶＤ法、光励起ＣＶＤ法、スパッタ法、蒸着法
などにより低温堆積させるＭＩＳＦＥＴの研究が数多く
なされてきた。しかるに、低温堆積された絶縁膜を有す
るＭＩＳＦＥＴにあっては、絶縁膜と基板との界面準位
密度がかなり大きくなってしまうため、良好な特性を有
するＭＩＳＦＥＴが得られていない。SUMMARY OF THE INVENTION However, InP
Since the Schottky barrier height is smaller (0.3 to 0.4 eV) than GaAs (0.8 eV), it has a large practical disadvantage such as a large reverse leakage current and a small gate breakdown voltage. Therefore, InP uses SiO 2 , Si
Nx, Al 2 O 3, a CVD method an insulating film such as PNx, plasma CVD, photo-excited CVD method, a sputtering method, have been many studies of the MISFET for low temperature deposition by vapor deposition or the like. However, in the case of a MISFET having an insulating film deposited at a low temperature, the interface state density between the insulating film and the substrate becomes considerably large, and a MISFET having good characteristics has not been obtained.
【０００４】また、ＩｎＰ基板やＩｎＧａＡｓ基板の上
に金属カドミウムを２００Å積んでその上にショットキ
電極を形成することにより、ショットキ障壁高さの向上
を図ったダイオードとＭＥＳＦＥＴに関する技術が、Ｌ
ｉｃａｔａらによって報告されている（Ａｍｅｒｉｃａ
ｎ Ｉｎｓｔｉｔｕｔｅ ｏｆ Ｐｈｙｓｉｃｓ Ａｐ
ｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．５８（８），２５ Ｆｅｂ
ｒｕａｒｙ １９９１）。しかし、この技術によればシ
ョットキ障壁高さをかなり高くすることができるもの
の、０．５５〜０．７０ｅＶ程度である。Further, a technology relating to a diode and a MESFET in which a metal cadmium is deposited on an InP substrate or an InGaAs substrate by 200 mm and a Schottky electrode is formed thereon to improve the Schottky barrier height is disclosed in L.
icata et al. (America
n Institute of Physics Ap
pl. Phys. Lett. 58 (8), 25 Feb
rury 1991). However, according to this technique, although the Schottky barrier height can be considerably increased, it is about 0.55 to 0.70 eV.
【０００５】この発明は上記のような背景の下になされ
たもので、その目的とするところはIII−Ｖ族化合物半
導体基板において、逆方向リーク電流が小さくゲート耐
圧の高いショットキゲート電極を有する特性の良好なＭ
ＥＳＦＥＴおよびショットキ・ダイオードとその製造方
法を提供することにある。この発明の他の目的は、ショ
ットキ障壁高さがＧａＡｓに匹敵するショットキゲート
電極を有するＩｎＰ ＭＥＳＦＥＴおよびＩｎＰ ショ
ットキ・ダイオードとその製造方法を提供することにあ
る。The present invention has been made in view of the above background, and has as its object to provide a III-V compound semiconductor substrate having a Schottky gate electrode having a small reverse leakage current and a high gate breakdown voltage. Good M
An object of the present invention is to provide an ESFET, a Schottky diode and a method of manufacturing the same. Another object of the present invention is to provide an InP MESFET and an InP Schottky diode having a Schottky gate electrode having a Schottky barrier height comparable to that of GaAs, and a method of manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、金属原料設置部および基板設置部を加熱
しながら、キャリアガスを金属原料設置部側から基板設
置部側へ流して、例えばＩｎＰのようなＩＩＩ−Ｖ族化
合物半導体層がその表面にエピタキシャル成長されてな
る基板またはＩＩＩ−Ｖ族化合物半導体基板上に、安定
な酸化物を生成可能な金属の薄膜を１０原子層以下に被
着させ、この金属薄膜を酸化させた後、この金属酸化物
層の上にショットキ電極を形成するようにしたものであ
る。また、好ましくは、金属原料設置部の温度よりも基
板設置部の温度の方が０．１℃以上１０℃以下高くなる
ように温度を制御する。また、金属原料としては、Ｂ
ｅ，Ｍｇ，Ａｌ，Ｓｉ，Ｃａ，Ｔｉ，Ｆｅ，Ｃｏ，Ｎ
ｉ，Ｃｕ，Ｚｎ，Ｇａ，Ｇｅ，Ａｓ，Ｚｒ，Ａｇ，Ｃ
ｄ，Ｓｎ，Ｓｂ，Ｔｅ，Ｃｓ，Ｐｂ，ＢｉもしくはＣｅ
を用いる。In order to achieve the above object, the present invention provides a method for heating a metal source installation section and a substrate installation section while flowing a carrier gas from the metal source installation section to the substrate installation section. For example, a thin film of a metal capable of forming a stable oxide is formed on a substrate having a group III-V compound semiconductor layer such as InP epitaxially grown on its surface or a group III-V compound semiconductor substrate in a thickness of 10 atomic layers or less. After the metal thin film is oxidized, a Schottky electrode is formed on the metal oxide layer. Preferably, the temperature is controlled such that the temperature of the substrate installation part is higher than the temperature of the metal raw material installation part by 0.1 ° C. or more and 10 ° C. or less. In addition, as a metal raw material, B
e, Mg, Al, Si, Ca, Ti, Fe, Co, N
i, Cu, Zn, Ga, Ge, As, Zr, Ag, C
d, Sn, Sb, Te, Cs, Pb, Bi or Ce
Is used.
【０００７】[0007]
【作用】上記した手段によれば、半導体基板とショット
キ電極との間に金属酸化物層が介在されそれが１０原子
層以下と薄いため、基板と金属酸化物層との間に働く弾
性歪によって界面での不対結合の発生が防止され、ショ
ットキ障壁高さが充分に高いショットキ電極が得られ、
これによって、逆方向リーク電流が小さく耐圧の高いシ
ョットキゲート電極を有する特性の良好なＭＥＳＦＥＴ
およびショットキ・ダイオードを製造することが可能と
なる。１０原子層を超える厚みの金属酸化物層では、そ
の弾性限界を超えてしまい、界面へ応力が働き、界面で
不対結合が生じて欠陥準位ができてしまう。According to the above means, since the metal oxide layer is interposed between the semiconductor substrate and the Schottky electrode and is as thin as 10 atomic layers or less, the elastic strain acting between the substrate and the metal oxide layer causes The occurrence of unpaired bonding at the interface is prevented, and a Schottky electrode with a sufficiently high Schottky barrier height is obtained.
As a result, a MESFET with good characteristics having a Schottky gate electrode with a small reverse leakage current and a high withstand voltage
And a Schottky diode can be manufactured. In a metal oxide layer having a thickness exceeding 10 atomic layers, its elastic limit is exceeded, stress acts on the interface, and unpaired bonding occurs at the interface, resulting in a defect level.
【０００８】１０原子層以下の金属薄膜の被着方法とし
ては、気相輸送法、分子線エピタキシャル法、真空蒸着
法及び有機金属気相成長法などが考えられるが、１０原
子層以下という非常に薄い金属薄膜を被着するには、被
着速度を遅くしたり、被着時間の制御精度を上げる必要
がある。被着速度を遅くするために、原料部の温度を下
げて原料の蒸気圧を低くする方法があるが、基板温度の
低下に伴なって不純物を取り込み易くなり純度が低下す
るという問題が出てくる。また、被着時間の精度をあげ
るには、より迅速なバルブ開閉操作やシャッター開閉操
作が必要とされ、より高度の制御機構が要求される。従
って、気相輸送法が最も望ましい。しかも、気相輸送法
において、金属原料設置部の温度よりも基板設置部の温
度の方が０．１℃以上１０℃以下高くなるように温度を
制御して金属薄膜を被着するようにすると、金属は被着
時間に依存せず、高々２〜３原子層、通常は１原子層が
基板に化学吸着され、それ以上は被着されず、安心して
１０原子層以下の金属薄膜を被着させることができる。
また、基板への密着力も強いものが得られる。As a method of depositing a metal thin film having a thickness of 10 atomic layers or less, a vapor transport method, a molecular beam epitaxy method, a vacuum vapor deposition method, and a metal organic chemical vapor deposition method can be considered. In order to deposit a thin metal thin film, it is necessary to reduce the deposition speed or to increase the control accuracy of the deposition time. In order to slow the deposition rate, there is a method of lowering the temperature of the raw material portion to lower the vapor pressure of the raw material, but with the lowering of the substrate temperature, it becomes easy to take in impurities and the problem that the purity decreases. come. Further, in order to improve the accuracy of the deposition time, a quicker valve opening / closing operation and a shutter opening / closing operation are required, and a more sophisticated control mechanism is required. Accordingly, the vapor transport method is most desirable. In addition, in the vapor phase transport method, when the temperature of the substrate installation part is controlled to be higher than the temperature of the metal raw material installation part by 0.1 ° C. or more and 10 ° C. or less, the metal thin film is deposited. The metal does not depend on the deposition time, and at most 2 to 3 atomic layers, usually 1 atomic layer, are chemisorbed on the substrate, and no more is deposited, and a metal thin film of 10 atomic layers or less is deposited with confidence. Can be done.
Further, a material having a strong adhesion to the substrate can be obtained.
【０００９】[0009]
【実施例】以下、ＩｎＰ基板上にショットキ電極を形成
する場合を例にとって説明する。 （実施例１）まず、Ｆｅドープ半絶縁性ＩｎＰ基板上
に、Ｓｉ（シリコン）をドーピングしたｎ型ＩｎＰ層を
気相エピタキシャル成長させたものを用意する。成長さ
せるｎ型ＩｎＰエピタキシャル層は、例えばキャリア濃
度が２×１０17cm-3で、厚みが０．２μｍとする。次
に、上記基板上に、図１に示すような装置を用いて金属
薄膜を形成する。図１において、１は円筒状の石英反応
管で、この石英反応管１の一端（図では左端）にはガス
導入管２が、また石英反応管１の他端（図では右端）に
はガス排気管３が接続されている。上記ガス導入管２の
途中には、マスフローコントローラ４が設けられ、石英
反応管１内に流すガスの流量を調整できるように構成さ
れているとともに、石英反応管１の外側には、ヒーター
５ａ，５ｂが配置され、反応管内の温度を制御できるよ
うに構成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a case where a Schottky electrode is formed on an InP substrate will be described as an example. (Example 1) First, an n-type InP layer doped with Si (silicon) is vapor-phase epitaxially grown on an Fe-doped semi-insulating InP substrate. The n-type InP epitaxial layer to be grown has, for example, a carrier concentration of 2 × 10 17 cm −3 and a thickness of 0.2 μm. Next, a metal thin film is formed on the substrate using an apparatus as shown in FIG. In FIG. 1, reference numeral 1 denotes a cylindrical quartz reaction tube, and a gas introduction tube 2 is provided at one end (left end in the figure) of the quartz reaction tube 1 and a gas introduction tube is provided at the other end (right end in the figure) of the quartz reaction tube 1. The exhaust pipe 3 is connected. A mass flow controller 4 is provided in the middle of the gas introduction pipe 2 so as to be able to adjust the flow rate of the gas flowing into the quartz reaction tube 1, and a heater 5 a, 5b is arranged to control the temperature in the reaction tube.
【００１０】この実施例では、上記石英反応管１の上流
側に安定な酸化物を生成可能な金属原料６を入れたボー
ト７を設置し、石英反応管１の下流側に上記ＩｎＰ基板
８を設置する。それから、上記ヒーター５ａ，５ｂに給
電して、基板設置部の温度Ｔ２が上記原料ボート部の温
度Ｔ１よりも０．１℃以上１０℃以下高くなるように制
御する。また、ガス導入管２より水素もしくはアルゴン
のような不活性ガスを供給し、ボート７内の原料金属の
蒸気を下流側へ運んで、ＩｎＰ基板８上に化学吸着させ
て、１０原子層以下の金属薄膜を成長させる。In this embodiment, a boat 7 containing a metal material 6 capable of producing a stable oxide is installed upstream of the quartz reaction tube 1, and the InP substrate 8 is placed downstream of the quartz reaction tube 1. Install. Then, power is supplied to the heaters 5a and 5b so as to control the temperature T2 of the substrate installation portion to be higher than the temperature T1 of the raw material boat portion by 0.1 ° C. or more and 10 ° C. or less. In addition, an inert gas such as hydrogen or argon is supplied from the gas introduction pipe 2, and the vapor of the raw metal in the boat 7 is carried to the downstream side, and is chemically adsorbed on the InP substrate 8. Grow a metal thin film.
【００１１】このように、基板設置部の温度Ｔ２が上記
原料ボート部の温度Ｔ１よりも０．１℃以上１０℃以下
高くなるように制御し、金属の蒸気をキャリアガスで基
板側へ運んでやることにより、ＩｎＰ基板８上に１０原
子層以下の金属薄膜を成長させることができる。すなわ
ち、基板設置部の温度Ｔ２が上記原料ボート部の温度Ｔ
１よりも低い（Ｔ２＜Ｔ１）と、基板上への原料金属の
堆積反応が一方的に進行するため、数原子層単位での厚
みの制御が行なえないとともに、温度Ｔ２とＴ１との差
が０．１℃未満であると、温度揺らぎによって堆積の速
度にむらが生じるため数原子層単位での厚みの制御が行
なえない。また、温度Ｔ２とＴ１との差が１０℃を越え
ると、基板上への金属の堆積反応が進行しない。As described above, the temperature T2 of the substrate installation section is controlled so as to be higher than the temperature T1 of the raw material boat section by 0.1 ° C. or more and 10 ° C. or less, and the metal vapor is carried to the substrate side by the carrier gas. By doing so, a metal thin film of 10 atomic layers or less can be grown on the InP substrate 8. That is, the temperature T2 of the substrate setting part is equal to the temperature T of the raw material boat part.
If it is lower than 1 (T2 <T1), the deposition reaction of the raw material metal on the substrate proceeds unilaterally, so that the thickness cannot be controlled in units of several atomic layers, and the difference between the temperatures T2 and T1 becomes small. When the temperature is lower than 0.1 ° C., the fluctuation of temperature causes unevenness in the deposition rate, so that the thickness cannot be controlled in units of several atomic layers. If the difference between the temperatures T2 and T1 exceeds 10 ° C., the metal deposition reaction on the substrate does not proceed.
【００１２】一方、基板上への数原子層の金属薄膜形成
後は、上記ガス導入管２からの導入ガスを酸素に切換え
て、ＩｎＰ基板８上の金属薄膜を酸化させて金属酸化物
層１２を形成した後、電子ビーム蒸着装置等により上記
金属酸化物層１２上にショットキ電極１３を形成する
（図２参照）。１４は別個に形成されたオーミック電極
である。なお、上記実施例では、金属原料としてＢｅ，
Ｍｇ，Ａｌ，Ｓｉ，Ｃａ，Ｔｉ，Ｆｅ，Ｃｏ，Ｎｉ，Ｃ
ｕ，Ｚｎ，Ｇａ，Ｇｅ，Ａｓ，Ｚｒ，Ａｇ，Ｃｄ，Ｓ
ｎ，Ｓｂ，Ｔｅ，Ｃｓ，Ｐｂ，ＢｉもしくはＣｅのよう
に安定な酸化物を生成可能な金属を用いる。On the other hand, after the formation of the metal thin film of several atomic layers on the substrate, the gas introduced from the gas introduction pipe 2 is switched to oxygen, and the metal thin film on the InP substrate 8 is oxidized to form the metal oxide layer 12. Is formed, a Schottky electrode 13 is formed on the metal oxide layer 12 by an electron beam evaporation apparatus or the like (see FIG. 2). 14 is an ohmic electrode formed separately. In the above embodiment, Be,
Mg, Al, Si, Ca, Ti, Fe, Co, Ni, C
u, Zn, Ga, Ge, As, Zr, Ag, Cd, S
A metal capable of forming a stable oxide, such as n, Sb, Te, Cs, Pb, Bi or Ce, is used.
【００１３】一例として、金属原料としてＣｄを用い、
基板設置部の温度Ｔ２と原料ボート部の温度Ｔ１との温
度差ΔＴを２℃（ただし、Ｔ２＞Ｔ１）として、ＩｎＰ
基板の表面上に、Ｃｄを１０原子層以下となるように吸
着させてから、これを酸化させた後、この金属酸化物層
１２上に金電極１３を１５００Å形成して、図２に示す
ようなショットキダイオードを作製した。基板設置部の
温度Ｔ２を２００〜５００℃の範囲で変化させて得られ
たデバイスについて、電極１３，１４間に印加する電圧
を変えながら、電圧−電流特性を測定した。その結果、
ショットキ障壁は一般のＩｎＰショットキ電極の０．５
ｅＶを上回り、最高は０．８ｅＶであり、逆方向電圧２
Ｖでのリーク電流は１×１０-6Ａ／cm2で、耐圧は約９
０Ｖと良好であった。さらに、上記のようにして基板表
面にＣｄ薄膜を吸着させて酸化させた金属酸化膜の形成
後の基板表面を、オージェ（Ａｕｇｅｒ）電子分光装置
によって測定したところ、数原子層のＣｄ酸化膜が形成
されていることが分かった。As an example, Cd is used as a metal raw material,
Assuming that the temperature difference ΔT between the temperature T2 of the substrate setting part and the temperature T1 of the raw material boat part is 2 ° C. (where T2> T1),
After adsorbing Cd on the surface of the substrate so as to have a thickness of 10 atomic layers or less, and oxidizing the same, a gold electrode 13 is formed on the metal oxide layer 12 at 1500 °, as shown in FIG. A Schottky diode was produced. The voltage-current characteristics of the device obtained by changing the temperature T2 of the substrate installation portion in the range of 200 to 500 ° C. were measured while changing the voltage applied between the electrodes 13 and 14. as a result,
The Schottky barrier is 0.5% of the general InP Schottky electrode.
eV, the maximum is 0.8 eV, and the reverse voltage 2
The leakage current at V in 1 × 10- 6 A / cm 2 , the breakdown voltage of about 9
It was as good as 0V. Further, the surface of the substrate after the formation of the metal oxide film obtained by adsorbing and oxidizing the Cd thin film on the substrate surface as described above was measured by an Auger electron spectrometer. It was found to be formed.
【００１４】[0014]
【００１５】[0015]
【００１６】[0016]
【００１７】上記実施例では、一例としてＩｎＰ基板上
へのショットキ電極の形成を例にとって説明したが、こ
の発明はＩｎＧａＡｓ基板その他ＩＩＩ−Ｖ族化合物半
導体基板または表面にＩＩＩ−Ｖ族化合物半導体層がエ
ピタキシャル成長されてなる基板上にショットキ電極を
形成する場合に適用することができる。In the above embodiment, the formation of a Schottky electrode on an InP substrate has been described as an example. However, the present invention relates to an InGaAs substrate or other III-V compound semiconductor substrate or a III-V compound semiconductor layer formed on the surface. The present invention can be applied to a case where a Schottky electrode is formed on a substrate formed by epitaxial growth.
【００１８】[0018]
【発明の効果】以上説明したように本発明は、金属原料
設置部および基板設置部を加熱しながら、キャリアガス
を金属原料設置部側から基板設置部側へ流して、表面に
ＩＩＩ−Ｖ族化合物半導体層がエピタキシャル成長され
てなる基板またはＩＩＩ−Ｖ族化合物半導体基板上に、
安定な酸化物を生成可能な金属の薄膜を１０原子層以下
に被着させ、この金属薄膜を酸化させた後、この金属酸
化物層の上にショットキ電極を形成するようにしたの
で、基板と金属酸化物層との間に働く弾性歪によって界
面での不対結合が発生するのが防止され、ショットキ障
壁高さが充分に高いショットキ電極が得られ、これによ
って、逆方向リーク電流が小さく耐圧の高いショットキ
ゲート電極を有する特性の良好なＭＥＳＦＥＴおよびシ
ョットキ・ダイオードを製造することが可能となる。し
かも、キャリアガスを金属原料設置部側から基板設置部
側へ流して、安定な酸化物を生成可能な金属の薄膜を化
合物半導体基板表面により被着させ、この金属薄膜を酸
化させるようにしたので、表面欠陥を生じさせることな
く１０原子層以下の厚みの金属酸化物層を形成し、界面
準位密度が低くかつショットキ障壁高さが充分に高いシ
ョットキ電極を得ることができるという効果がある。ま
た、金属原料設置部の温度よりも基板設置部の温度の方
が０．１℃以上１０℃以下高くなるように温度を制御し
て金属薄膜を被着するようにしたので、金属は被着時間
に依存せずに１〜３原子層が基板に化学吸着され、それ
以上は被着されないため、安心して１０原子層以下の金
属薄膜を被着させることができるとともに、基板への密
着力も強いものが得られるという効果がある。As described above, according to the present invention, a carrier gas is flowed from the metal material setting part side to the substrate setting part side while heating the metal material setting part and the substrate setting part, and the III-V group is formed on the surface. On a substrate or a III-V compound semiconductor substrate on which a compound semiconductor layer is epitaxially grown,
A metal thin film capable of producing a stable oxide is deposited on a layer of 10 atomic layers or less, and after oxidizing the metal thin film, a Schottky electrode is formed on the metal oxide layer. The occurrence of unpaired coupling at the interface due to the elastic strain acting between the metal oxide layer and the metal oxide layer is prevented, and a Schottky electrode having a sufficiently high Schottky barrier height is obtained. It is possible to manufacture a MESFET and a Schottky diode having good characteristics having a Schottky gate electrode having a high density. In addition, a carrier gas is flowed from the metal material installation part side to the substrate installation part side to deposit a metal thin film capable of generating a stable oxide on the surface of the compound semiconductor substrate and oxidize the metal thin film. By forming a metal oxide layer having a thickness of 10 atomic layers or less without causing surface defects, there is an effect that a Schottky electrode having a low interface state density and a sufficiently high Schottky barrier height can be obtained. In addition, the metal thin film is deposited by controlling the temperature so that the temperature of the substrate installation part is higher than the temperature of the metal raw material installation part by 0.1 ° C. or more and 10 ° C. or less. 1 to 3 atomic layers are chemisorbed on the substrate without depending on time and are not applied any more, so that a metal thin film of 10 atomic layers or less can be applied with confidence and strong adhesion to the substrate. There is an effect that things can be obtained.
【図１】本発明方法における金属薄膜形成に使用して好
適な装置の一例を示す断面正面図である。FIG. 1 is a sectional front view showing an example of an apparatus suitable for use in forming a metal thin film in the method of the present invention.
【図２】実施例１において製造したデバイスの構造を示
す断面図である。FIG. 2 is a sectional view showing the structure of the device manufactured in Example 1.
１ 石英反応管 ２ ガス導入管 ３ ガス排気管 ４ マスフローコントローラ ５ａ，５ｂ ヒーター ６ 金属原料 ７ ボート ８ 成長用基板（ＩｎＰ基板） １０ 半絶縁性ＩｎＰ基板 １１ Ｎ型ＩｎＰエピタキシャル膜 １２ 金属酸化物層 １３ ショットキ電極（金電極） １４ オーミック電極 DESCRIPTION OF SYMBOLS 1 Quartz reaction tube 2 Gas introduction pipe 3 Gas exhaust pipe 4 Mass flow controller 5a, 5b heater 6 Metal raw material 7 Boat 8 Growth substrate (InP substrate) 10 Semi-insulating InP substrate 11 N-type InP epitaxial film 12 Metal oxide layer 13 Schottky electrode (gold electrode) 14 Ohmic electrode
Claims (2)
しながら、キャリアガスを金属原料設置部側から基板設
置部側へ流して、表面にＩＩＩ−Ｖ族化合物半導体層が
エピタキシャル成長されてなる基板またはＩＩＩ−Ｖ族
化合物半導体基板上に、安定な酸化物を生成可能な金属
の薄膜を１０原子層以下に被着させ、この金属薄膜を酸
化させて金属酸化物層を形成した後、前記金属酸化物層
の上にショットキ電極を形成するようにしたことを特徴
とする化合物半導体装置の製造方法。A substrate having a group III-V compound semiconductor layer epitaxially grown on a surface thereof by flowing a carrier gas from the side of the metal source installation section to the side of the substrate installation section while heating the metal source installation section and the substrate installation section. Alternatively, a thin film of a metal capable of forming a stable oxide is deposited on a III-V compound semiconductor substrate in a thickness of 10 atomic layers or less, and the metal thin film is oxidized to form a metal oxide layer. A method for manufacturing a compound semiconductor device, wherein a Schottky electrode is formed on an oxide layer.
度よりも基板設置部の温度の方が０．１℃以上１０℃以
下高くなるように温度を制御するようにしたことを特徴
とする化合物半導体装置の製造方法。2. The method according to claim 1, wherein the temperature is controlled such that the temperature of the substrate installation part is higher than the temperature of the metal raw material installation part by 0.1 ° C. or more and 10 ° C. or less. A method for manufacturing a compound semiconductor device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4098733A JP2750330B2 (en) | 1991-12-17 | 1992-03-24 | Method for manufacturing compound semiconductor device |
| US07/990,707 US5326717A (en) | 1991-12-17 | 1992-12-15 | Method of fabricating a compound semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3-353644 | 1991-12-17 | ||
| JP35364491 | 1991-12-17 | ||
| JP4098733A JP2750330B2 (en) | 1991-12-17 | 1992-03-24 | Method for manufacturing compound semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05226371A JPH05226371A (en) | 1993-09-03 |
| JP2750330B2 true JP2750330B2 (en) | 1998-05-13 |
Family
ID=26439855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4098733A Expired - Lifetime JP2750330B2 (en) | 1991-12-17 | 1992-03-24 | Method for manufacturing compound semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5326717A (en) |
| JP (1) | JP2750330B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4751498B2 (en) * | 2000-03-30 | 2011-08-17 | 富士通株式会社 | Semiconductor three-terminal device |
| JP4352783B2 (en) * | 2002-08-23 | 2009-10-28 | 東京エレクトロン株式会社 | Gas supply system and processing system |
| KR101236811B1 (en) * | 2006-03-10 | 2013-02-25 | 페어차일드코리아반도체 주식회사 | GaN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME |
| FI20106181A0 (en) | 2010-11-11 | 2010-11-11 | Pekka Laukkanen | A PROCEDURE FOR FORMING A SUBSTRATE AND SUBSTRATE |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0812844B2 (en) * | 1987-03-27 | 1996-02-07 | 日本電気株式会社 | (III) -Group V compound semiconductor and method for forming the same |
| JPH0666274B2 (en) * | 1987-07-01 | 1994-08-24 | 日本電気株式会社 | (III) -Method for forming group V compound semiconductor |
| JPS6469052A (en) * | 1987-09-10 | 1989-03-15 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| US5027166A (en) * | 1987-12-04 | 1991-06-25 | Sanken Electric Co., Ltd. | High voltage, high speed Schottky semiconductor device and method of fabrication |
| JP2932305B2 (en) * | 1990-07-11 | 1999-08-09 | サンケン電気株式会社 | Method for manufacturing semiconductor device |
-
1992
- 1992-03-24 JP JP4098733A patent/JP2750330B2/en not_active Expired - Lifetime
- 1992-12-15 US US07/990,707 patent/US5326717A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US5326717A (en) | 1994-07-05 |
| JPH05226371A (en) | 1993-09-03 |
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