JP2982652B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a field effect transistor ("FE") using a ferroelectric and a conductor or a semiconductor as a part of a gate insulating film.
T ") and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a MOS type field effect transistor (metal oxide semiconductor field effect transistor) has been used.
r, a field effect transistor (metal ferroele) using a ferroelectric as a gate insulating film of a “MOSFET”
ctric semiconductor field effect transistor, "M
FSFET ”) is used as a memory cell of a nonvolatile storage device.

FIG. 3 shows an example of the configuration of a conventional MFSFET.

Referring to FIG. 3, a ferroelectric film 3 serving as a gate insulating film is formed on a silicon substrate, and a gate electrode 1 is formed thereon to form an MFS structure. In FIG. 3, the gate insulating film portion may have a laminated structure of a ferroelectric and a paraelectric, or a laminated structure of a ferroelectric, a paraelectric and a conductor, in addition to the ferroelectric alone.

Since the ferroelectric causes polarization when a voltage is applied, a voltage is applied between the gate electrode and the silicon substrate or between the source region 9 and the drain region 10 so that the ferroelectric film 3 of the gate insulating film is formed. Can be polarized. At that time, charge is attracted or rejected to the silicon substrate surface depending on the polarity of polarization,
The threshold voltage of the MFSFET changes.

[0006] Even if the applied voltage is removed after the ferroelectric film 3 is polarized, remnant polarization remains as a property of the ferroelectric, and the threshold voltage remains changed. By utilizing this, a nonvolatile storage device can be configured.

FIG. 4 shows an example of a circuit configuration of a nonvolatile memory device using an MFSFET. Usually, one MFSF
ET is represented by the symbol shown in FIG.

Referring to FIG. 4, MFSFETs 4A and 4B
The word line WL1 is connected to the gates of the MFSFETs 4C and 4C.
The word line WL2 is connected to the gate of D, the bit lines BL1 and BL3 are connected to the sources and drains of the MFSFETs 4A and 4C, and the bit lines BL3 and BL4 are connected to the sources and drains of the MFSFETs 4B and 4D. I have.

When writing to the MFSFET 4A, a high voltage is applied to the word line WL1 and a low voltage is applied to the bit lines BL1 and BL3, or a low voltage is applied to the word line WL1 and a high voltage is applied to the bit lines BL1 and BL3. 2
The direction of polarization can be written.

However, with this structure, a voltage is also applied to the MFSFET 4C connected to the same bit lines BL1 and BL3 of the unselected word line WL2.

Further, by setting the word line WL2 to an intermediate potential between the high voltage and the low voltage, the voltage applied to the ferroelectric of the MFSFET 4C can be reduced to about half of the voltage at the time of writing. , May break the polarization state.

As an example of a conventional cell structure in which a voltage is not applied to a ferroelectric substance when writing to another cell, for example, Japanese Patent Laid-Open No. 2-64993 discloses an MFSFET 6C as shown in FIG. MO for source and drain of
The sources or drains of the SFETs 6C1 and 6C2 are connected respectively. The gates of the MOSFETs 6C1 and 6C2 are connected to word lines WL11 and WL12, respectively.

Even if a voltage is applied to the bit line BL1 for writing to a cell of another word line, the voltage is not applied to the ferroelectric material of the MFSFET 6C by turning off the write control MOSFET 6C1 by the word line WL11. .

However, in the structure shown in FIG.
In addition to the ET, a MOSFET is required (that is, a three-transistor / cell structure), which increases the cell area, and is not suitable for integration of a nonvolatile memory.

Japanese Patent Application Laid-Open No. 5-326977 discloses a structure in which a write control FET is adjacent to an MFSFET. As shown in FIG. 7, a surface having a source region 9 and a drain region 10 sandwiching a channel region is formed. Orientation (100)
From the silicon substrate 23, the ferroelectric gate film 21 formed on the channel region, the gate electrode 15 formed on the ferroelectric gate film 21, and the gate wiring 16 formed on the gate electrode 15. MFSFET. A field oxide film 8 is provided directly above the source and drain regions 9 and 10, oxide films 17 and 18 are formed on the field oxide film 8, and an oxide film is formed on the drain region 10 side of the gate electrode 15 of the MFSFET. Through the film 17 (ie, adjacent to the gate electrode), a writing sidewall 20 made of a conductive material is formed on the semiconductor substrate 23.
Are formed in an insulated state with respect to. In addition, a write control transistor portion (MOSFE) in which the write sidewall 20 is connected to the gate wiring 16 and used as a gate.
T) is formed. Similarly, a reading side wall 19 is provided adjacent to the source 9 side of the gate electrode 15.

[0016]

However, in this structure, the write control FET is provided between the gate portion and the drain region 10 of the MFSFET. In order to increase the current of the write control FET, the gate portion and the drain are required. The distance of the area must be reduced.

Further, the field oxide film 8 is formed on the drain region 10, and a step is formed between the field oxide film 8 and the silicon surface of the gate portion.

When a ferroelectric substance is formed on this step, a solution is spin-coated in the sol-gel method, which is one of the film forming methods. Therefore, if there is a concave portion, the thickness of the ferroelectric substance depends on its shape and depth. Therefore, a uniform film cannot be formed, the characteristics of the MFSFET vary, and a margin required at the time of design increases.

Conventionally, for example, Japanese Patent Application Laid-Open No. 5-369
No. 86 discloses a MOS having a floating gate.
FET and other MOSFET are divided gate (split
A gate (gate) structure has been proposed.

FIG. 8 shows typical steps of a conventional method of manufacturing a semiconductor device having a split gate structure in the order of steps. A gate insulating film (oxide film) 6 and a floating gate 12 are formed over the transistor formation region (see FIG. 8A), and are patterned into a gate shape.

On top of this, an oxide film 14 serving as a gate insulating film of another FET formed adjacent to the FET having the floating gate is formed together with an insulating film on the floating gate 12. Control gate film 13
Is formed thereon, and a resist 11 is applied thereon and patterned (see FIG. 8B) to form a divided gate structure (see FIG. 8C). Referring to FIG. 8C, floating gate 12 is aligned with drain region 10, and control gate 13 is aligned with one edge of floating gate 12, source region 9 and drain region 10. In this case, the floating gate 12 is insulated from the control gate film 13 by the oxide film 14.

In the structure shown in FIG. 8, since the source region 9 and the drain region 10 are formed using the gate as a mask, the distance between the step of the field oxide film and the gate varies depending on the ferroelectric film formation, especially the shape dependence. It can be set to a degree that does not appear. Therefore, when such a split gate structure is applied, it is assumed that it is possible to separate the step portion of the field oxide film from the gate portion in a structure in which the write control FET and the MFSFET are adjacent to each other.

In general, when a ferroelectric substance is contained in a gate insulating film, elements in the ferroelectric substance diffuse around because the formation temperature of the ferroelectric substance is high (the temperature is raised during firing).

As one of means for avoiding the deterioration of characteristics due to the contamination of the gate oxide film and the contamination of the channel region by the diffusion, a film serving as a diffusion barrier under the ferroelectric is used. There is a way to keep it. In this case, since it is necessary to form the ferroelectric in a state where the barrier film exists, the processing of the gate shape is performed after the formation of the ferroelectric film.

However, when the split gate of the MFSFET is to be formed according to the conventional manufacturing method shown in FIG. 8, after the formation of the ferroelectric, the oxide film 14 (the structure of the gate insulating film 6 and the floating gate 12 of FIG. MFSFE
T), the oxide film 14 becomes M
Since the voltage remains below the gate of the FSFET, the voltage applied to the ferroelectric decreases, and a large voltage is required for polarization, which causes a problem that an operating voltage and a design margin are limited.

The oxide film 14 formed on the ferroelectric
When etching the oxide film, whether the entire oxide film is etched or if a part of the oxide film is left,
Alternatively, the thickness of the ferroelectric varies.

As a result, the voltage and electric field applied to the ferroelectric material vary, and the ferroelectric characteristics such as the polarization voltage vary. For this reason, there are problems that the design margin must be increased and the yield becomes unstable.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to reduce the variation in the characteristics of the ferroelectric film in the MFSFE.
It is an object of the present invention to provide a semiconductor device having a T split gate structure and a method of manufacturing the same.

[0029]

[0030]

[0031]

The present invention preferably provides a substrate having a source region and a drain region separated by a channel region, an insulating film on the channel,
A gate ferroelectric insulating film formed by laminating a conductor layer and a ferroelectric layer; a first gate portion including a gate electrode formed on the gate ferroelectric insulating film; A second gate portion comprising an insulating film and a gate electrode, the second gate portion being provided at a position adjacent to the first gate portion via an insulating layer provided on a side wall of the first gate portion;
A semiconductor device is provided, wherein the gate electrodes of the first and second gate portions are electrically connected to each other.

According to the present invention, a substrate having a source region and a drain region separated by a channel region, a first ferroelectric layer, a first conductor layer, and a second
A gate ferroelectric insulating film formed by stacking the following ferroelectric layers, a first gate portion including a gate electrode formed on the gate ferroelectric insulating film, and the first gate on the channel An insulating film provided at a position adjacent to the first gate unit via an insulating layer provided on a side wall of the unit;
A second gate portion comprising a gate electrode, wherein the gate electrodes of the first and second gate portions are electrically connected to each other.

[0033]

In the present invention, in the step (b), a gate ferroelectric insulating film having a laminated structure of a conductor film and / or a semiconductor film, a ferroelectric film, and an insulating film may be formed. .

In the manufacturing method of the present invention, preferably, (a) a field region and a transistor region are formed on a semiconductor substrate, and (b) a laminated structure including an insulating layer, a first conductor layer, and a ferroelectric layer is formed. Forming a gate ferroelectric insulating film, (c) forming a conductor etching stopper film on the gate ferroelectric insulating film, and (d) patterning the etching stopper film and the gate ferroelectric insulating film. Forming a gate,
(e) forming an insulating layer so as to cover the gate portion, (f) exposing an etching stopper film, a source portion, and a drain portion above the gate portion by etch-back, and forming an insulating layer in the gate ferroelectric insulating film. Leave the insulating layer side wall on the side of the conductor film,
(g) forming and patterning a gate insulating film and a conductive film for a second FET formed adjacent to the gate portion,
It is characterized by forming a split gate structure.

[0036]

The present invention relates to an MFSFET having a split gate structure.
According to the present invention, an insulating film (oxide film) once formed on an etching stopper film of an FET including a ferroelectric as a gate insulating film is etched to an etching stopper film. Since the backing is performed, no insulating film other than the gate ferroelectric insulating film is formed and does not remain under the gate electrode.

Further, after the gate ferroelectric insulating film is formed, the thickness of the gate ferroelectric insulating film is changed even if the etching stopper film is etched because the conductive etching stopper film is provided thereon. In addition, even if the etching stopper film is a conductor and is etched and its thickness changes, the voltage and electric field applied to the ferroelectric and the ferroelectric characteristics do not change.

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram illustrating the configuration of an embodiment of the present invention. FIG. 2 is a view for explaining the manufacturing method according to the present embodiment in the order of typical steps.

Referring to FIG. 2, in this embodiment, after a field region and a transistor formation region are formed by field oxide film 8 on semiconductor substrate 23, gate oxide film 6 is formed.
Is formed by thermal oxidation, and then platinum 5 is formed by a sputtering method, and a PZT film 3 which is a ferroelectric substance is formed on the platinum 5 by a sol-gel method at about 650 ° C.

Platinum 2 is formed on PZT film 3 as an etching stopper film. A resist 11 is formed on platinum 2 serving as an etching stopper film, and the platinum 2, PZT film 3, platinum 5, and gate oxide film 6 are patterned to form a gate portion (see FIG. 2A).

Next, an oxide film 4 is formed on the entire surface by plasma CVD (see FIG. 2B).

By etching back, the etching stopper film 2 above the gate portion and the substrate in the transistor formation region other than the lower portion of the gate are exposed, and the oxide film 4 is left only on the side surface of the gate portion of the MFSFET. In 4), the platinum 5 contained in the gate ferroelectric insulating film is insulated (see FIG. 2C). At this time, the PZT film 3 is etched as in the case where there is no platinum 2 because the platinum 2 as a conductor is etched even if the etching is performed too much, the thickness changes, and the variation in the ferroelectric characteristics varies depending on the etching amount. This phenomenon can be avoided.

Another F formed adjacent to this gate portion
A gate insulating film 7 is formed on the substrate surface for ET (exposed surface of the substrate) by thermal oxidation. Thereafter, polysilicon 1 is formed by CVD (see FIG. 2D), and is patterned to form a gate connecting the two FETs.

Next, ion implantation is performed to form the drain diffusion layer 1.
0 and a source diffusion layer 9 are formed (see FIG. 8E). If ion implantation is performed after gate patterning, L
A diffusion layer having a DD (Lightly Doped Drain) structure can also be formed.

Through the above steps, an MFSFET semiconductor device having a split gate structure as shown in FIG. 1 is manufactured.
In this embodiment, polysilicon 1 serving as a gate electrode is used.
The source region 9 and the drain region 10 can be formed by ion-implantation using the oxide film 4 remaining on the side surfaces of the gate and platinum 2 as a mask. Field oxide film 8
Between the field region and transistor formation region due to
The distance of the gate portion of the FSFET can be set large, and variations in ferroelectric characteristics are suppressed. Note that M
The FET adjacent to the FSFET can function as, for example, a write control FET as described in the above-described conventional example.

In this embodiment, a conductor layer other than platinum 5 or a semiconductor layer doped with impurities may be used as the gate portion of the MFSFET as long as it contains a ferroelectric substance and a conductive material. A structure in which a conductor layer and a semiconductor layer are stacked may be used. Further, in this embodiment, as shown in FIG. 1, the gate portion of the MFSFET has a configuration including a gate oxide film 6, a platinum 2, a ferroelectric (PZT) film 3, and a platinum 2 provided on a substrate. However, it is also possible to adopt a configuration comprising a first ferroelectric film, a first conductor layer, a second ferroelectric (PZT) film, and platinum 2 on a substrate. Even in such a configuration, in a process after forming the gate ferroelectric insulating film, the etching stopper film is etched since the conductor etching stopper film is provided on the gate ferroelectric insulating film. The thickness of the gate ferroelectric insulating film does not change even if it is performed, and the voltage, electric field, and ferroelectric characteristics applied to the ferroelectric change even if the thickness changes because the etching stopper film is etched because it is a conductor Never. Further, although PZT is used as the ferroelectric film in this embodiment, another ferroelectric material such as PLZT having a perovskite-type crystal structure similar to this may be used.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment, but includes various embodiments according to the principle of the present invention.

[0049]

As described above, according to the present invention,
The insulating film (oxide film) once formed on the etching stopper film of the FET containing the ferroelectric as the gate insulating film is etched back to the etching stopper film, and does not remain under the gate electrode, except for the gate ferroelectric insulating film. Since the insulating film is not formed, the voltage applied to the ferroelectric, which is a problem in the prior art, is reduced, and a large voltage is required to polarize the ferroelectric, which limits the operating voltage and the design margin. This solves the problem of the prior art.

Further, according to the present invention, after the formation of the gate ferroelectric insulating film, the conductor etching stopper film exists on the gate ferroelectric insulating film. The thickness of the gate ferroelectric insulating film does not change, and the voltage and electric field applied to the ferroelectric and the ferroelectric characteristics change even if the thickness of the etching stopper film changes because the conductor is etched. There is no. For this reason, according to the present invention, it is completely solved that the operating voltage and the design margin are restricted and the yield becomes unstable, which are problems in the above-mentioned prior art.

Further, according to the present invention, the step portion between the field region and the transistor formation region due to the field oxide film and the MFSF which causes the thickness variation at the time of forming the ferroelectric material.
The distance between the gate portions of the ET can be set large, and variations in ferroelectric characteristics are suppressed. For this reason, the present invention avoids that the operating voltage and the design margin are restricted and the yield becomes unstable.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining a manufacturing method according to one embodiment of the present invention in the order of steps.

FIG. 3 is a diagram illustrating an MFSFET.

FIG. 4 is a diagram illustrating an example of a circuit configuration of a conventional nonvolatile memory device using an MFSFET.

FIG. 5 is a diagram showing symbols in a circuit diagram of the MFSFET.

FIG. 6 is a diagram showing a circuit configuration of a conventional memory cell using an MFSFET.

FIG. 7 is a diagram showing a configuration of a conventional MFSFET.

FIG. 8 is a cross-sectional view of a typical step in a conventional method of manufacturing a split gate structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Polysilicon (gate electrode) 2 Platinum (etching stopper film) 3 PZT (ferroelectric) 4 Oxide film 5 Platinum 6 Gate oxide film 7 Gate oxide film 8 Field oxide film 9 Source region 10 Drain region 11 Resist 12 Floating gate 13 Control gate 14 Oxide film 15 Gate electrode 16 Gate wiring 17 Oxide film 18 Oxide film 19 Read sidewall 20 Write sidewall 21 Ferroelectric gate film

Continuation of the front page (56) References JP-A-6-196647 (JP, A) JP-A-6-112500 (JP, A) JP-A-6-112504 (JP, A) JP-A-5-206411 (JP) , A) JP-A-5-326977 (JP, A) Electronic materials August issue (1994) p. 27−32

Claims (2)

(57) [Claims] A substrate having a source region and a drain region separated by a channel region; a gate ferroelectric insulating film in which an insulating film, a first conductor layer, and a ferroelectric layer are stacked on the channel; A first gate portion comprising a gate electrode formed on the gate ferroelectric insulating film; and an insulating layer provided on a side wall of the first gate portion on the channel. And a second gate portion comprising an insulating film and a gate electrode, provided at a position adjacent to the portion, wherein the gate electrodes of the first and second gate portions are electrically connected to each other. Semiconductor device. 2. A substrate having a source region and a drain region separated by a channel region, and a first ferroelectric layer, a first conductor layer, and a second ferroelectric layer laminated on the channel. A gate ferroelectric insulating film, a first gate portion including a gate electrode formed on the gate ferroelectric insulating film, and an insulating layer provided on a side wall of the first gate portion on the channel A second gate portion, which is provided at a position adjacent to the first gate portion through a second gate portion and includes an insulating film and a gate electrode, wherein the gate electrodes of the first and second gate portions are electrically connected to each other. A semiconductor device characterized in that the semiconductor device is electrically connected.