JP2972451B2 - Cache memory control method by hardware control software - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control method using hardware control software, and more particularly to controlling the number of block loads occurring when a block is loaded into a cache memory and updating a cache directory when reading a command from a main memory device. The present invention relates to a cache memory control method by hardware control software in the control of the block memory and the control of the operation of suppressing the block load to the cache memory.

[0002]

2. Description of the Related Art In order to bridge an operation speed gap between a main processing unit and a main memory unit, a method of providing a cache memory unit composed of a high-speed and small-capacity memory is generally adopted between them. Further, in a method of prefetching and executing an instruction word such as pipeline processing, a cache memory is separated into an instruction word and an operand, and an instruction word cache memory and an operand cache memory are provided.

The main memory device is divided into blocks of a predetermined capacity in advance, and data stored in some of these blocks is written in a cache memory in the cache memory device (block load). ).

[0004] Information on which block in the block of the main memory device is written in the cache memory is written in a cache directory in the cache memory device.

[0005] In response to a data read request from the main processor, the cache directory and the cache memory are read. First, the data read from the cache directory determines whether the data requested to be read exists in the cache memory. Is examined. If there is (hit), the corresponding data in the data read from the cache memory is sent to the main processing unit. If it is found that the data does not exist (mis-hit), the read data from the cache memory is discarded, the corresponding address in the main memory device is read and sent to the main processing device, and the main memory containing the read data is read. A data block in the device is block-loaded into a free block of the cache memory or a block with the longest unused time (LRU replacement).
At the same time, the cache directory and the LRU replacement information are also updated.

[0006] The number of block loads from the main memory device executed at the time of a mishit is a fixed value determined by the hardware configuration. The above operation is performed in the same manner in the case of the instruction word cache memory.

On the other hand, in the main processing unit, hardware control software (hereinafter referred to as HCSW) for hardware / firmware functions has been implemented in order to reduce the control storage capacity and the firmware design amount. HC
SW is a machine language instruction group coded by a software instruction group selected from all instructions released to general software and an HCSW support instruction group, and is stored in a hardware area of the main memory.

The operation modes of the main processing unit include a software mode and an HCSW mode. In the software mode, software manages the contents of an instruction counter, a base register, a general-purpose register, and the like, and the main processing device operates based on instructions from the software. Also,
In the case of the HCSW mode, the contents of the instruction counter, base register, general-purpose register, and the like managed by the software are saved, and the main processing device operates based on the instruction of the HCSW.

The HCSW is activated by hardware or firmware as required, and enters the HCSW mode.
After the processing is completed, the mode shifts to software mode.

The HCSW is for realizing a part of the hardware / firmware function.
An HCSW instruction group is present in the main memory in a certain functional unit. The functions realized by the HCSW are mainly control functions such as so-called process management / stack processing / configuration control instructions.
As the operation of W, there are few repetitive processing such as loop processing,
In many cases, execution is sequentially performed in the vertical direction. For this reason, the arrangement of the instruction words of the HCSW instruction group on the main memory is not a local arrangement on the main memory typified by loop processing as described in general software, but realizes one function. For this reason, it is characterized by being arranged continuously on a wide address.

In the cache memory control method, there is no distinction between general software and HCSW.
The general software instruction group and the HCSW instruction group are similarly controlled and written into the instruction word cache memory only by being controlled based on the address on the main memory.

[0012]

In the above-described conventional cache memory control method, when the above-described HCSW is to be executed, a miss hit occurs in the instruction word cache memory, and a predetermined main memory device transmits the instruction word cache memory to the instruction word cache memory. The amount of read data at the time of block loading performed by
Since the program amount of the HCSW instruction group for realizing a certain function is much smaller and the number of block loads is fixed, when the execution of the HCSW instruction in the instruction word cache memory loaded with the block is completed. Then, the instruction word cache memory becomes a mishit, and the block load needs to be performed. Thereafter, this state is repeated, and while the HCSW realizes one function,
There is a drawback that the instruction word cache memory becomes a mishit many times, and the performance is significantly reduced.

In the method of using the instruction word cache memory, the general software instruction and the HCSW instruction are controlled without distinction, and both the general software instruction group and the HCSW instruction group are controlled based on the address in the main memory. Similarly, since the instruction word cache memory is written in a lump, even if it is known that the group of HCSW instructions is of low importance in performance, the instruction word cache memory is written to the instruction word cache memory. There is a drawback that the number of empty blocks in the block is reduced, or blocks in which general software instructions and HCSW instructions which are more important in performance exist are lost from the instruction word cache memory.

Further, by writing the HCSW instruction group of low performance importance, other general software instruction groups of high performance importance and the HCSW instruction which should be originally stored in the instruction word cache memory. The logic in which the block in which the instruction group exists is block-loaded to the block with the longest unused time (LRU replacement) becomes a target block to be replaced by the next block load, and therefore, it is effectively used. There is a disadvantage that the instruction cache memory to be executed is not used effectively.

[0015]

According to the cache memory control method by the hardware control software of the present invention, hardware control software which is a routine in a machine language instruction format stored in a hardware area of a main memory device is executed by a microprogram. A function for controlling the hardware by executing the hardware control software one by one by a microprogram, and a means for storing the hardware control software instruction and the general software instruction in the same cache memory without distinction, Means for changing the number of times of block loading from the main memory device to the cache memory before starting the hardware control software, means for arbitrarily changing the hardware control software, Triggered by the completion of Dowea control software, and means for changing the hardware predetermined block loading number, the updating operation of the LRU replacement information is executed when the block load,
Means for inhibiting by an instruction before the start of the hardware control software, means for inhibiting by an instruction of the hardware control software, and releasing the update operation inhibition of the LRU replacement information upon termination of the hardware control software Means for suppressing a cache block load and reading an instruction word without passing through a cache memory, and instructing to inhibit block load before starting the hardware control software, It is provided with means for instructing the block load suppression by hardware control software, and means for releasing the block load suppression when the hardware control software ends.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a cache memory control method using hardware control software according to the present invention.

As shown in FIG. 1, an instruction cache memory device adopting a cache memory control method by hardware control software according to the present embodiment has an address register 1 and an instruction word including block groups 3, 4, 5, and 6. A cache memory 2, an instruction word cache directory 7 including LRU replacement information 8 and block groups 9, 10, 11, 12, and hit detection circuits 13, 14, 15,
16, an instruction cache memory control circuit 18, a data selection circuit 19, an address update circuit 20, an instruction cache memory buffer device 17, a buffer device control circuit 21, and an instruction cache memory write control circuit 2.
2 and an LRU replacement information updating circuit 23.

In FIG. 1, in response to a data read request from a main processor (not shown), a command 101 and an address signal 102 are sent from the main processor to the instruction word cache memory device. Address signal 102
Are input to the address register 1 and held. The middle address signal 104 of the address signal 102 is
A column number is designated in the instruction word cache memory 2, the instruction word cache directory 7, and the instruction word cache memory write inhibit circuit 22, and becomes an access address signal.

From the block groups 9, 10, 11, and 12 of the instruction word cache directory 7, the middle address signal 1
From the column number designated by 04, the load content is read out to the hit detection circuits 13, 14, 15, and 16, respectively. In the LRU replacement information 8, the column number portion designated by the middle address signal 104 is also updated. At this time, the LRU replacement update inhibit signal 12 specified by the HCSW instruction group
If 5 is sent from the main processing unit, the operation of the LRU replacement information updating circuit 23 is stopped, the LRU replacement information 8 is not updated, and the state of the old value is maintained.

Similarly, from the block groups 3, 4, 5, and 6 of the instruction word cache memory 2, the middle address signal 1
The content of the load is read out to the data selection circuit 19 from the column number designated by 04.

In the hit detection circuits 13, 14, 15, and 16, when the valid bits of the blocks 9, 10, 11, and 12 indicate valid display, the data bits to be read and the data bits are sent from the address register 1. Hit signals 110, 111, 112, 113 indicating a hit or mishit condition are compared with the upper address 103.
Are sent to the instruction word cache memory control circuit 18, respectively.

In this process, the hit detection circuit 13,
Hit signals 110, 11 sent to the instruction word cache memory control circuit 18 from 14, 15, 16 respectively.
When all of 1, 1, 112 and 113 indicate a mishit state, the data read from the block groups 3, 4, 5, and 6 of the instruction cache memory 2 are discarded, and the instruction cache memory control circuit 18 Indicates a read request signal 1 to a main memory device (not shown).
17 is sent out. At this time, a read request to the main memory device is transmitted by the block load request signal 126 sent from the main processing unit for the number of block loads specified by the HCSW instruction group.

In response to the read request signal 117, the main memory device sends a data block 108 from a block having a predetermined column number and sends it to the instruction word cache memory buffer device 17.

The instruction cache memory buffer output data block 109 is assigned to a block group indicated by the LRU replacement information 8, in this case, a block having the predetermined column number in the block group 3 of the instruction cache memory 2. At the same time, in the block group 9 of the instruction word cache memory directory 7, a predetermined data bit is loaded into a block having a predetermined column number. Also, the block having a predetermined column number in the LRU replacement information 8
Output signal 107 of U replacement information updating circuit 23
Is loaded. At this time, if the LRU replacement information update inhibition signal 125 specified by the above-mentioned HCSW instruction group has been sent from the main processing unit, the operation of the LRU replacement information updating circuit 23 is stopped, and the LRU replacement information updating circuit 23 is stopped.
The replacement information 8 is not updated, the state of the old value is maintained, and the block group 3 loaded this time is replaced.
Are replacement target blocks at the next block loading.

On the other hand, the command word cache memory buffer output data block 109 inputted to the data selection circuit 19 is generated via the low order address signal 105 inputted from the address register 1 to the command word cache memory control circuit 18. Controlled by the control signal 127 input to the data selection circuit 19, only the word to be read from the main processing device is selected, and the main processing device sends it out as read data 119. Needless to say, the instruction word cache memory control circuit 18 sends a reply signal 118 together with the read data 119 to the main processor.

At this time, if a plurality of block load requests are specified by the HCSW instruction group, the data blocks corresponding to the number of block load requests are held in the instruction word cache memory buffer device 17. Furthermore, HCSW
A buffer control signal 124 is output from the buffer device control circuit 21 in response to the block load request signal 123 specified by the instruction group a plurality of times, and a predetermined data block is stored in the instruction word cache memory buffer output data block 1.
09, the instruction word cache memory buffer device 17
Sent out. In synchronization with this, an address update signal 121 is sent from the main processor to the address update circuit 21 to generate the middle address 120 indicating the address of the above-mentioned predetermined data block, and the address register 1 is updated. . Hereinafter, the above-described operation is repeated until the number of block load requests is reached.

At this time, if an instruction cache memory block load inhibition request is issued by the HCSW instruction group, the instruction cache memory write operation inhibition request signal 122 is sent from the main processor to the instruction cache memory write control circuit. 22, the instruction cache memory write control circuit 22 outputs a write inhibit signal 128, and the write to the instruction cache memory 2 is inhibited. Needless to say, the updating of the instruction word cache memory directory 7 is also suppressed. The instruction word cache memory buffer output data block 109 at this time is sent to the data selection circuit 19, and a predetermined word is sent to the main processing unit as read data 119 by the control signal 127. The instruction word cache memory control circuit 18 also sends the reply signal 1 to the main processor in the same manner as described above.
18 is sent out.

FIG. 2 is a diagram showing an embodiment of the HCSW activation method for changing the operation at the time of block loading of the instruction word cache memory 2 before the HCSW activation according to the present invention.

In this embodiment, by tracing the pointer of each table, it is possible to arrive at a group of HCSW instructions which realize one process. Now, the start address storage table pointer 200 is set in the start address storage table 21.
It points to the beginning of 0. Start address storage table 21
0 is configured by sequentially arranging a plurality of entries. There is one entry corresponding to one process realized by the HCSW. Each entry includes a control information field 211 and a start address information field 212. The control information field 211 stores information on contents to be processed prior to the transfer to the HCSW. The control information field 211 includes the number of block loads of control information relating to the instruction cache memory, the update suppression information of LRU replacement information, and the instruction cache. It contains information on block load inhibition to memory and the like. Activation address information field 2
Reference numeral 12 stores the head address of the HCSW instruction group 220 to be executed.

Transfer to the HCSW is performed by hardware and firmware. The transfer routine to the HCSW instruction group first displays the transition to the HCSW mode as common preprocessing, and saves the instruction counter, base register, general-purpose register, or switches to the HCSW dedicated register group. Thereafter, based on the start address storage table pointer 200, an entry corresponding to the process to be executed is read out from the table 210, and by checking the control information field 211 of the entry, an individual process to be executed prior to import is performed. The start address is determined from the address information field 212 of the entry.

In the case of FIG. 2, the HCSW instruction groups 221, 22
2 and 223, the control information fields 211 in the start address storage table 210 are set as shown in the HCSW control information field setting table in Table 1. it can.

[0033]

[Table 1]

That is, the HCSW of high importance in performance
In the instruction group 221, the block load is executed a plurality of times.
Update of the LRU replacement information and block loading to the instruction cache memory are performed. As a result, the HCSW instruction group 221 operates by making full use of the instruction word cache memory.
During execution, the number of misses of the instruction word cache memory is reduced, and an improvement in performance can be expected.

Further, in the HCSW instruction group 222 of medium importance in performance, the block load is executed a plurality of times and the block load to the instruction cache memory is also executed, but the LRU replacement information is not updated.
Other more important general software and HCS
The W instruction group does not need to be evicted from the instruction word cache memory when the next block is loaded, and the instruction word cache memory is used efficiently.

Further, in the HCSW instruction group 223 having a lower degree of importance in performance, since the block load to the instruction cache memory is suppressed, the instruction word is read from the main memory device every time. There is no change in the instruction cache memory, and other general software and HCSW instructions of higher importance in performance remain held in the instruction cache memory.

As described above, the operation at the time of block loading of the instruction word cache memory is changed to an operation suitable for the importance of the performance of each HCSW instruction group before the HCSW is activated. Can be used effectively.

FIG. 3 is a diagram showing one embodiment of the HCSW operation when the operation at the time of block loading of the instruction word cache memory is changed according to the instruction of the HCSW of the present invention.

FIG. 3 shows the HCSW instruction groups 310 and 320,
Each of the HCSW instruction groups has a high, medium, and low importance. In addition, each HC
The SW instruction group includes a branch instruction 340 and HCSW support instructions 341, 342, 343 and H for changing the operation at the time of block loading of the instruction word cache memory.
An HCSW support instruction 344 for exiting the CSW mode is arranged. HCSW support instructions 341, 342,
As shown in the execution content table of the HCSW support instruction in Table 2, the contents of the change in the operation at the time of block loading of the instruction word cache memory executed in 343 are as follows.

[0040]

[Table 2]

The port instruction 341 is an operation content at the time of block loading when executing a group of HCSW instructions of higher importance in performance. The HCSW support instruction 342
Is the content of operation at the time of block loading when executing a group of HCSW instructions of medium importance in performance.
In the SW support instruction 343, HC of lower importance in performance is used.
This is the operation content at the time of block loading when executing the SW instruction group.

If the HCSW instruction group 310 is in operation, the degree of importance in performance is high. Therefore, in the operation at the time of block loading of the instruction word cache memory, the block loading is executed a plurality of times and the LRU replacement information is Is also executed, and a block load to the instruction word cache memory is also executed, so that the instruction word cache memory is fully used.

When the operation of the HCSW shifts from the HCSW instruction group 310 to the HCSW instruction group 320, the HCSW instruction group 3
In step 10, the HCSW support instruction 342 is executed, the operation at the time of block loading of the instruction cache memory is executed a plurality of times, the update operation of the LRU replacement information is suppressed, and the block loading to the instruction cache memory is executed. It is set to a content suitable for a group of HCSW instructions having a medium importance in performance. Thereafter, the branch instruction 340 is executed, and the operation of the HCSW shifts to the HCSW instruction group 320. At this time, the instruction word of the HCSW instruction group 320 is fetched, and a mishit occurs in the instruction word cache memory. A block load is performed. The operation at the time of block loading executed at this time is an operation suitable for the HCSW instruction group of medium importance in performance set by the above-described HCSW support instruction 342, and thereafter the HCSW instruction group 320 operates in this state. to continue. Further, when the operation of the HCSW is further transferred from the HCSW instruction group 320 to the HCSW instruction group 330, the HCSW support instruction 343 is executed. When the HCSW instruction group 330 operates, the operation at the time of loading the block of the instruction word cache memory has a high performance. The operation is suitable for a group of HCSW instructions of lower importance. Further, the HCSW instruction group 33
When the operation of the HCSW is shifted from 0 to the HCSW instruction group 310, the HCSW support instruction 341 is executed and the HCS
When the W instruction group 310 operates, the operation at the time of block loading of the instruction word cache memory is an operation suitable for the HCSW instruction group of higher importance in performance.

That is, the operation at the time of block loading of the instruction word cache memory is performed by the
When the operation of the HCSW is transferred to the instruction group, the operation is changed to an operation suitable for the HCSW instruction group with higher performance importance by executing the HCSW support instruction 341, and the HCSW with medium performance importance is executed. When the operation of the HCSW is transferred to the instruction group, by executing the HCSW support instruction 342, the operation is changed to the operation suitable for the HCSW instruction group having the middle importance in performance, and the HCSW having the lower importance in performance is performed. When the operation of the HCSW is transferred to the instruction group, by executing the HCSW support instruction 343, the H of lower importance in performance is executed.
The operation has been changed to be suitable for the CSW instruction group.

In order to shift from the HCSW mode to the software mode at the end of the operation of each HCSW instruction group,
The HCSW support instruction 344 for exiting the HCSW mode is executed, and the operation at the time of block loading of the instruction word cache memory is set to a predetermined operation of hardware, that is, the number of times of block loading is set to one, and the update inhibition of the LRU replacement information is released. In this case, the block load suppression to the instruction cache memory is released.

As described above, the operation at the time of block loading of the instruction cache memory is dynamically changed by the HCSW support instruction, so that the instruction cache memory can be adapted to the performance importance of each HCSW instruction group. Can be controlled.

[0047]

As described above, the cache memory control method by the hardware control software of the present invention is important in terms of performance by changing the operation at the time of block loading of the instruction word cache memory by the HCSW as necessary. In a high-order HCSW, the number of miss hits in the instruction word cache memory can be reduced by executing the block load multiple times, and the performance is improved. In the case of the HCSW with low performance importance, the update of the LRU replacement information and the block load to the instruction cache memory are suppressed, so that general software and HCSW with higher performance importance are erased from the instruction cache memory. Therefore, the instruction cache memory can be used effectively.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a cache memory control method using hardware control software according to the present invention.

FIG. 2 is a diagram illustrating an embodiment of an HCSW activation method for changing an operation at the time of block loading of an instruction cache memory before the HCSW activation in the cache memory control method by the hardware control software of the embodiment.

FIG. 3 is a diagram showing an embodiment of an HCSW operation in a case where an operation at the time of block loading of an instruction cache memory is changed according to an instruction of the HCSW in a cache memory control method by hardware control software of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Address register 2 Instruction cache memory 3, 4, 5, 6, 9, 10, 11, 12 Block group 7 Instruction cache directory 8 LRU replacement information 13, 14, 15, 16 Hit detection circuit 17 Instruction cache memory buffer Device 18 Command cache memory control circuit 19 Data selection circuit 20 Address update circuit 21 Buffer device control circuit 22 Command cache memory write control circuit 23 LRU replacement information update circuit 200 Start address storage table pointer 210 Start address storage table 211 Control information field 212 boot address information field 220, 221, 222, 223, 310, 320, 3
30 HCSW instruction group 340 Branch instruction 341, 342, 343, 344 HCSW support instruction

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 12/08 G06F 12/12 G06F 9/26

Claims (3)

(57) [Claims] 1. A hardware control software which is a routine in a machine language instruction format stored in a hardware area of a main memory device is called by a microprogram, and the hardware control software is executed by the microprogram one by one. A data processing device having a function of controlling the hardware control software instruction and the general software instruction and storing the same in the same cache memory without distinguishing between the hardware control software instruction and the general software instruction. Means for changing the number of times before the start of the hardware control software; means for arbitrarily changing the number of times by the hardware control software; The cache memory control method according to the hardware control software, characterized in that and means for changing the block load times. 2. The hardware control software which is a routine in a machine language instruction format stored in a hardware area of a main memory device is called by a microprogram, and the hardware control software is executed by the microprogram one by one. A data processing device having a function of controlling the hardware control software instruction and the general software instruction and storing the same in the same cache memory without distinguishing between the hardware control software instruction and the general software instruction. Means for suppressing an update operation of the LRU replacement information by an instruction before activation of the hardware control software, means for inhibiting the update operation of the LRU replacement information by an instruction of the hardware control software, In the wake of the completion, the LRU
Means for canceling suppression of update operation of replacement information. A cache memory control method using hardware control software. 3. A hardware control software, which is a routine in a machine language instruction format stored in a hardware area of a main memory device, is called by a microprogram, and the hardware control software is executed by the microprogram one by one. In the data processing device having a function of controlling the hardware control software instruction and the general software instruction and storing the same in the same cache memory without discriminating, the cache block load is suppressed and the instruction is executed without passing through the cache memory. Means to read words, means for instructing block load suppression before the hardware control software is activated, and means for instructing block load suppression by the hardware control software,
Means for releasing the block load inhibition upon termination of the hardware control software. A cache memory control method using hardware control software.