JP2002041358A - Processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a processor system capable of efficiently handling large stream data with small amount of locality, which does not require the increase in associability for enhancement of hit rate and can reduce power consumption. SOLUTION: In the processor system having a processor 101 and a main memory 103 to store the stream data to be processed by the processor 101, a stream buffer 102 to store a series of data as a stream is provided and a stream control part 104 to control read and write of the main memory 103 and the stream buffer 102 based on a stream instruction of the processor 101 is also provided between the processor 101 and the main memory 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a processor system (processor device) having a processor and a main memory for storing stream data processed by the processor.

[0002]

2. Description of the Related Art In a processor system using a processor such as a microprocessor or a digital signal processor (DSP), data to be processed by the processor is stored in a main memory, and an instruction of the processor is used to store data.
The necessary data is temporarily loaded from its main memory into a register and then supplied to, for example, an arithmetic unit for arithmetic processing, or the data from the main memory is directly supplied to, for example, an arithmetic unit for arithmetic operation. Processing was normal.

Incidentally, the access speed of the main memory is very slow as compared with the operation speed of the processor, and this speed difference tends to increase in recent years.
It was a shack to improve the performance of the processor system.

Therefore, in many systems using a processor, a cache memory, which has a smaller capacity than the main memory but has a high access speed, is provided between the processor and the main memory, so that the system is apparently provided. The main memory access speed was increased.

However, the cache memory is very effective for data having locality in space and time, but is useful for large-scale and low-locality stream data such as in signal processing. However, cache memories were not always suitable. That is,
When the data amount of the stream data increases, there is a problem that the capacity of the cache memory is absolutely insufficient, and there is a problem that although the capacity is sufficient, a cache miss occurs due to a problem in the configuration of the cache memory.

For example, set associative (set asso
In a cache memory of the ciative type, when different stream data or general variables are concentrated on the same set address, the associativeness of the cache memory (associati
vity) (the number of ways) is insufficient, and even though the entire cache memory has a sufficient capacity, necessary data is evicted from the cache memory and a cache miss occurs.

[0007]

SUMMARY OF THE INVENTION In view of the foregoing, the present invention provides a processor system having a processor and a main memory for storing stream data to be processed by the processor. An object of the present invention is to propose a processor system which can be handled efficiently, does not need to increase associativity for improving a hit rate, and can reduce power consumption.

[0008]

According to a first aspect of the present invention, in a processor system having a processor and a main memory storing stream data processed by the processor, a series of data is stored between the processor and the main memory. Is a processor system that is provided with a stream buffer that stores a stream as a stream, and a stream control unit that controls reading and writing of the main memory and the stream buffer based on a stream instruction of the processor.

According to the first aspect of the present invention, the main memory includes:
The stream data to be processed by the processor is stored, and the stream control unit controls reading and writing of the main memory and the stream buffer based on the stream instruction of the processor.

According to a second aspect of the present invention, in the processor system according to the first aspect of the present invention, stream data read from a main memory is sequentially stored in a stream buffer by a prefetch instruction of the processor, and the stream buffer is stored by a load instruction of the processor. Sequentially retrieves the stream data stored in the
A processor that stores stream data stored in the processor in a stream buffer according to a store instruction of the processor, and writes back the stream data stored in the stream buffer to a main memory according to a write-back instruction of the processor. System.

According to a third aspect of the present invention, in the processor system according to the first aspect of the present invention, the stream control section comprises: a boundary register for allocating a plurality of divided areas in the stream buffer to the plurality of streams; A stream pointer that holds the range of each stream data in the area, an address register that holds the main memory address for prefetching and writing back for each stream, and an increment for updating the address value after prefetching and writing back. A processor system includes a step register for holding a value and a counter for holding the number of words of stream data to be prefetched and written back.

According to a fourth aspect of the present invention, there is provided a processor system having a plurality of processors and a main memory for storing stream data processed by the plurality of processors. Is stored in multiple processors.
A main memory and a corresponding stream are provided based on a stream instruction of at least one processor among a plurality of processors. The processor system is provided with a stream control unit for controlling reading and writing of a buffer, and addresses respectively corresponding to all streams processed by a plurality of processors are individually assigned.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, a processor system (processor apparatus) according to an embodiment of the present invention will be described.
An example of the (processor circuit) will be described in detail. First, FIG.
The overall configuration of the processor system will be described with reference to FIG. In this processor system, the processor 10
1 and a main memory 103 for storing data to be processed by the processor 101.
Stream buffer 102 between main memory 103
Is provided. Further, a stream control unit 104 for controlling reading and writing of the main memory 103 and the stream buffer 102 is provided. Note that the processor 101 can be a microprocessor or a digital signal processor (DSP).

The processor 101 executes a program. The instructions to be executed include an initialization instruction for a stream, a prefetch instruction, and a load (l) instruction.
oad) instruction, store instruction and write back
back) instruction is included.

When the processor 101 executes these stream instructions, the processor 101 supplies the stream control unit 104 with control signals such as a stream ID, an address, and a command. The stream control unit 104
When these control signals are received, the stream control unit 10
4 is a stream buffer 102 and a main memory 10
3 controls read and write. As a result, stream data is transferred between the stream buffer 102, the main memory 103, and the processor 101.

The stream buffer 102 is an SRAM
(Static RAM) or DRAM (dynamic R)
AM) and is controlled by read and write commands from the stream control unit 104.

Next, an example of a specific configuration of the stream control unit 104 in FIG. 1 will be described with reference to FIG. The stream control unit 104 includes a boundary register 2 composed of n registers for managing a plurality of n streams.
01, stream pointer 20 consisting of n registers
Address register 203, n consisting of 2, n registers
A step register 204 comprising n registers and a counter 205 comprising n counters.

The stream buffer 102 has n streams.
It is divided into n areas corresponding to the reams. Boun
Dali register 201 has a register B₀, B₁, ‥‥‥
‥, B _n-1From the stream for n streams.
Of the area divided into a plurality of n pieces of the trim buffer 102
Specify. Of streams 0, 1, 2,.
For example, the starting point of the area assigned to stream 3
Is register B_TwoAnd the end point is register B_ThreeSpecify with
You. However, the starting point of stream 0 is the stream buffer
Filer 102.

The stream pointer 202 is composed of registers of three fields of V, TOP and TAIL for each of n streams. V indicates the presence or absence of data in the corresponding stream data. For example, V =
If 0, the stream data is empty, and if V = 1, it indicates that stream data exists. TOP and TAIL indicate the start point and the end point next to the end of the stream data in the areas respectively allocated to the n streams in the stream buffer 102.

The address register 203 holds the address of the main memory 103 when prefetching and writing back the stream data to the main memory 103. The step register 204 stores the main memory 10
For 3, the increment of the address of the main memory 103 at the time of prefetching or writing back a plurality of words of stream data is specified in word units. For example, when the value of the step register 204 is 1, continuous words on the main memory 103 are prefetched or written back to consecutive words on the main memory 103, and when the value is 2, every other word is executed.

The operation of the stream control unit 104 when the processor 101 executes each stream instruction will be described below in detail. When the processor 101 executes the stream initialization instruction, the stream ID specified by the instruction and the pointer value indicating the boundary point are stored in the processor 10.
1 to the stream control unit 104. The stream control unit 104 sets a pointer value in a register specified by the stream ID of the boundary register 201. At the same time, the stream control unit 104 clears the V register specified by the stream ID of the stream pointer 202 to 0, and sets the register of TOP and the register of TAIL at the head of the allocated area.

When the processor 101 executes a stream data prefetch instruction, the stream ID specified by the instruction, the prefetch start address of the main memory 103, the step value, and the number of prefetch words are passed from the processor 101 to the stream control unit 104. The stream control unit 101 sets an address, a step value, and the number of words in each of the registers specified by the stream IDs of the address register 203, the step register 204, and the counter 205, and starts prefetch to the main memory 103. Normally, prefetch is performed on the main memory 103 in units of blocks, similarly to blocks (or lines) in the cache memory. However, in the case of prefetching in block units when the value of the step register 204 is equal to or more than a certain value, prefetching is performed in word units when the efficiency is reduced due to unnecessary word reading.

The block data read out from the main memory 103 is temporarily stored in the latch 105, and is stored in the step register 20 from words included in the block.
Only the word designated by 4 is selected, read from the latch 105, and written to the stream buffer 102.

Then, 1 is set to the V register of the stream pointer 202, and the TAIL register is incremented by the number of words written. Further, the address register 203 is incremented by the block size read from the main memory 103, and the counter 205 is decremented by the number of words written in the stream buffer 102. Then, the count content of the counter 205 is 0.
The above-mentioned prefetch operation is repeated until.

When the updated value of the TAIL of the stream pointer 202 matches the end point of the boundary register 201, it returns to the start point and continues updating. Hereinafter, the same applies to the updating of TOP in other instructions.

The contents of the V register of the stream pointer 202 are 1, and the contents of the TAIL register and TO
If the contents of the register of P match, the prefetch is interrupted until a free area is created, the stream data is consumed by loading or the like, and after the free space is created, the prefetch is restarted.

Next, the prefetch operation when the value of the step register 204 is 2 will be described with reference to FIG. Based on the address of the register of the address register 203, the main memory 103 is prefetched in block units (1), and the read data from the main memory 103 is latched in the latch 105 (2), and the step register 2
The stream data is selected according to the address increment in the register 04 (3), the selected stream data is written to the stream buffer 102 (4), and the contents of the stream pointer 202, the address register 203 and the counter 205 are updated. Yes (5).

When the processor 101 executes a stream data load instruction, the stream I specified by the instruction is executed.
D is passed from the processor 101 to the stream control unit 104. The stream control unit 104 checks the register specified by the stream ID of the stream pointer 202. If the contents of the V register of the stream pointer 202 is 1, 1 from the point indicated by the TOP register
The word is read out and returned to the processor 101, and the TOP register is incremented by one word. If the content of the V register of the stream pointer 202 is 0, the load is discarded and an error is returned to the processor 101. When the contents of the TOP register are updated to match the contents of the TAIL register, the contents of the V register are set to 0.

When the processor 101 executes a stream data store instruction, the stream I specified by the instruction is executed.
D is passed from the processor 101 to the stream control unit 104. The stream control unit 104 checks the register specified by the stream ID of the stream pointer 202. If the contents of the V register are 1 and the contents of the TOP register match the contents of the TAIL register, the store is discarded and an error is returned to the processor 101. In other cases, the store data is written to the stream buffer 102 pointed to by the TAIL register, the content of the V register is set to 1, and the content of the TAIL register is incremented by one word.

When the processor 101 executes a stream data write-back instruction, the stream ID, write-back start address, step value, and number of write-back words specified by the instruction are passed from the processor 101 to the stream control unit 104. Stream control unit 1
04 is an address register 203, a step register 2
The address, the step value, and the number of words are set in each register designated by the stream ID 04 and the stream ID of the counter 205, and write back to the main memory 103 is started. Normally, write back is performed in the main memory 10
3, the block is read out from the location indicated by the TOP register of the stream pointer 203 and transferred to the main memory 103. The contents of each of the TOP register of the stream pointer 202, the address register 203, and the counter 205 are updated, and the write-back operation is repeated until the count of the counter 205 becomes zero. If all data existing in the stream is written back before the count of the counter 205 becomes 0 (the contents of the TOP register of the stream pointer 202 and the contents of the TAIL register match), the stream pointer 202
Is set to 0, and the write-back operation is suspended until data is newly stored in the stream.

Next, another example of the processor system according to the embodiment of the present invention will be described with reference to FIG.
The description of the processor system with reference to FIG. In the example of the processor system shown in FIG. 4, a plurality of processors and stream buffers respectively corresponding to the plurality of processors are provided, and the plurality of stream buffers are shared by the plurality of processors.

The m processors 101-1 and 101-
, 101-m, and stream buffers 102-1, 102-2,..., 1 shared by the m processors.
02-m and stream control units 104-1, 104-2,.
104-m. The m stream buffers 102-1, 102-2,..., 102-m
Are connected to the main memory 103 via the shared bus 401. Note that, instead of the shared bus 401, an interconnection network such as a cross bus switch can be provided. m
Stream buffers 102-1, 102-2,.
‥‥ and 102-m are connected to the shared bus 401 via latches, respectively, although not shown.

The m processors 101-1 and 101-
Addresses respectively corresponding to all the streams processed by 2,..., 101-m are individually assigned.

The m processors 101-1 and 101-
2, ‥‥‥‥, 101-m are their own stream buffers 102-1, 102-2, ‥‥‥‥, 102, respectively.
Accessing -m is the same as described above. However,
Executing a load instruction on an empty stream buffer,
Regarding the execution of the store instruction for the full stream buffer, the stream control unit 104 does not return an error to each processor and suspends the execution until the execution becomes possible.

The m processors 101-1 and 101-
When 2, 2, 101-m accesses a stream buffer corresponding to another processor, the access is performed according to a memory map. That is, for the address assigned to the stream to be accessed, loading,
Issue a store instruction.

A description will be given also with reference to FIG. 6 showing an additional part of the specific configuration of the stream control unit 104 in FIG. Stream control units 104-1, 104-2,..., 104
-M is assigned a predetermined address in advance to each of the n streams managed by the respective stream base address registers 207.
Is held in. Stream control units 104-1, 10
4-2, ‥‥‥‥‥, 104-m are shared bus 401
(Or processors 101-1, 101-2,...,
The comparator 208 compares the upper bits of the load / store address from 101-m) with the contents of the stream base address register 207. If they match, it is determined that the stream is accessed. Using the lower bits of the address as the stream ID, one stream is selected from n streams and accessed.

In FIG. 4, for example, the processor 101
-2 issues a load to the address of the stream buffer 102-1 managed by the processor 101-1.
The data is extracted from the stream buffer 102-1 corresponding to 01-1, and returned to the processor 101-2.
Further, the processor 101-m issues a store to the address of the stream buffer 102-2 managed by the processor 101-2, and the stream buffer 102-2 of the processor 101-2 receives the stored data, and Write data to buffer 102-2.

As shown in FIG. 5, in a processor system having the same configuration as that of FIG. 4, by prefetching or writing back a stream buffer to an address to which a stream is mapped, it is possible to cope with different processors. Data can be transferred between stream buffers.

According to this example of the processor system, since the stream buffer is used instead of the cache, there are the following advantages as compared with the processor system using the cache.

When handling data of a large-scale stream with low locality, a cache causes a cache miss due to competition between data of a plurality of streams or competition between data of a stream and data of a general variable. Performance tends to decrease. However, since no contention occurs in the stream buffer, the processor system using the stream buffer has higher performance than the processor system using the cache.

In a processor system using a cache, in order to reduce contention in the cache, associativity is increased. However, power consumption during cache access increases. In a processor system using a stream buffer, power consumption does not increase when accessing the stream buffer, which is advantageous over a processor system using a cache.

Since the cache manages data on a block (line) basis, data unnecessary for the operation may be taken into the cache together, and the cache capacity is wasted. However, in the stream buffer, only necessary data is taken into the stream buffer as much as possible, so that the buffer capacity can be effectively utilized.

By sharing the stream buffer among a plurality of processors, data communication between the processors can be performed without special synchronization processing.

[0044]

According to the first aspect of the present invention, a processor,
And a main memory for storing stream data processed by the processor.
In a processor system having a processor and a main memory for storing stream data processed by the processor, a stream buffer for storing a series of data as a stream is provided between the processor and the main memory, and a stream instruction for the processor is provided. A stream control unit is provided for controlling the reading and writing of the main memory and the stream buffer on the basis of the stream data, so that large-scale and less-localized stream data can be efficiently handled, and the associativity for improving the hit ratio can be improved. There is no need to increase the number, and a processor system capable of reducing power consumption can be obtained.

According to a second aspect of the present invention, in the processor system of the first aspect of the present invention, stream data read from the main memory is sequentially stored in a stream buffer by a prefetch instruction of the processor, and is loaded by a load instruction of the processor. The stream data stored in the stream buffer is sequentially taken out and passed to the processor, the stream data stored in the processor is stored in the stream buffer by the store instruction of the processor, and the stream buffer is stored in the stream buffer by the write back instruction of the processor. Is written back to the main memory, it is possible to obtain a processor system having the same effects as the first embodiment of the present invention.

According to a third aspect of the present invention, in the processor system according to the first aspect of the present invention, the stream control unit comprises: a boundary register for allocating a plurality of divided areas in the stream buffer to the plurality of streams; A stream pointer for holding an existing range of each stream data in a plurality of areas, an address register for holding an address of a main memory for prefetching and writing back to each stream, and an address register for updating an address value after prefetching and writeback. Since a step register for holding an increment value and a counter for holding the number of words of stream data to be prefetched and written back are provided, it is possible to obtain a processor system having the same effects as those of the first invention.

According to the fourth aspect of the present invention, in a processor system having a plurality of processors and a main memory for storing stream data processed by the plurality of processors,
A plurality of stream buffers, each of which stores stream data, are provided with a plurality of stream buffers corresponding to a one-to-one correspondence, and a plurality of stream buffers are provided one-to-one corresponding to stream instructions of an arbitrary processor among the plurality of processors. And a stream control unit for controlling the reading and writing of the main memory and the corresponding stream buffer based on the main memory. The addresses corresponding to all the streams processed by the plurality of processors are individually assigned, so that a large scale Stream data with low locality can be handled efficiently, there is no need to increase associativity for improving the hit rate, and a processor system capable of reducing power consumption can be obtained. Share multiple stream buffers And it allows the data communication between a plurality of processors without special synchronization process, it is possible to obtain a processor system that can perform a stream instruction only.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a processor system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a specific configuration example of a stream control unit in the processor system of FIG. 1;

FIG. 3 is a block diagram illustrating a prefetch operation of the stream control unit in FIG. 2;

FIG. 4 is a block diagram showing another example of the processor system according to the embodiment of the present invention, together with an explanation of a part of the operation;

FIG. 5 is a block diagram showing another example of the processor system according to the embodiment of the present invention, together with a description of some other operations;

FIG. 6 is a block diagram showing an additional part of a specific configuration example of the stream control unit in FIG. 2;

[Explanation of symbols]

101 processor, 102 stream buffer, 1
03 Main memory, 104 Stream control unit, 10
5 Latch.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 9/38 310 G06F 9/38 310A 15/16 645 15/16 645

Claims (4)

[Claims] 1. A processor system having a processor and a main memory for storing stream data processed by the processor, wherein a stream buffer for storing a series of data as a stream is provided between the processor and the main memory. And a stream control unit for controlling reading and writing of the main memory and the stream buffer based on a stream instruction of the processor. 2. The processor system according to claim 1, wherein stream data read from said main memory is sequentially stored in said stream buffer by a prefetch instruction of said processor, and said stream buffer is stored by said load instruction of said processor. The stream data stored in the processor is sequentially taken out and passed to the processor, and the stream data stored in the processor is stored in the stream buffer by a store instruction of the processor, and the stream data is stored in the stream buffer by the write back instruction of the processor. A processor system, wherein stream data stored in a stream buffer is written back to the main memory. 3. The processor system according to claim 1, wherein the stream control unit is configured to assign a plurality of divided areas in the stream buffer to a plurality of streams, and a plurality of areas of the stream buffer. A stream pointer for holding the range of each stream data within the address, an address register for holding the address of the main memory for prefetching and writing back for each stream, and an increment value for updating the address value after prefetching and writeback And a counter for holding the number of words of stream data to be prefetched and written back. 4. A processor system having a plurality of processors and a main memory for storing stream data processed by the plurality of processors, wherein the stream data is stored between the plurality of processors and the main memory. Providing a plurality of stream buffers corresponding to the plurality of processors on a one-to-one basis, and corresponding to the plurality of stream buffers on a one-to-one basis, based on a stream instruction of any of the plurality of processors, A stream control unit for controlling reading and writing of the main memory and the corresponding stream buffer is provided, and addresses respectively corresponding to all streams processed by the plurality of processors are individually assigned. Processor system.