JP2967477B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device using an insulated gate field effect transistor.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor devices, miniaturization of element dimensions is progressing. It is known that in miniaturization of an insulated gate field effect transistor (hereinafter also referred to as MOSTr), a short channel effect becomes a problem.
As one method of suppressing the single-channel effect, it has been considered to reduce the depth of the source and drain diffusion layers of the transistor.

However, in the method of simply making the diffusion layer shallow,
There are problems such as an increase in the sheet resistance of the diffusion layer and an increase in the contact resistance between the wiring material and the diffusion layer. Therefore, FIG.
As shown in FIG. 3A and the MOS Tr shown in FIG. 3B, a structure in which a region serving as a diffusion layer of the source 106 and the drain 107 and the gate electrode 104 on the gate oxide film 103 are simultaneously raised by selective Si film 108 growth. Proposed. On the side wall of the gate electrode 104, a side wall oxide film 105 is formed.

Further, as shown in FIG.
A method has been proposed in which a metal is deposited after being raised by growth, and this metal is silicidized as a silicide film 11 by annealing. According to the method shown in FIG. 3, it is possible to simultaneously form a shallow diffusion layer and reduce the resistance.

Further, by depositing a silicon nitride film having high etching resistance in the pretreatment for epitaxial growth on the surface of the oxide film as a sidewall of the gate electrode, it is possible to prevent the lower portion of the sidewall from being etched in the pretreatment for growth. A method of suppressing the short circuit between the gate, the source and the drain to prevent the short circuit has also been devised (JP-A-63-16627).

[0006]

However, in the above-mentioned conventional method, the source and drain regions and the gate electrode are simultaneously raised by using selective silicon growth. Usually, in a process using selective growth, silicon may be deposited on an insulating film due to a loss of selectivity. For example, in a selective silicon growth process on a source region, a drain region, and a gate electrode of a MOS Tr, when silicon crystal grains grow on an uncolored edge film of a gate sidewall due to a loss of selectivity, the gate electrode and the source region There is a possibility that the silicon crystal grains may electrically short between the gate electrodes or between the gate electrode and the drain region.

In particular, when a thick rising film is required, the distance between the gate electrode and the source region and the drain region is substantially shortened, so that an electrical short circuit occurs due to smaller-sized crystal grains. become. As a result, there is a problem that a leak current increases due to a short circuit between the gate electrode and the source region or the drain region.

The present invention has been made under such a background. In a MOS Tr using a lift-up process, a leakage current due to a short circuit between a gate electrode and a source region or a drain region is small, and the manufacturing of the MOS Tr is simplified. Provided is a method for manufacturing a MOS Tr that improves yield and reliability.

[0009]

According to the first aspect of the present invention,
In a method of manufacturing a semiconductor device, a gate insulating film forming step of forming a gate insulating film in a predetermined region on an upper surface of a Si substrate;
A gate electrode forming step of forming a gate electrode on the upper surface of the gate insulating film, and a sidewall forming step of forming a sidewall made of an insulating film on a side wall of the gate electrode;
S for selectively growing a Si film on the exposed Si surface
an i-film growth step, a Si-film oxidation step of oxidizing the Si film, an oxide-film removal step of etching away part or all of the oxidized region, and a metal-film growth step of growing a metal film on the upper surface of the Si substrate. An annealing step of silicidizing the metal film on the upper surface of the Si film from which the oxide film has been removed;
Removing an unreacted metal film on the insulating film.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, Ti is used as the metal film.
It is characterized in that any one of W, Mo and Co is used.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, a gate insulating film forming step of forming a gate insulating film in a predetermined region on the upper surface of the Si substrate, and forming a gate electrode on the upper surface of the gate insulating film. A gate electrode forming step;
A sidewall forming step of forming a first sidewall made of a silicon oxide film on a side wall of the gate electrode;
S for selectively growing a Si film on the exposed Si surface
an i-film growing step, a Si film oxidizing step of oxidizing the Si film, an etching step of removing a region oxidized in the Si film oxidizing step and the first side wall by etching, Forming a second sidewall made of an insulating film on the substrate;
A metal film growing step of growing a metal film on the substrate, an annealing step of silicidizing the metal film on the upper surface of the Si film from which the oxide film has been removed, and an unreacted metal removing the unreacted metal film on the insulating film And a film removing step.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, Ti is used as the metal film.
It is characterized in that any one of W, Mo and Co is used.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, there is provided a gate insulating film forming step of forming a gate insulating film in a predetermined region on an upper surface of a Si substrate, and forming a gate electrode on the upper surface of the gate insulating film. An electrode forming step, a side wall forming step of forming a side wall made of a silicon nitride film on a side wall of the gate electrode, a Si film growing step of selectively growing a Si film on an exposed Si surface, A Si film oxidation step of oxidizing the film, an oxide film removal step of etching away part or all of the oxidized region, a metal film growth step of growing a metal film on the upper surface of the Si substrate, and a Si film having the oxide film removed. An annealing process for silicidizing the metal film on the upper surface of the film and an unreacted metal film removing process for removing the unreacted metal film on the insulating film. .

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, Ti is used as the metal film.
It is characterized in that any one of W, Mo and Co is used.

[0015]

Next, a method for manufacturing a semiconductor according to an embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 3 is a cross-sectional view of a MOS Tr showing a manufacturing process of a method for manufacturing an OS Tr.

First, as shown in FIG. 1A, N-type S
After forming an element isolation oxide film (LOCOS) 2 on the i-substrate 1, a silicon oxide film having a thickness of 8 nm is formed by, for example, a thermal oxidation method. Then, a 200 nm-thick polysilicon (polycrystalline silicon) film is grown on the silicon oxide film surface by a CVD (chemical vapor deposition) method.

Next, patterning is performed by a photolithography technique to form a gate oxide film 3 from the silicon oxide film and a gate electrode 4 from the polysilicon.
Then, after a Si oxide film is grown to a thickness of 80 nm by the CVD method, etch back by anisotropic dry etching is performed to form a sidewall oxide film 5a.

Next, BF ₂ ions are implanted into the Si substrate 1 by ion implantation under the conditions of an acceleration voltage of 3 KeV and an area concentration of 1 × 10 ¹⁵ / cm ² . Then, an annealing process at 1000 ° C. is performed in a nitrogen atmosphere to activate the implanted B atoms, thereby forming diffusion layers of the source 6 and the drain 7.

Next, as shown in FIG. 1B, a selective Si film 8 is selectively grown on the Si substrate 1 and the gate electrode 4. In one embodiment, the selective growth of the selective Si film 8 is performed by a UHV (ultra-high vacuum) -capable of achieving an ultimate vacuum of 1 × 10 ⁻¹⁰ Torr and an evacuation speed of the growth chamber of 500 liter / sec (in terms of N ₂ ). This is performed using a CVD apparatus. First, the Si substrate 1 is subjected to a dilute HF (diluted hydrogen fluoride solution) treatment, a pure water rinse (pure cleaning) treatment, and a drying treatment, and then introduced into a UHV-CVD apparatus.

The Si substrate 1 is annealed at 800 ° C. in a high vacuum in a growth chamber of a UHV-CVD apparatus. Thereby, the natural oxide film on the surface of the Si substrate 1 is removed by this annealing process. The substrate temperature of the Si substrate 1 is set to 650 ° C. Further, 5 sccm of Si ₂ H ₆ gas is supplied into the growth chamber in the UHV-CVD apparatus. As a result,
The selective Si film 8 is formed on the Si substrate 1 and the gate electrode 4 by 80
grown to a thickness of nm.

Next, as shown in FIG.
On the surface of the film 8, a 20 nm-thick Si
An oxide film 9 is formed.

Next, as shown in FIG. 1D, the oxide region on the surface of the selective Si film 8 and the gate sidewall oxide film 5a are removed by etching the oxide film with a dilute HF solution. Then, the Si oxide film is again formed to 80 nm by the CVD method.
Grown in thickness. Next, the Si oxide film is etched back by anisotropic dry etching to form a sidewall oxide film 5b. Then, a Ti film 10 is deposited on the entire surface by sputtering.

Next, as shown in FIG. 1E, the Ti film and the Si film react by annealing at a predetermined temperature, and a Ti silicide film 11 is formed. Then, the unreacted Ti film on the insulating film is removed by etching. Thereafter, a MOS Tr is formed through a process of forming an interlayer insulating film and a wiring process using a known process.

As described above, one embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and a process change or the like may be made without departing from the gist of the present invention. The present invention is also included in the present invention. Next, a semiconductor manufacturing process according to a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view of the MOS Tr showing a manufacturing process of the method for manufacturing the MOS Tr.

First, as shown in FIG. 2A, an element isolation oxide film (LOCOS) 2, a gate oxide film 3 and a gate electrode 4 are formed on a Si substrate 1 by using the same process as in the first embodiment. Form. Next, an Si nitride film is deposited to a thickness of 80 nm by a CVD method. Then, etch back by anisotropic dry etching is performed to form the sidewall nitride film 5.

Next, BF ₂ ions are implanted into the Si substrate 1 by ion implantation under the conditions of an acceleration voltage of 30 keV and an area concentration of 1 × 10 ¹⁵ / cm ² . Then, an annealing process at 1000 ° C. is performed in a nitrogen atmosphere to activate the B atoms implanted into the Si substrate 1. Thus, source 6
And a diffusion region for the drain 7 is formed.

Next, as shown in FIG. 2B, a selective Si film 8 is grown on the Si substrate 1 and the gate electrode 4 to a thickness of 80 nm using the same process as in the first embodiment.

Next, as shown in FIG. 2C, the selective Si film 8 on the Si substrate 1 and the gate electrode 4 is formed by a thermal oxidation method.
An Si oxide film 9 is formed with a thickness of 20 nm.

Next, as shown in FIG. 2D, an oxide film is etched with a dilute HF solution to remove an oxidized region in the Si substrate 1 and the selective Si film 8 on the gate electrode 4. Then, a Ti film 10 is deposited on the entire surface of the Si substrate 1 by a sputtering method.

In this embodiment, the sidewall nitride film 12 uses a nitride film as an insulating film. Therefore, H
The sidewall nitride film 12 is not removed during the F process. Thus, unlike the case of the oxide film sidewall in one embodiment, it is not necessary to replace the sidewall film after the HF treatment. However, since the selectivity between the Si film and the nitride film is lower than that of the oxide film, care must be taken when growing a thick elevated film.

Next, as shown in FIG. 2E, in the annealing process, the Ti film 10 reacts with the selective Si 8 to form the Ti silicide film 11. Next, after the annealing treatment, the unreacted Ti film 10 on the insulating film is removed by etching. After that, through the formation of an interlayer insulating film and a wiring process using a well-known process, the MOS
Tr is formed.

In the first embodiment and the second embodiment, the embodiments related to the PMOS Tr (p-channel MOS transistor) have been described.
NMOS Tr (n-channel MOS transistor)
Needless to say, the present invention can also be implemented in a CMOS Tr (complementary MOS transistor). In addition, although Ti has been described as the metal formed after the selective Si film growth, W, Co, Mo, and the like can be used. In the first embodiment and the second embodiment,
Although the selective growth of the selective Si film by UHV-CVD has been described, the same effect can be obtained when the selective growth is performed by LPCVD (low-pressure CVD).

As described above, after forming the gate sidewall, the Si film is selectively formed. On this occasion,
There is a possibility that selectivity is lost and Si crystal grains are formed on the insulating film. However, in the present invention, by oxidizing the substrate in the next step, the Si crystal grains formed on the gate sidewall insulating film are oxidized and turned into an insulator. As a result, there is an effect that shorts between the gate electrode and the source region and between the gate electrode and the drain region can be prevented. Thus, leakage current between the gate electrode and the source region or between the gate electrode and the drain region can be reduced.

[0034]

According to the present invention, after the poly-Si crystal grains formed on the sidewalls are thermally oxidized when the selectivity is lost due to a change in process conditions such as selective growth of the Si film with respect to the Si substrate, etc. Since the oxide film is removed by etching, the leakage current between the gate electrode and the source region or between the gate electrode and the drain region of the MOS Tr is reduced, and the effect of improving the yield rate and the reliability in the manufacture of the MOS Tr is improved. is there.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

[Description of Signs] 1 Si substrate (silicon substrate) 2 element isolation oxide film 3 gate oxide film 4 gate electrode 5a, 5b sidewall oxide film 6 source 7 drain 8 selective Si film 9 Si oxide film 10 Ti film 11 Ti silicide film 12 Sidewall nitride film

Claims (6)

(57) [Claims] A gate insulating film forming step of forming a gate insulating film on a predetermined region of an upper surface of a Si substrate; a gate electrode forming step of forming a gate electrode on an upper surface of the gate insulating film; Forming a sidewall made of a silicon film, and selectively growing a Si film on an exposed Si surface.
an i-film growing step, a Si film oxidizing step of oxidizing the Si film, an oxide film removing step of etching away part or all of an oxidized region, and a metal film growing step of growing a metal film on the upper surface of the Si substrate. A semiconductor process comprising: an annealing process for silicidizing the metal film on the upper surface of the Si film from which the oxide film has been removed; and an unreacted metal film removing process for removing an unreacted metal film on the insulating film. Device manufacturing method. 2. The method according to claim 1, wherein any one of Ti, W, Mo and Co is used as said metal film. A gate insulating film forming step of forming a gate insulating film on a predetermined region of the upper surface of the Si substrate; a gate electrode forming step of forming a gate electrode on the upper surface of the gate insulating film; A sidewall forming step of forming a first sidewall made of a film, and a step of selectively growing a Si film on the exposed Si surface.
an i-film growth step; a Si film oxidation step of oxidizing the Si film; an etching step of removing the region oxidized in the Si film oxidation step and the first sidewall by etching; Forming a second sidewall made of an insulating film on the silicon substrate, growing a semiconductor metal film on the upper surface of the Si substrate, and silicidizing the metal film on the upper surface of the Si film from which the oxide film has been removed. A method for manufacturing a semiconductor device, comprising: an annealing treatment step; and an unreacted metal film removing step of removing an unreacted metal film on an insulating film. 4. The method according to claim 3, wherein any one of Ti, W, Mo and Co is used as the metal film. 5. A gate insulating film forming step of forming a gate insulating film on a predetermined region of an upper surface of a Si substrate, a gate electrode forming step of forming a gate electrode on an upper surface of the gate insulating film, and silicon nitride on a side wall of the gate electrode. Forming a sidewall made of a film, and selectively growing a Si film on the exposed Si surface.
an i-film growth step; a Si film oxidation step of oxidizing the Si film; an oxide film removal step of etching away part or all of an oxidized region; and a metal film growth step of growing a metal film on the upper surface of the Si substrate And an annealing process for silicidizing the metal film on the upper surface of the Si film from which the oxide film has been removed, and an unreacted metal film removing process for removing the unreacted metal film on the insulating film. A method for manufacturing a semiconductor device. 6. The method according to claim 5, wherein any one of Ti, W, Mo and Co is used as the metal film.