CN103137480B - Forming method of metal oxide semiconductor (MOS) device and MOS device formed through method - Google Patents
Forming method of metal oxide semiconductor (MOS) device and MOS device formed through method Download PDFInfo
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Abstract
The invention provides a forming method of a metal oxide semiconductor (MOS) device. The forming method comprises first providing a semiconductor substrate at least comprising three regions, enabling a first region to be used for forming a gate region, enabling a second region and a third region which are adjacent to the first region to be respectively used for forming a source region and a drain region; utilizing an epitaxial method to the semiconductor substrate of the first region to extend outwards to grow an epitaxial layer; then utilizing an isotropic etching method to etch the epitaxial layer to form a channel region; then utilizing the epitaxial method to grow silicon-germanium in the second region and the third region, and respectively forming a silicon-germanium source region structure and a drain region structure; and then doping the silicon-germanium source region structure and the drain region structure. The invention further provides the MOS device formed by utilizing the method. Due to the technical scheme, damage to a silicon substrate caused by etching of the source region and the drain region in a conventional method is avoided, the goal of reducing defects is achieved, and electric leakage of the formed MOS device in the using process cannot occur easily.
Description
Technical field
The present invention relates to field of semiconductor manufacture, a kind of formation method particularly relating to MOS device and the MOS device utilizing said method to be formed.
Background technology
MOS device is one of primary element in integrated circuit.In recent years, occurred in semicon industry that employing silicon-germanium improves MOS device performance as source, drain electrode.Known, when uniaxial compressive directly puts on the channel region of transistor from silicon-germanium source region and drain region, the performance of PMOS transistor can be improved.When uniaxial tensile strain is added on channel region, the performance of nmos pass transistor can be improved.
Fig. 1 is to Figure 3 shows that each structural representation formed in the making step of employing of the prior art silicon-germanium as the MOS device of source, drain electrode.First, with reference to figure 1, be depicted as the sectional view of common MOS structure.Particularly, this structure comprises: Semiconductor substrate 10, form gate insulator 11 over the substrate 10 and grid 12, and the side of this gate insulator 11 and grid 12 is formed with insulative sidewall 13.Then, with reference to figure 2, utilize autoregistration, dry etching removes the part semiconductor substrate 10 of source electrode and drain region, in order to follow-up formation silicon-germanium source electrode and drain electrode.Then, with reference to figure 3, etch in above-mentioned steps on the region of formation, utilize epitaxy grown silicon-germanium, to form source electrode 14 and drain electrode 15 structures.
But the present inventor finds, above-mentioned way exists some defects, particularly, in Fig. 2 etching process, in Semiconductor substrate 10, namely source electrode and drain region respectively with the junction of Semiconductor substrate 10, the especially region at angle, can form some defects.And when subsequent ion injects formation doped region, too fast for preventing ion from spreading in silicon-germanium, low temperature control need be carried out to this source electrode and drain electrode, and this defect can not be repaired very well at this low temperature, be brought in MOS device as defect.In use, easily generation source region and drain region are to leaky in substrate, cause the degradation of device for this MOS device.
In view of this, be necessary a kind of formation method proposing new MOS device in fact, solve existing MOS device in manufacturing process, source electrode and drain electrode existing defects, in use there will be leaky.
Summary of the invention
The problem that the present invention solves is a kind of formation method proposing new MOS device, solves existing MOS device in manufacturing process, and source electrode and drain electrode existing defects, in use there will be leaky.
For solving the problem, the invention provides a kind of formation method of MOS device, comprising:
Semiconductor substrate is provided; Described Semiconductor substrate at least comprises three regions, and wherein, first area is for the formation of gate regions, and the second area adjacent with first area, the 3rd region are respectively used to form source region and drain region;
Utilize epitaxy that the Semiconductor substrate of described first area is stretched out and grow epitaxial loayer;
Utilize isotropic etching method to etch described epitaxial loayer and form channel region;
Utilize epitaxy at second area, the 3rd region growing silicon-germanium, form silicon-germanium source structure, drain structure respectively;
Described silicon-germanium source structure, drain structure are adulterated.
Alternatively, described silicon-germanium source structure, drain structure are carried out to doping step and comprised light dope and heavy doping, form light doping section and heavily doped region respectively.
Alternatively, utilize epitaxy to grow epitaxial loayer step to comprise:
Form the first dielectric layer and the second dielectric layer on the semiconductor substrate successively; Described first dielectric layer is different from described second dielectric layer material;
Second dielectric layer defines area of grid; Described first dielectric layer and the second dielectric layer of removing described area of grid form the first opening;
Utilize epitaxy to grow described epitaxial loayer in described first opening, described epitaxial loayer does not fill completely described first opening;
Deposit the 3rd dielectric layer the 3rd dielectric layer removed outside described first opening, described 3rd dielectric layer is different from described second dielectric layer material;
Remove second dielectric layer in described second area and the 3rd region.
Alternatively, after utilizing isotropic etching method to etch described epitaxially grown Semiconductor substrate formation channel region step, also carry out the first dielectric layer step removing second area, the 3rd region, carry out afterwards utilizing epitaxy at second area, the 3rd region growing silicon-germanium, form silicon-germanium source structure, drain structure respectively.
Alternatively, utilize epitaxy at second area, the 3rd region growing silicon-germanium, after forming silicon-germanium source structure, drain structure step respectively, before heavy doping step is carried out to described silicon-germanium source structure, drain structure, also carry out:
Described silicon-germanium source structure, drain structure and described 3rd dielectric layer form the 4th dielectric layer and carry out being polished to and exposes described 3rd dielectric layer; Described 4th dielectric layer is different from described 3rd dielectric layer material;
Remove described 3rd dielectric layer to form the second opening;
Deposit gate insulator material and grid material are to form gate insulator and grid layer, and the gate insulator material removed outside the second opening and grid material;
Remove described 4th dielectric layer in described silicon-germanium source structure, drain structure.
Alternatively, described silicon-germanium source structure, drain structure are carried out doping step and are comprised:
Light dope is carried out to described silicon-germanium source structure, drain structure;
Side wall is formed at the dual-side of described gate insulator and grid layer;
Heavy doping is carried out to described silicon-germanium source structure, drain structure, under making described side wall, forms light doping section, in remaining described silicon-germanium source structure, drain structure, form heavily doped region.
Alternatively, after removing described 4th dielectric layer step in described silicon-germanium source structure, drain structure, before carrying out light dope to described silicon-germanium source structure, drain structure, also carry out forming sidewall step at the dual-side of described gate insulator and grid layer.
Alternatively, described MOS device is P type MOS device, in described light dope and described heavy doping step, is all boron ion implantation.
Alternatively, described first dielectric layer material is silicon dioxide, described second dielectric layer material is silicon nitride, described 3rd dielectric layer material is also silicon dioxide, described 4th dielectric layer material is silicon nitride, utilizes phosphoric acid to carry out the second area on the described area of grid both sides of described removal, second dielectric layer step in the 3rd region.
Alternatively, HF acid is utilized to carry out first dielectric layer step in described removal second area, the 3rd region.
Alternatively, HF acid is utilized to carry out described 3rd dielectric layer of described removal to form the second opening procedure.
Alternatively, described 4th dielectric layer step that phosphoric acid carries out in described removal described silicon-germanium source structure, drain structure is utilized.
Alternatively, in deposit gate insulator material and grid material the gate insulator material removed outside the second opening and grid material step, described gate insulator material is silicon dioxide, and described grid material is polysilicon.
Alternatively, utilize isotropic etching method to etch described epitaxially grown Semiconductor substrate and formed in the step of channel region, described isotropic etching method etching adopts wet etching, and etching agent is the mixture of HF, HNO3, acetic acid.
Alternatively, utilize isotropic etching method to etch described epitaxially grown Semiconductor substrate and formed in the step of channel region, described isotropic etching method etching adopts dry etching, and etching agent is SF
6or CF
4.
The present invention also provides a kind of MOS device, is formed by the forming method of MOS device of foregoing description.
Compared with prior art, the present invention has the following advantages: first utilize epitaxy to form the epitaxial loayer being arranged in channel region, this epitaxial loayer is identical with Semiconductor substrate material and lattice structure, isotropic etching method is utilized to etch this epitaxial loayer afterwards, avoid prior art self aligned approach and need etch semiconductor substrates, thus cause and form large defect respectively with Semiconductor substrate junction (see the position at the angle in Fig. 2 and Fig. 3 shown in arrow in source region and drain region, this angle is more sharp-pointed, occur around it that defect probability is larger), decrease in Semiconductor substrate, namely in source region, the damage that drain region is formed with Semiconductor substrate intersection respectively, thus, in use not easily there is leaky in the MOS device formed.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is each structural representation formed in the making step of employing of the prior art silicon-germanium as the MOS device of source, drain electrode;
Fig. 4 is the flow chart of the formation method of MOS device provided by the invention;
Fig. 5 to Figure 17 is the intermediate structure schematic diagram of the MOS device according to the formation of Fig. 4 flow process;
Figure 18 is the final structure schematic diagram of the MOS device according to the formation of Fig. 4 flow process.
Embodiment
Existing MOS structure, when forming silicon-germanium source electrode with drain electrode, first adopts self aligned approach etch semiconductor substrates, the large defect that this process can be formed in Semiconductor substrate.The MOS structure with this defect in use there will be source region and drain region to leaky in substrate.For this problem, the present inventor proposes first to utilize epitaxy to form the epitaxial loayer being arranged in channel region, this epitaxial loayer is identical with Semiconductor substrate material and lattice structure, isotropic etching method is utilized to etch this epitaxial loayer afterwards, avoid the self aligned approach etch semiconductor substrates using and adopt in prior art, thus, decrease in Semiconductor substrate, i.e. source region, the damage that drain region is formed with Semiconductor substrate intersection respectively, reach and reduce defect object, the MOS device formed in use not easily occurs that source region and drain region are to leaky in substrate.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.Owing to focusing on, principle of the present invention is described, therefore, charts not in scale.
Fig. 4 is the flow chart of the formation method of MOS device provided by the invention.Fig. 5 to Figure 18 be according to Fig. 4 flow process formed the intermediate structure of MOS device and the schematic diagram of final structure.Below in conjunction with Fig. 4 and Fig. 5 to Figure 18, the method for formation MOS device of the present invention is described in detail.For convenience of description, below for the introduction of P type MOS device.
With reference to Fig. 4, first, perform S10, provide Semiconductor substrate 20, its schematic cross-section as shown in Figure 5; This Semiconductor substrate 20 at least comprises three regions, and wherein, first area I is for the formation of gate regions, and the second area II adjacent with first area I, the 3rd region III are respectively used to form source region and drain region.In the present embodiment, Semiconductor substrate 20 is silicon, also can select germanium as required.
Then, still with reference to Fig. 4, perform S15, utilize epitaxy that the Semiconductor substrate 20 of described first area I is stretched out and grow epitaxial loayer (mark).In the present embodiment, due to the material of epitaxial loayer and Semiconductor substrate 20 and lattice structure identical.
This step, in concrete implementation, comprises the following steps S151-S155.
Perform S151, described Semiconductor substrate 20 is formed the first dielectric layer 21 and the second dielectric layer 22 successively, form the schematic cross-section of structure as shown in Figure 6.Wherein, described first dielectric layer 21 is different from described second dielectric layer 22 material.In the present embodiment, described first dielectric layer 21 material is silicon dioxide, and described second dielectric layer 22 material is silicon nitride.In other embodiment, also can select respective material as required.
Perform S152, the second dielectric layer 22 defines area of grid; Remove and be positioned at described first dielectric layer 21 of described area of grid and the second dielectric layer 22 forms the first opening 23, form the schematic cross-section of structure as shown in Figure 7.This step can adopt photoetching and etching method.Described photoetching is by the photoresist of area of grid on mask plate design transfer to the second dielectric layer 22, forms the mask of patterning.Described etching is with the mask of this patterning for template, and continuation etching first dielectric layer 21 and the second dielectric layer 22 form the first opening 23.Photoetching is all semiconductor conventional process with these two kinds of methods of etching.
Perform S153, utilize epitaxy grown epitaxial layer in described first opening 23, form structural section schematic diagram as shown in Figure 8.The epitaxial loayer of growth does not fill completely described first opening 23.Epitaxy in this step can be molecular beam epitaxy, and technique can adopt existing technique.
Perform S154, deposit the 3rd dielectric layer 24 the 3rd dielectric layer 24 removed outside described first opening 23, form the schematic cross-section of structure as shown in Figure 9, the remaining area of the first opening 23 is filled full.Described 3rd dielectric layer 24 is different from described second dielectric layer 22 material.In the present embodiment, described 3rd dielectric layer 24 material is also silicon dioxide.
Perform S155, remove the second area II on described area of grid both sides and second dielectric layer 22 of the 3rd region III, form structural section schematic diagram as shown in Figure 10.In this step, the second dielectric layer 22 material is silicon nitride, and minimizing technology can adopt phosphoric acid, preferred hot phosphoric acid.
After above-mentioned steps completes, first dielectric layer 21 of second area II and the 3rd region III still exists, and in step S20 implementation, plays the object of the Semiconductor substrate 20 of protection described second area II and the 3rd region III.
Be understandable that, the first dielectric layer 21 in this step also can adopt other layer, and the material of this layer can play a protective role in isotropic etching process.
Then, with reference to Fig. 4, perform S20, utilize isotropic etching method to etch described epitaxial loayer and form channel region, form the schematic cross-section of structure as shown in figure 11.This step can adopt wet etching, and etching agent is the mixture of HF, HNO3, acetic acid; Also can adopt dry etching, etching agent is SF
6, CF
4deng.
Adopt the isotropic etching of this step, owing to there being the existence of the first dielectric layer 21 bottom source region and drain region, thus, large source region, the defect of drain region substrate can not be caused.
Again then, perform step S21, remove first dielectric layer 21 of second area II, the 3rd region III.First dielectric layer 21 material is silicon dioxide, and this minimizing technology can adopt HF acid.
Then perform S25, utilize epitaxy at second area II, the 3rd region III grown silicon-germanium, form silicon-germanium source structure 25, silicon-germanium drain structure 26 respectively, form the schematic cross-section of structure as shown in figure 12.This epitaxy is also such as molecular beam epitaxy, can adopt technique of the prior art.
Then perform S26, described silicon-germanium source structure 25, drain structure 26 and described 3rd dielectric layer 24 form the 4th dielectric layer 27 and carries out being polished to and expose described 3rd dielectric layer 24, form the schematic cross-section of structure as shown in figure 13.Described 4th dielectric layer 27 is different from described 3rd dielectric layer 24 material.In the present embodiment, described 4th dielectric layer 27 material is silicon nitride.
Then perform S27, remove described 3rd dielectric layer 24 to form the second opening 28, form the schematic cross-section of structure as shown in figure 14.3rd dielectric layer 24 material is silicon dioxide, adopts HF acid to remove.
Perform S28, deposit gate insulator material and grid material the gate insulator material removed outside the second opening 28 and grid material, to form gate insulator 29 and grid 30 respectively, form structural section schematic diagram as shown in figure 15, described second opening 28 is filled full.In the present embodiment, described gate insulator 29 material is silicon dioxide, and described grid 30 material is polysilicon, and depositing technics can adopt existing technique.
Perform S29, remove described 4th dielectric layer 27 in described silicon-germanium source structure 25, drain structure 26, form the schematic cross-section of structure as shown in figure 16.
Afterwards, with reference to Fig. 4, perform S30, light dope and heavy doping are carried out to described silicon-germanium source structure 25, drain structure 26, form light doping section and heavily doped region respectively.This step in the process of implementation, comprises the following steps S301-S304.
First perform S301, respectively form a sidewall 31 at described gate insulator 29 with the dual-side of grid 30, shown in Figure 17.This sidewall 31 can avoid the ion implantation in S302 step to impact grid 30 and gate insulator 29.In other embodiments, this step can be omitted.
Then perform S302, light dope carried out to described silicon-germanium source structure 25, drain structure 26, form the schematic cross-section of structure as shown in figure 17; This step Plasma inpouring is boron ion.The injection degree of depth and concentration set as required.
Then perform S303, form side wall 32 at the dual-side of described gate insulator material and grid material, shown in Figure 18.Side wall 32 forming step can adopt eat-backs.
Perform S304 afterwards, heavy doping is carried out to described silicon-germanium source structure 25, drain structure 26.
Through above-mentioned steps, as shown in figure 18, side wall defines light doping section 32 times to the cross section structure of the MOS device of formation, and remaining described silicon-germanium source structure 25, drain structure 26 li form heavily doped region.This step Plasma inpouring is boron ion.The injection degree of depth and concentration set as required.
In the present embodiment, described MOS device is P type MOS device, in described light dope and described heavy doping step, is all boron ion implantation, such as boron or boron fluoride etc.In other embodiment, MOS device also can be N-type device, correspondingly, and ion implantation N-type ion.
To sum up, compared with prior art, the method of above-mentioned formation MOS device has the following advantages: first utilize epitaxy to form the epitaxial loayer being arranged in channel region, this epitaxial loayer is identical with Semiconductor substrate material and lattice structure, adopt dielectric layer protection Semiconductor substrate afterwards, then isotropic etching method is utilized to etch this epitaxial loayer, avoid in prior art self aligned approach etch semiconductor substrates process in the defect that source region and drain region are formed with Semiconductor substrate junction respectively, thus, the MOS device formed in use there will not be source region, drain region is to leaky in Semiconductor substrate.
The present invention also provides a kind of MOS device, is formed by the forming method of MOS device of foregoing description.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (15)
1. a formation method for MOS device, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate at least comprises three regions, and wherein, first area is for the formation of gate regions, and the second area adjacent with first area, the 3rd region are respectively used to form source region and drain region;
Utilize epitaxy that the Semiconductor substrate of described first area is stretched out and grow epitaxial loayer;
Utilize isotropic etching method to etch described epitaxial loayer and form channel region;
Utilize epitaxy at second area, the 3rd region growing silicon-germanium, form silicon-germanium source structure, drain structure respectively;
Described silicon-germanium source structure, drain structure are adulterated;
Wherein, utilize epitaxy to grow epitaxial loayer step to comprise:
Form the first dielectric layer and the second dielectric layer on the semiconductor substrate successively, described first dielectric layer is different from described second dielectric layer material;
Second dielectric layer defines area of grid, removes described first dielectric layer and second dielectric layer of described area of grid, form the first opening;
Utilize epitaxy to grow described epitaxial loayer in described first opening, described epitaxial loayer does not fill completely described first opening;
Deposit the 3rd dielectric layer the 3rd dielectric layer removed outside described first opening, described 3rd dielectric layer is different from described second dielectric layer material;
Remove second dielectric layer in described second area and the 3rd region.
2. the formation method of MOS device according to claim 1, is characterized in that, described silicon-germanium source structure, drain structure are carried out to doping step and comprised light dope and heavy doping, forms light doping section and heavily doped region respectively.
3. the formation method of MOS device according to claim 1, it is characterized in that, after utilizing isotropic etching method to etch described epitaxial loayer formation channel region step, also carry out the first dielectric layer step removing second area, the 3rd region, carry out the described epitaxy that utilizes afterwards at second area, the 3rd region growing silicon-germanium, form the step of silicon-germanium source structure, drain structure respectively.
4. the formation method of MOS device according to claim 3, it is characterized in that, utilize epitaxy at second area, the 3rd region growing silicon-germanium, after forming silicon-germanium source structure, drain structure step respectively, before doping step is carried out to described silicon-germanium source structure, drain structure, also carry out:
Described silicon-germanium source structure, drain structure and described 3rd dielectric layer form the 4th dielectric layer and carry out being polished to and exposes described 3rd dielectric layer; Described 4th dielectric layer is different from described 3rd dielectric layer material;
Remove described 3rd dielectric layer to form the second opening;
Deposit gate insulator material and grid material are to form gate insulator and grid layer, and the gate insulator material removed outside the second opening and grid material;
Remove described 4th dielectric layer in described silicon-germanium source structure, drain structure.
5. the formation method of MOS device according to claim 4, is characterized in that, described silicon-germanium source structure, drain structure are carried out to doping step and comprised:
Light dope is carried out to described silicon-germanium source structure, drain structure;
Side wall is formed at the dual-side of described gate insulator and grid layer;
Heavy doping is carried out to described silicon-germanium source structure, drain structure, under making described side wall, forms light doping section, in remaining described silicon-germanium source structure, drain structure, form heavily doped region.
6. the formation method of MOS device according to claim 5, it is characterized in that, after removing described 4th dielectric layer step in described silicon-germanium source structure, drain structure, before carrying out light dope to described silicon-germanium source structure, drain structure, also carry out forming sidewall step at the dual-side of described gate insulator and grid layer.
7. the formation method of MOS device according to claim 2, is characterized in that, described MOS device is P type MOS device, in described light dope and described heavy doping step, is all P type ion implantation.
8. the formation method of MOS device according to claim 4, it is characterized in that, described first dielectric layer material is silicon dioxide, described second dielectric layer material is silicon nitride, described 3rd dielectric layer material is also silicon dioxide, described 4th dielectric layer material is silicon nitride, utilizes phosphoric acid to carry out the step of the second area on the described area of grid both sides of described removal, second dielectric layer in the 3rd region.
9. the formation method of MOS device according to claim 8, is characterized in that, utilizes HF acid to carry out the step of the first dielectric layer in described removal second area, the 3rd region.
10. the formation method of MOS device according to claim 8 or claim 9, is characterized in that, utilizes HF acid to carry out described 3rd dielectric layer of described removal to form the step of the second opening.
The formation method of 11. MOS device according to claim 10, is characterized in that, utilizes phosphoric acid to carry out the step of described 4th dielectric layer in described removal described silicon-germanium source structure, drain structure.
The formation method of 12. MOS device according to claim 4, is characterized in that, described gate insulator material is silicon dioxide, and described grid material is polysilicon.
The formation method of 13. MOS device according to claim 1, is characterized in that, utilize isotropic etching method to etch described epitaxial loayer and formed in the step of channel region, described isotropic etching method etching adopts wet etching, and etching agent is HF, HNO
3, acetic acid mixture.
The formation method of 14. MOS device according to claim 1, is characterized in that, utilize isotropic etching method to etch described epitaxial loayer and formed in the step of channel region, described isotropic etching method etching adopts dry etching, and etching agent is SF
6or CF
4.
15. 1 kinds of MOS device, is characterized in that, the formation method of the MOS device according to above-mentioned arbitrary claim and being formed.
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| CN1787230A (en) * | 2004-12-08 | 2006-06-14 | 株式会社东芝 | Semiconductor device including field-effect transistor |
| CN102104067A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor epitaxially growing source/drain region and manufacturing method thereof |
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| US8022488B2 (en) * | 2009-09-24 | 2011-09-20 | International Business Machines Corporation | High-performance FETs with embedded stressors |
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| JPH11163324A (en) * | 1997-11-26 | 1999-06-18 | Nec Corp | Method for manufacturing semiconductor device |
| CN1543679A (en) * | 2002-07-12 | 2004-11-03 | ض� | Method for ultra-thin silicon-on-oxide devices including epitaxial silicon terminations and articles of manufacture thereof |
| CN1787230A (en) * | 2004-12-08 | 2006-06-14 | 株式会社东芝 | Semiconductor device including field-effect transistor |
| CN102104067A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor epitaxially growing source/drain region and manufacturing method thereof |
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