CN101281871A - Composite hard mask layer, metal oxide semiconductor transistor and manufacturing method thereof - Google Patents

Abstract

The invention discloses a method for manufacturing a metal oxide semiconductor transistor by using a composite hard mask layer, which comprises the steps of providing a substrate with a surface comprising a dielectric layer and a polysilicon layer, and forming the composite hard mask comprising a middle hard mask and a side wall hard mask covering the side wall of the middle hard mask on the polysilicon layer. Performing a first etching process to etch the polysilicon layer and the dielectric layer by using the composite hard mask as an etching mask to form a gate structure; and performing a second etching process to form grooves in the substrate on two sides of the gate structure respectively. And then, carrying out a selective epitaxial growth process to form epitaxial layers in the grooves respectively. The invention also discloses a composite hard mask layer and a metal oxide semiconductor transistor.

Description

Composite hard mask layer, metal oxide semiconductor transistor and manufacturing method thereof

technical field

The present invention relates to a method for making a metal-oxide semiconductor transistor (MOS transistor) using a composite hard mask layer, especially a method for growing a metal-oxide semiconductor transistor (MOS transistor) using selective epitaxy (hereinafter referred to as SEG). Methods of fabricating MOS transistors.

Background technique

Selective epitaxial growth (SEG) technology is mainly to form an epitaxial layer with the same lattice arrangement as the substrate on the surface of a single crystal substrate, which is used in the manufacture of many semiconductor devices, such as raised source/drain (raised source/drain ) transistors have the advantages of good short channel characteristics and low parasitic resistance, and at the same time, through the existence of an increased epitaxial layer, it can avoid the trouble of excessive consumption of silicon substrate when forming metal silicide; while the embedded source/drain (recessed source/drain) has the advantages of improving drain induced barrier lowering (DIBL) and punchthrough effects, reducing off-state leakage current, and reducing power consumption.

Generally speaking, the SEG technology first uses the surface cleaning process to completely remove the native oxide (native oxide) or other impurities (impurity) on the substrate surface, and then deposits the epitaxial layer on the substrate surface, and makes the epitaxial layer along the surface of the substrate. The lattice structure grows upwards. Please refer to FIG. 1 to FIG. 4 . FIG. 1 to FIG. 4 are schematic diagrams of a known method for fabricating strained silicon MOS transistors using SEG technology. As shown in FIG. 1, first, a substrate 100 is provided, such as a silicon substrate, on which a plurality of shallow trench isolations (shallow trench isolation, STI) 102 have been formed, and a dielectric layer 112, a polysilicon layer, and a dielectric layer 112 are sequentially formed on the substrate. layer 114, and a hard mask layer comprising silicon nitride or silicon oxide, wherein the hard mask layer is patterned by a photolithography process, and the resulting patterned hard mask layer 120 is used to define the position and line width of the gate .

See Figure 2. Next, an etching process is performed to remove part of the polysilicon layer 114 and the dielectric layer 112 to form the gate 110 . Subsequently, an ion implantation process is performed to form lightly doped drains (LDDs) 116 in the substrate 100 on both sides of the gate 110 , and spacers 118 are formed on sidewalls of the gate 110 . Next, please refer to Figure 3 and Figure 4. Then, using the patterned hard mask layer 120 and the partition walls 118 as etching masks, the grooves 130 are respectively etched in the substrate 100 on both sides of the gate 110 . As shown in FIG. 4 , an epitaxial layer 132 is formed on the surface of the substrate 100 in the groove 130 during the subsequent SEG process. In addition, before etching the groove 130 or after forming the epitaxial layer 132 by the SEG process, an ion implantation process may be performed to form the embedded source/drain.

It is worth noting that after forming the gate 110 and before performing the SEG process of forming the embedded source/drain, the substrate 100 will undergo multiple etching and cleaning steps, such as cleaning the polysilicon layer 114 after etching, lightly doped Cleaning after the ion implantation of the drain electrode 116, etching of the partition wall 118 and cleaning after the etching, etching of the groove 130 and cleaning after the etching, and cleaning before the SEG process. hard mask layer 120. Therefore, before the SEG process is performed, the worn patterned hard mask layer 120 exposes the underlying polysilicon layer 114 , and this kind of wear occurs mostly at the edge of the patterned hard mask layer 120 . When the subsequent SEG process is performed, these exposed corners of the polysilicon layer 114 will form epitaxial layers that should not appear. The formation of these epitaxial layers may cause ions doped in the polysilicon layer 114 to diffuse into these epitaxial layers, thereby reducing the activation degree of the gate 110 or increasing the inversion of the gate 110 , affecting device performance. These epitaxial layers 132 may even cause a short circuit between the gate 110 and the source/drain in subsequent processes, resulting in a decrease in yield.

In addition, since the hard mask layer 120 made of silicon nitride is not easy to remove, it is often used in subsequent removal steps to remove the hard mask layer 120 , for example, to remove the hard mask layer 120 to form Metal silicide will affect the surface profile of the gate 110, and even remove the spacer 118 together in the removal step, and cause damage to the sidewalls of the gate 110 or the dielectric layer 112 at the bottom of the polysilicon layer 114 .

Therefore, how to provide a hard mask layer that can effectively resist the wear caused by the etching and cleaning steps and not cause damage to other components during removal is an important issue in the field of semiconductor technology.

Contents of the invention

Therefore, the present invention hereby provides a method for manufacturing MOS transistors using a composite hard mask, so as to improve the damage to other components due to consumption of the hard mask layer in the prior art, and damage to other components when the hard mask layer is removed. missing.

According to the patent scope of the present invention, a method for manufacturing a metal oxide semiconductor transistor using a composite hard mask layer is provided. The method includes providing a substrate having a surface comprising a dielectric layer and a polysilicon layer, and then forming at least one composite hardmask on the polysilicon layer, the composite hardmask comprising a middle hardmask and sides covering the middle hardmask wall sidewall hard mask. Next, a first etching process is performed, using the composite hard mask as an etching mask to etch the polysilicon layer and the dielectric layer to form a gate structure; a second etching process is performed to form the substrate on both sides of the gate structure Form grooves (recesses) respectively. Afterwards, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in each of the grooves.

According to the patent scope of the present invention, a method for manufacturing a metal oxide semiconductor transistor with a composite hard mask layer is provided. The method includes providing a substrate with a dielectric layer and a polysilicon layer on the surface, sequentially forming a first hard mask layer and a second hard mask layer on the film layer, and performing photolithography and etching processes to remove A portion of the first hard mask layer and a portion of the second hard mask layer form at least an intermediate hard mask. Next, a third hard mask layer covering the polysilicon layer and the intermediate hard mask is formed, and an etch-back process is performed to remove part of the third hard mask layer to form at least one sidewall hard mask, and the A sidewall hardmask covers sidewalls of the intermediate hardmask to form a composite hardmask. performing a first etching process, using the composite hard mask as an etching mask to etch the polysilicon layer and the dielectric layer to form a gate structure; Form grooves. Then perform SEG process to form epitaxial layers in these grooves respectively.

According to the patent application scope of the present invention, a composite hard mask for making MOS transistors is further provided, including a middle hard mask (middle hard mask) and a sidewall hard mask (spacer hardmask), and the sidewall hard mask A mask is disposed on sidewalls of the middle hard mask layer.

According to the patent scope of the present invention, a MOS transistor is further provided, comprising a gate structure disposed on a substrate, a composite hard mask layer disposed on the gate structure, the composite hard mask layer comprising an intermediate hard mask layer A mask and a sidewall hard mask are disposed on sidewalls of the middle hard mask. The MOS transistor also includes a pair of lightly doped drains respectively disposed in the substrate on both sides of the gate structure; and a pair of lightly doped drains respectively disposed in the substrate on both sides of the gate structure for use as the MOS transistor The epitaxial layer of the source/drain.

In the method for making MOS transistors using a composite hard mask provided by the present invention, the sidewall hard mask of the composite hard mask is used to effectively resist the wear and tear caused by the etching and cleaning steps, and effectively protect the components it covers; at the same time, it is used as the main body The intermediate hard mask can be removed without causing damage to other components, so that the yield can be improved.

Description of drawings

1 to 4 are schematic diagrams of a known method for fabricating strained silicon MOS transistors using SEG technology.

FIG. 5 to FIG. 11 are the first preferred embodiment of the fabrication method of the composite hard mask layer provided by the present invention.

FIG. 12 to FIG. 16 are the second preferred embodiment of the fabrication method of the composite hard mask layer provided by the present invention.

[Description of main component symbols]

100 base 102 shallow trench isolation

110 grid 112 dielectric layer

114 polysilicon layer 116 lightly doped drain

118 barrier ribs 120 patterned hard mask layer

130 grooves 132 epitaxial layers

200 base 202 shallow trench isolation

210 grid 212 dielectric layer

214 film layer 216 lightly doped drain

218 partition wall 220 first hard mask layer

222 photoresist layer 224 intermediate hard mask

230 second hard mask layer 234 sidewall hard mask

240 composite hard mask 250 grooves

252 epitaxial layers

300 base 302 shallow trench isolation

312 dielectric layer 314 film layer

320 first hard mask layer 322 second hard mask layer

324 photoresist layer 326 intermediate hard mask

330 third hard mask layer 336 sidewall hard mask

340 composite hard mask

Detailed ways

Please refer to FIG. 5 to FIG. 11 . FIG. 5 to FIG. 11 are the first preferred embodiment of the manufacturing method of the composite hard mask layer provided by the present invention. As shown in FIG. 5 , firstly, a substrate 200 is provided, such as a silicon substrate, on which a plurality of shallow trench isolations (shallow trench isolation, STI) 202 have been formed. Subsequently, a dielectric layer 212 , a polysilicon layer 214 , and a first hard mask layer 220 are sequentially formed on the substrate 200 . The first hard mask layer 220 includes silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide (SiC), silicon carbide containing oxygen (SiOC), Silicon-rich-nitride (SRN), high temperature oxide (HTO), anti-reflective bottom layer, or bis (tert-butylamino) silane (Bis (tert-butylamino) silane, BTBAS) . A photoresist layer 222 is formed on the first hard mask layer 220, and the photoresist layer 222 is patterned through a photolithography process.

See Figure 6. Next, an etching process is performed to remove part of the first hard mask layer 220 by using the patterned photoresist layer 222 as a mask to form an intermediate hard mask 224 .

See Figure 7. Subsequently, a second hard mask layer 230 is formed on the polysilicon layer 214 and the intermediate hard mask 224 . The second hard mask layer 230 includes silicon nitride, silicon oxynitride, silicon carbide nitride, silicon carbide, silicon carbide containing oxygen, or polysilicon silicon nitride (SRN). The second hard mask layer 230 has a different etching selectivity than the first hard mask layer 220 .

See Figure 8. Next, an etching back process is performed to remove part of the second hard mask layer 230 to form sidewall hard masks 234 on the sidewalls of the middle hard mask 224 . The middle hard mask 224 and the sidewall hard mask 234 form a composite hard mask 240 . As previously mentioned, the middle hard mask 224 has a different etch selectivity than the sidewall hard mask 234 . And as shown in FIG. 8, the ratio of the width X of the middle hard mask 224 to the width Y of the sidewall hard mask 234 is about 1:10. In addition, the width of the sidewall hard mask layer 234 is not greater than 10 nanometers (nanometer).

The composite hard mask 240 provided in the first preferred embodiment is used to define the position of the gate structure 210 in the SEG process. Referring to FIG. 9 , the first etching process is performed next, and the film layer 214 and the dielectric layer 212 are etched down through the composite hard mask 240 to form the gate structure 210 . Since the composite hard mask 240 is used to define the position and line width of the gate structure 210, after the photolithography process of patterning the first photoresist layer 222, a trimming step can be performed to Trimming the patterned first photoresist layer 222 ; or performing a trimming step after the etching process for forming the intermediate hard mask 224 to trim the intermediate hard mask 224 . In short, through the trimming step, the first preferred embodiment can adjust the width of the middle hard mask 224 , supplemented by the width of the sidewall hard mask 234 to define the line width of the gate structure 210 .

Please refer to FIG. 10, an ion implantation process is then performed to respectively form lightly doped drains (LDD) 216 in the substrate 200 on both sides of the gate structure 210, and form the sidewalls of the gate structure 210. Partition wall 218 . The spacers 218 and the composite hard mask 240 are used as etching masks in the second etching process to respectively form grooves 250 in the substrate 200 on both sides of the gate structure 210 .

See Figure 11. The epitaxial layer 252 is formed on the surface of the substrate 200 in the groove 250 during the SEG process to serve as the embedded source/drain. Of course, before etching the groove 250 or after forming the epitaxial layer by the SEG process, an ion implantation process may be performed to form the aforementioned embedded source/drain. If the MOS transistor is a PMOS transistor, the embedded source/drain includes silicon germanium (SiGe) or the like; if the MOS transistor is an NMOS transistor, the embedded source/drain includes silicon carbide (SiC) or the like. In addition, the method provided by this first preferred embodiment is not limited to fabricating the aforementioned embedded source/drain, it can also be used to fabricate raised source/drain or planer source/drain. drain.

Before performing the SEG process for forming the embedded source/drain, the substrate 200 will undergo multiple etching and cleaning steps, such as cleaning after etching the polysilicon layer 214, cleaning after ion implantation of the lightly doped drain 216, and cleaning the partition walls. The etch and post-etch cleaning of 218 , the etching and post-etch cleaning of recess 250 , and the cleaning before the SEG process, all of which will consume the composite hard mask 240 . However, since the etching selectivity ratio of the sidewall hard mask 234 of the composite hard mask 240 is different from that of the middle hard mask 224, or in other words, the etching rate of the sidewall hard mask 234 is much lower than that of the middle hard mask 224. Etching rate, so the above-mentioned etching and cleaning process will greatly reduce the consumption of the edge of the composite hard mask 240, so that the gate structure 210 covered by the composite hard mask 240 will not be exposed after the above-mentioned etching and cleaning process, Therefore, the corners of the gate structure 210 will not form an epitaxial layer during the SEG process, which will reduce the activation degree of the gate structure 210 or increase the inversion of the gate structure 210, which will affect the performance of the gate.

In addition, since the main body of the composite hard mask 240 is still the intermediate hard mask 224, in the subsequent step of removing the composite hard mask 234, it is less likely to damage other components, such as affecting the surface profile of the gate 210, even the removal step The partition walls 218 are removed together.

Please refer to FIG. 12 to FIG. 16 . FIG. 12 to FIG. 16 are the second preferred embodiment of the manufacturing method of the composite hard mask layer provided by the present invention. As shown in FIG. 12 , firstly, a substrate 300 is provided, such as a silicon substrate, on which a plurality of shallow trench isolations (STIs) 302 have been formed. Subsequently, a dielectric layer 312 , a polysilicon layer 314 , a first hard mask layer 320 and a second hard mask layer 322 are sequentially formed on the substrate 300 . The first hard mask layer 320 includes silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide (SiC), silicon carbide containing oxygen (SiOC), Polysilicon silicon nitride (SRN), high temperature silicon oxide (HTO), anti-reflective underlayer, or bis(tert-butylamino)silane (BTBAS). The second hard mask layer 322 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, silicon carbide, silicon carbide containing oxygen, polysilicon nitride (SRN), high temperature silicon oxide (HTO), Anti-reflective bottom layer, or bis(tert-butylamino)silane (BTBAS) and other materials. The first hard mask layer 320 and the second hard mask layer 322 have different etching ratios.

Please refer to Figures 13 and 14. Perform photolithography and etching processes, first form a photoresist layer 324 on the second hard mask layer 322, use a photolithography process to pattern the photoresist layer 324, and use the patterned photoresist Layer 324 undergoes an etching process to remove part of the first hard mask layer 320 and part of the second hard mask layer 322. After removing the photoresist layer 324, an intermediate hard mask as shown in FIG. 14 is formed. 326.

See Figure 15. Next, a third hard mask layer 330 is formed on the polysilicon layer 314 and the middle hard mask 326 . The third hard mask layer 330 includes materials such as silicon nitride, silicon oxynitride, silicon carbide nitride, silicon carbide, silicon carbide containing oxygen, or polysilicon silicon nitride (SRN).

Please refer to Figure 15 and Figure 16. An etch-back process is then performed to remove part of the third hard mask layer 330 to form a sidewall hard mask 336 on the sidewall of the middle hard mask 326 . The middle hard mask 326 and the sidewall hard mask 336 form a composite hard mask 340 . Notably, the middle hardmask 326 has a different etch ratio than the sidewall hardmask 336 . And as shown in FIG. 15 , the ratio of the width X of the middle hard mask 326 to the width Y of the sidewall hard mask 336 is about 1:10. In addition, the width of the sidewall hard mask layer 336 is not greater than 10 nanometers.

The composite hard mask 340 provided in the second preferred embodiment is the same as that in the aforementioned first preferred embodiment, and can be used in the SEG process to define the position and line width of the gate. Since the composite hard mask 340 is used to define the line width of the gate, after the photolithography process of the patterned photoresist layer 324, a trimming step may be performed to trim the patterned photoresist layer. 324 ; or after the etching process for forming the intermediate hard mask 326 , a trimming step is performed to trim the intermediate hard mask 326 . In short, through the trimming step, the second preferred embodiment can adjust the width of the middle hard mask 326 , supplemented by the width of the sidewall hard mask 336 to define the line width of the gate. Since the subsequent manufacturing process of the MOS transistor is the same as that described in the first preferred embodiment, it will not be repeated here.

Since the etch rate of the sidewall hard mask 336 in the composite hard mask 340 is different from the etch rate of the middle hard mask 326, or in other words, the etch rate of the sidewall hard mask 336 is much lower than the middle hard mask 326, therefore The etching and cleaning process required by the semiconductor process will greatly reduce the wear on the edge of the composite hard mask 340, and also make the components covered by the composite hard mask 340, such as the gate described in the second embodiment, It will not be exposed after the above etching and cleaning process, resulting in the formation of epitaxial layers that should not appear at the corners of the gate during the SEG process, reducing the activation degree of the gate or increasing the inversion of the gate, which will affect the performance of the gate.

In addition, since the main body of the composite hard mask 340 is still the intermediate hard mask 326, in the subsequent step of removing the composite hard mask 336, it is less likely to damage other elements, such as affecting the surface profile of the gate, even during the removal step. Remove the partition walls together.

Please refer to Figure 9 and Figure 16 again. In summary, the present invention provides a hybrid hard mask layer (hybrid hard mask) 240/340 for making MOS transistors, which includes a middle hard mask (middle hard mask) 224/326 and a middle hard mask layer A spacer hard mask 234/336 of the sidewalls of the masks 224/326. The middle hard mask 224/326 may further include a bottom hard mask 320 and a top hard mask 322 as shown in FIG. 16 . The bottom hard mask 320 includes silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide (SiC), silicon carbide (SiOC), polysilicon Silicon Nitride (SRN), High Temperature Silicon Oxide (HTO), Antireflective Underlayer, or Bis(tert-butylamino)silane (BTBAS). The top hard mask 322 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, silicon carbide, silicon carbide containing oxygen, polysilicon nitride (SRN), high temperature silicon oxide (HTO), anti-reflective bottom layer, Or bis(t-butylamino)silane (BTBAS) and other materials. The bottom hard mask layer 320 and the top hard mask layer 322 have the same or different etch ratios.

The sidewall hard mask 234/336 includes materials such as silicon nitride, silicon oxynitride, silicon carbide nitride, silicon carbide, silicon carbide containing oxygen, or polysilicon silicon nitride (SRN), and the sidewall hard mask 234/ 336 has a different etch ratio than intermediate hardmask 224/326. The width of the middle hardmask 224/326 has a ratio to the width of the sidewall hardmask 234/336, and the ratio is about 1:10. In addition, the width of the sidewall hard mask layer 234/336 is no greater than 10 nanometers.

In the SEG process, the substrate carrying various components will undergo multiple etching and cleaning processes, and the composite hard mask used to define the position and size of the components is different from that of the middle hard mask due to the etching ratio of the sidewall hard mask. The etch ratio, that is, the etch ratio of the sidewall hard mask is much lower than that of the middle hard mask, so the above-mentioned etching and cleaning process will greatly reduce the consumption of the edge of the composite hard mask, and also make the composite hard mask cover The gate structure will not be exposed after the above etching and cleaning process, but the performance of the gate structure will be affected by the consumption or formation of an epitaxial layer that should not appear in the subsequent process. For example, as described in the first preferred embodiment and the second preferred embodiment, the epitaxial layer in the SEG process will not be formed at the corner of the gate, which will affect the activation degree of the gate or increase the inversion of the gate. In addition, since the main body of the composite hard mask is still an intermediate hard mask, it is less likely to be damaged and other components in subsequent steps of removing the composite hard mask.

To put it simply, the fabrication method of the MOS transistor using the composite hard mask provided by the present invention uses the sidewall hard mask to effectively resist the wear and tear caused by the etching and cleaning steps, and protect the elements it covers; The hard mask can be removed without causing damage to other components, so the yield can be improved.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (53)

1. manufacture method of utilizing the metal oxide semiconductor transistor of composite hard mask layer includes:

Substrate is provided, and this substrate surface includes dielectric layer and polysilicon layer;

Form at least one compound being masked in firmly on this polysilicon layer, and this compound hard mask includes middle hard mask and the hard mask of sidewall that covers the hard mask sidewalls in this centre;

Carry out first etch process, utilize this compound hard mask to be this polysilicon layer of etching mask etching and this dielectric layer, to form grid structure;

Carry out second etch process, in this grid structure substrate on two sides, to form groove respectively; And

Carry out selective epitaxial growth technology, in these grooves, to form epitaxial loayer respectively.

2. the method for claim 1, the step that wherein forms this compound hard mask also includes:

On this polysilicon layer, form first hard mask layer and photoresist layer in regular turn;

Carry out photoetching process, with this photoresist layer of patterning;

Carry out etch process, utilize the photoresist layer of this patterning to remove this first hard mask layer of part, and form the hard mask in this centre for mask;

On the hard mask of this polysilicon layer and this centre, form second hard mask layer; And

Carry out etch back process, remove this second hard mask layer of part, with in this centre firmly the sidewall of mask form the hard mask of this sidewall.

3. method as claimed in claim 2 also comprises pre-shaping step, is carried out at after this photoetching process, in order to repair the photoresist layer of this patterning.

4. method as claimed in claim 2 also comprises pre-shaping step, is carried out at after this etch process, in order to repair the hard mask in this centre.

5. the method for claim 1, wherein position and the live width of this compound hard mask in order to define this grid structure.

6. the method for claim 1, wherein the hard mask in this centre include silica, silicon nitride, silicon oxynitride, fire sand, carborundum, contain siloxicon, many silicon silicon nitride, high-temperature oxydation silicon, antireflection bottom or two (tertiary butyl amino) silane.

7. the method for claim 1, wherein the hard mask of this sidewall includes silicon nitride, silicon oxynitride, fire sand, carborundum, contains siloxicon or many silicon silicon nitride.

8. the method for claim 1, wherein the hard mask in this centre of this compound hard mask has different etching ratios with the hard mask of this sidewall.

9. the method for claim 1, wherein the width of the hard mask in this centre and the width of the hard mask of this sidewall have a ratio, and this ratio is about 1: 10.

10. the method for claim 1, wherein carry out this second etch process before, the sidewall that also is contained in this grid structure forms the step of spaced walls.

11. the method for claim 1, wherein this grid structure is the transistorized grid structure of P-type mos.

12. method as claimed in claim 11, wherein this epitaxial loayer includes SiGe.

13. the method for claim 1, wherein this grid structure is the transistorized grid structure of N type metal oxide semiconductor.

14. method as claimed in claim 13, wherein this epitaxial loayer includes carborundum.

15. the process for forming MOS transistor with composite hard mask layer includes following steps:

Substrate is provided, and this substrate surface includes dielectric layer and polysilicon layer;

Form first hard mask layer and second hard mask layer in regular turn on this rete;

Carry out photoetching and etch process, form the hard mask at least one centre with this second hard mask layer of part to remove this first hard mask layer of part;

Form the 3rd hard mask layer, cover the hard mask in this polysilicon layer and this centre;

Carry out etch back process, form the hard mask of at least one sidewall, and the hard mask of this sidewall covers the sidewall of the hard mask in this centre to constitute compound hard mask to remove part the 3rd hard mask layer;

Carry out first etch process, utilize this compound hard mask for this polysilicon layer of etching mask etching and this dielectric layer to form grid structure;

Carry out second etch process, in this grid structure substrate on two sides, to form groove respectively; And

Carry out selective epitaxial growth technology, in these grooves, to form epitaxial loayer respectively.

16. method as claimed in claim 15, wherein this photoetching and etch process also include:

Form the photoresist layer on this second hard mask layer;

Carry out photoetching process, with this photoresist layer of patterning; And

Carry out etch process, utilize this photoresist layer to remove this first hard mask layer of part and this second hard mask layer of part, and form the hard mask in this centre for mask.

17. method as claimed in claim 16 also comprises pre-shaping step, is carried out at after this lithography step, in order to repair the photoresist layer of this patterning.

18. method as claimed in claim 16 also comprises pre-shaping step, is carried out at after this etch process, in order to repair the hard mask in this centre.

19. method as claimed in claim 15 is wherein in position and the live width of this compound hard mask in order to define this grid structure.

20. method as claimed in claim 15, wherein this first hard mask layer include silica, silicon nitride, silicon oxynitride, fire sand, carborundum, contain siloxicon, many silicon silicon nitride, high-temperature oxydation silicon, antireflection bottom or two (tertiary butyl amino) silane.

21. method as claimed in claim 15, wherein this second hard mask layer include silica, silicon nitride, silicon oxynitride, fire sand, carborundum, contain siloxicon, material such as many silicon silicon nitride, high-temperature oxydation silicon, antireflection bottom or two (tertiary butyl amino) silane.

22. method as claimed in claim 15, wherein the 3rd hard mask layer includes silicon nitride, silicon oxynitride, fire sand, carborundum, contains materials such as siloxicon or many silicon silicon nitride.

23. method as claimed in claim 15, wherein this first hard mask layer, second hard mask layer have different etching ratios with the 3rd hard mask layer.

24. method as claimed in claim 15, wherein the width of the hard mask in this centre and the width of the hard mask of this sidewall have a ratio, and ratio is about 1: 10.

25. method as claimed in claim 15, wherein carry out this second etch process before, also be contained in the step that this grid structure sidewall forms spaced walls.

26. method as claimed in claim 15, wherein this grid structure is the transistorized grid structure of P-type mos.

27. method as claimed in claim 26, wherein this epitaxial loayer includes SiGe.

28. method as claimed in claim 15, wherein this grid structure is the transistorized grid structure of N type metal oxide semiconductor.

29. method as claimed in claim 28, wherein this epitaxial loayer includes carborundum.

30. a compound hard mask of making metal oxide semiconductor transistor includes:

Middle hard mask; And

The hard mask of sidewall is arranged at the sidewall of the hard mask in this centre.

31. compound hard mask as claimed in claim 30, wherein the hard mask in this centre also includes bottom mask and hardmask layer.

32. compound hard mask as claimed in claim 31, wherein this bottom hardmask layer include silica, silicon nitride, silicon oxynitride, fire sand, carborundum, contain siloxicon, many silicon silicon nitride, high-temperature oxydation silicon, antireflection bottom or two (tertiary butyl amino) silane.

33. compound hard mask as claimed in claim 31, wherein this hardmask layer include silica, silicon nitride, silicon oxynitride, fire sand, carborundum, contain siloxicon, material such as many silicon silicon nitride, high-temperature oxydation silicon, antireflection bottom or two (tertiary butyl amino) silane.

34. compound hard mask as claimed in claim 31, wherein this bottom hardmask layer has identical etching ratio with this top hard mask.

35. compound hard mask as claimed in claim 31, wherein this bottom hardmask layer has different etching ratios with this hardmask layer.

36. compound hard mask as claimed in claim 30, wherein the hard mask of this sidewall includes silicon nitride, silicon oxynitride, fire sand, carborundum, contains materials such as siloxicon or many silicon silicon nitride.

37. compound hard mask as claimed in claim 30, wherein the hard mask of this sidewall has different etching ratios with the hard mask in this centre.

38. compound hard mask as claimed in claim 30, wherein the width of the hard mask in this centre and the width of the hard mask of this sidewall have a ratio, and this ratio is about 1: 10.

39. a metal oxide semiconductor transistor includes:

Grid structure is arranged in the substrate;

Composite hard mask layer is arranged on this grid structure, and hard mask and the hard mask of sidewall were arranged at the sidewall of the hard mask in this centre in the middle of this composite hard mask layer included;

A pair of lightly doped drain is arranged at respectively in this substrate of these grid structure both sides; And

A pair of epitaxial loayer is arranged at respectively in this substrate of these grid structure both sides, in order to the source/drain as this metal oxide semiconductor transistor.

40. metal oxide semiconductor transistor as claimed in claim 39, wherein this grid structure includes polysilicon layer and dielectric layer in regular turn.

41. metal oxide semiconductor transistor as claimed in claim 39 also includes spaced walls, is arranged at the sidewall of this grid structure.

42. metal oxide semiconductor transistor as claimed in claim 39, wherein the hard mask in this centre also includes bottom mask and hardmask layer.

43. metal oxide semiconductor transistor as claimed in claim 42, wherein this bottom hardmask layer include silica, silicon nitride, silicon oxynitride, fire sand, carborundum, contain siloxicon, many silicon silicon nitride, high-temperature oxydation silicon, antireflection bottom or two (tertiary butyl amino) silane.

44. metal oxide semiconductor transistor as claimed in claim 42, wherein this hardmask layer include silica, silicon nitride, silicon oxynitride, fire sand, carborundum, contain siloxicon, material such as many silicon silicon nitride, high-temperature oxydation silicon, antireflection bottom or two (tertiary butyl amino) silane.

45. metal oxide semiconductor transistor as claimed in claim 42, wherein this bottom hardmask layer has identical etching ratio with this top hard mask.

46. metal oxide semiconductor transistor as claimed in claim 42, wherein this bottom hardmask layer has different etching ratios with this hardmask layer.

47. metal oxide semiconductor transistor as claimed in claim 39, wherein the hard mask of this sidewall includes silicon nitride, silicon oxynitride, fire sand, carborundum, contains materials such as siloxicon or many silicon silicon nitride.

48. metal oxide semiconductor transistor as claimed in claim 39, wherein the hard mask of this sidewall has different etching ratios with the hard mask in this centre.

49. metal oxide semiconductor transistor as claimed in claim 39, wherein the width of the hard mask in this centre and the width of the hard mask of this sidewall have a ratio, and this ratio is about 1: 10.

50. metal oxide semiconductor transistor as claimed in claim 39, wherein this grid structure is the transistorized grid structure of P-type mos.

51. metal oxide semiconductor transistor as claimed in claim 50, wherein this epitaxial loayer includes SiGe.

52. metal oxide semiconductor transistor as claimed in claim 39, wherein this grid structure is the transistorized grid structure of N type metal oxide semiconductor.

53. metal oxide semiconductor transistor as claimed in claim 52, wherein this epitaxial loayer includes carborundum.

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