JP2951355B2 - Logic simulation equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a logic simulation apparatus that handles detailed delays in consideration of individual signal propagation delays generated in logic gates and wiring of a logic circuit, and minimizes the amount of memory used in the logic simulation apparatus. The purpose is to reduce the overhead in event processing and minimize the overhead, and to perform high-speed processing. It has an evaluation pipeline, a fan-out pipeline, and an event scheduler. An event that stores time event data linked to a chain
It has a list memory and a time-corresponding address, and those addresses are used as pointers to the first and last addresses of the chain of events in the event list memory in which the time corresponding to the address is a designated time. A time management memory to be stored, and an empty area management circuit that manages the empty area using the empty area in the event list memory as a chain and using the first and last addresses as pointers are provided. Reading the pointers indicating the beginning and end of the event chain in the event list memory stored at the address corresponding to the above, sequentially reading the event data linked to the corresponding chain from the event list memory, After reading is completed, pointers indicating the beginning and end of the chain are cleared. Notify band management circuit, characterized in that to register as an empty area in the free area management circuit.

[Industrial applications]

The present invention relates to a logic simulation apparatus that handles a detailed delay in consideration of individual signal propagation delays generated in a logic gate of a logic circuit and in wiring, and in particular, outputs an output value of each evaluated logic gate to a predetermined logic gate in a subsequent stage. The present invention relates to an event scheduling mechanism for propagating an event at a time.

In order to verify the timing of a designed logic circuit in detail, the need for a dynamic simulator capable of handling detailed delay is increasing.

On the other hand, with the increase in the scale of logic circuits, a software simulator built on a general-purpose computer has taken an enormous amount of processing time. Therefore, dedicated hardware has been developed to execute logic simulation at high speed.
It is already in practical use.

However, most of them perform a simulation with a single delay that regards the delay amount of all gates as the same or a zero delay that ignores the delay amount, and cannot be used for timing verification. In the case of a device that can handle detailed delays, the event scheduler for scheduling events at arbitrary times becomes complicated, and a large amount of memory is required. Speed has dropped significantly.

In particular, the present invention provides an event scheduling device that enables high-speed event processing with a small memory capacity.

[Conventional technology]

FIG. 5 shows a basic configuration of a conventional logic simulation apparatus. In the figure, 1 is a net status memory, 2 is a new event buffer NEB, 3 is a fan-out pipeline, 4 is an evaluation gate buffer EGB, 5 is an evaluation pipeline, and 6 is an event scheduler. .

The net status memory 1 stores state information (value) for each logical unit (hereinafter referred to as a gate) constituting a simulation target logical circuit as illustrated in FIG.
And is updated according to the simulation execution.

The evaluation gate buffer EGB4 stores information (including a change time, an input terminal, and a change value) of a gate whose input value has changed.

The evaluation pipeline 5 has, for each gate, information such as fan-in information, detailed delay amount, and logic type of the gate, and extracts information of the gate whose input value has changed at time t from the evaluation gate buffer EGB4. The logic state is evaluated, and as a result, a gate that changes the output value is detected. Further, a change time t 'of the output value is calculated in consideration of the detailed delay, and the event data of the gate is transmitted to the event scheduler 6. Output in packets.

The event schedule device 6 sorts the output value change events of the respective gates having the different change times t ′ output from the evaluation pipeline 5 in time series and sequentially propagates the events to the fan-out destination gate. Scheduling. For this purpose, the event schedule device 6 sets each event belonging to the same time for each change time.
Connect the data to a chain, store it in a table, and manage the schedule so that it can be easily retrieved in chronological order. These event data include a gate name and a change value (old value, new value).

When dispatching (issuing) event data that has been scheduled in this manner,
Each event data of the chain having the change time coincident with the current time is sequentially read, and the new event buffer NEB2 is sent to the fan-out pipeline 3.

The event data input to the new event buffer NEB2 is temporarily stored, then read out sequentially, and a process of updating the logic state of the corresponding gate in the net status memory 1 is performed.

The fan-out pipeline 3 holds gate connection (fan-out) information within the range of the logic circuit stored in the net status memory 1, and changes the output value according to the input event information. Find all the gates that lead to the output of the gate
Store in buffer EGB4.

The above operation is sequentially and continuously executed for each change time, and the process ends when the evaluation is performed for all the gates.

FIG. 7 shows a method of managing event data in a conventional event schedule device. In the figure, reference numeral 7 denotes a time management memory for registering a pointer of a chain of event data for each change time, 8 denotes an event list memory for storing a chain of event data, and 9 denotes a current time pointer.

When an event packet is input from the evaluation pipeline 5, the event schedule device 6 shown in FIG. 5 checks whether or not the change time of the event data is registered in the time management memory 7, and if the change time is registered, it is determined. For example, by using the pointer stored in the entry of the change time,
The end of the chain of the corresponding event data in the event list memory 8 is known, and new event information is connected to the end to incorporate it into the schedule. On the other hand, if a change time that matches the change time of the input event data cannot be found in the time management memory 7, a new change time is added to the time management memory 7 and the event list memory 8 is added. Open a new chain of event data and link by pointer.

When reading the event data scheduled for each change time in this way, the current time data is set in the current time pointer 9 and updated sequentially, and the schedule is scheduled at each current time. Read the chain of events. For this reason,
An entry having a matching change time is searched in the time management memory 7 for each time of the current time pointer 9, and if there is, an event is set using the pointer to the event list memory 8 set in the entry.・ List memory 8
And reads and outputs sequential event data in the chain. This gives
Information on all gates whose output values change at the same time at each current time can be supplied to the new event buffer NEB2 and the fan-out pipeline 3.

[Problems to be solved by the invention]

In the conventional event scheduler, the event
The data chain is managed using the absolute change time as a key. Therefore, when an event is generated by evaluating a gate, an absolute change time is specified as a time at which the event is scheduled.

On the other hand, the change time of the output value in the evaluation of the gate is specified in consideration of the delay time, and the delay time is given as a relative time from the change time of the input value (corresponding to the current time).

For this reason, a calculation for converting the change time into an absolute time is required, and the processing becomes an overhead of the evaluation pipeline and slows down the processing.

It is also desirable to make the area of the event data that is no longer necessary after processing the events in the schedule reusable. However, this processing takes time in conventional devices, so it is necessary to prepare a large capacity memory. was there.

SUMMARY OF THE INVENTION It is an object of the present invention to perform processing at a high speed by minimizing the amount of memory used in a logic simulation apparatus and by minimizing the overhead in event processing.

[Means for solving the problem]

According to the present invention, the address of the time management memory for managing the schedule of the event data is associated with the time position, and if the relative time from the current time is known, the address at the corresponding time can be accessed by simple address calculation. To

As a result, the evaluation pipeline does not need to calculate the change time based on the detailed delay for the gate whose output value has changed, and it is sufficient to specify the delay time for the event time.
When receiving the event data, the event scheduler obtains the address of the time management memory by adding the delay time to the current time, and can schedule at the corresponding change time.

FIG. 1 is a principle diagram of the present invention, and shows a basic configuration of an event scheduling apparatus.

In FIG. 1, 3 is a fan-out pipeline, 5 is an evaluation pipeline, and 6 is an event schedule device.

An input event buffer 11 receives and stores event packets to be scheduled from the evaluation pipeline 5 via the signal line a. The event packet is a relative time TIME that indicates how many units of time the event should be scheduled before the current time.
And an event data EVENT indicating which gate changes to which signal value. Reference numeral 12 denotes a time management memory for managing a time at which the event should be scheduled, and a time data at which the event should be registered from the signal line b. Receive.

13 is an event list that stores events to be registered
Memory.

An empty area management circuit 14 manages an empty area in the event list memory 13. Event list memory 13
Receives the event to be registered from the signal line c, writes the event to the empty area notified by the signal line g from the empty area management circuit 14, and notifies the time management memory 12 of the address through e. The time management memory 12 registers this address as the last link of the event at the time received from the input event buffer 11 through b.

(Operation)

The operation of the configuration of the present invention shown in FIG. 1 is performed as follows.

When the event packet output from the evaluation pipeline 5 is input to the input event buffer 11, the relative time TIME corresponding to the delay time of the detailed delay is i, and the current time in the logic simulation device is n. Then, the change time at which the event EVENT should be scheduled is given by n + i, and the address (n + i) of the time management memory 12 is accessed. At address (n + 1), there is a pointer to the event list memory 13,
Includes pointers As and Ae to the first and last two addresses of the chain of the event whose output value changes at the pointer change time n + i.

On the other hand, EVENT of the input event buffer 11 is the event list memory given by the empty area management circuit 14.
Stored in one of the 13 empty areas. Therefore, the pointer Ae in the time management memory 12 is updated with this storage address, and this address is deleted from the empty area managed by the empty area management circuit 14.

The corresponding event at the change time is read by accessing the time management memory 12 at the address of the current time, accessing the event list memory 13 using the obtained pointer, and sequentially reading the chain of events. Done. The read event is output to the fan-out pipeline 3 via the output event buffer 15.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS.

FIG. 2 shows an embodiment configuration of the logic simulation apparatus. The configuration shown is basically the same as the configuration of the conventional device described with reference to FIG. 5, so that the components in FIG. 2 are indicated by the same reference numerals as those in FIG.

2 is different from the conventional apparatus in FIG. 5 in that the evaluation pipeline 5 in FIG. 2 detects a gate whose output value has been changed and determines the change time relative to the current time. To create and send the event packet 5a specified in the above to the event schedule device 6.
The event scheduler 6 has a unique configuration as described with reference to FIG.

The details of the embodiment of the event schedule apparatus 6 will be described with reference to FIGS.

FIG. 3 is an explanatory diagram of the time management memory 12 and the event list memory 13. The time management memory 12 includes a pointer A indicating the current time and a register B having a relative time. The time management memory 12 stores the start address (FIRS) on the event list memory 13 of the event registered at each time.
T) and the last address (LAST).

The value of FIRST indicated by the current time pointer A is sent to the event list memory 13 through the signal line d.

The event list memory 13 has an N for linking the event storing the event data and the event at the same time.
It consists of EXT LINK. The event at the current time is read out one after another following this NEXT LINK, and sent to the output event buffer 15 in FIG. 1 through h. Since the area read out here is reusable, the values of FIRST and LAST are notified to the empty area management circuit 14 through f in order to register the area as an empty area.

FIG. 4 is an explanatory diagram of the empty area management circuit 14. The empty area management circuit 14 includes a pointer to an empty area start address C and an empty area end address D.

All empty areas in the event list memory 13 are NEXT
One chain is configured using LINK. In the initial state, all event lists are in one chain. Address C points to the beginning of this chain, and address D points to the end.

The update of the free area is performed as follows. NE pointed to by C
Write FIRST value in XT LINK. Write the value of LAST in D. These steps are completed in two steps, but since they can be operated in parallel, they are actually completed in one cycle.

When the output of the event is completed, FIRST and LAST of the current time in the time management memory 12 in FIG. 3 are cleared to zero.

Registration of an input event is performed as follows. First, when the relative time TIME to be registered is notified from the input event buffer 11 of FIG. 1 through the b to the time management memory 12 of FIG. 3, the time management memory indicates the current time + the relative time.
12 contents FIRST and LAST are read.

The event to be registered is the event
It is transmitted to the list memory 13, and through g, the empty area management circuit 14
Is written to the EVENT of the event list memory 13 (FIG. 3) pointed to by the empty area address notified from. Write 0 to NEXT LINK indicated by this address. Next processing is FIRS
It is different when the value of T is 0 and other than 0. If FIRST = 0 (that is, the event at that time has not been registered before), the address at which the event was written (via the event list memory 13 through e in FIG. 1) is stored in both FIRST and LAST indicated by A + B of 2. To be notified).

If FIRST is not 0, first write the address that wrote the event to the NEXT LINK pointed to by LAST. Next, time management memory
In the LAST pointed to by A + B, write the address where the event was written. The C of the empty area management circuit shown in FIG.
NEXT LINK of event list memory 13 pointed to by
Is written, and the empty area management link is updated.

The device of this embodiment operates as follows. First, when the time of the logic simulation device is updated, the time management memory 12
Is counted up, the event scheduled at that time is read from the event list memory 13, and output through i. During this time, event packets to be scheduled at an arbitrary relative time are input to the input event buffer 11 through a, and these are stored in the buffer 11. When there are no more events to be output at the current time in the event list memory 13, the input events are extracted from the buffer 11 and registered.

The value of the detail delay is quantized and modeled. For example, in order to handle delays up to 100 nsec with 0, 1 nsec as the minimum unit, it is necessary to define 0, 1 nsec as 1 unit time, and handle a relative time of 1000 units at maximum.

The depth of the address of the time management memory 12 needs to be the maximum value of the relative time. This value is set to 2 N (N is an integer). (For example, 1024). The bit length of the current time pointer is N. When the time increases by one unit time, it is counted up, but when it reaches MAX, it becomes 0 (ignoring overflow), so that the memory can be used cyclically.

〔The invention's effect〕

By using the device of the present invention, it is possible to configure a logic simulation device capable of executing a dynamic simulation of a logic circuit handling a detailed delay at a high speed with a small amount of memory.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a block diagram of an embodiment of a logic simulation apparatus according to the present invention, FIG. 3 is an explanatory diagram of a time management memory and an event list memory, and FIG. FIG. 5 is an explanatory diagram of a circuit, FIG. 5 is a basic configuration diagram of a conventional logic simulation device, FIG. 6 is an explanatory diagram showing an example of a logic circuit, and FIG. 7 is a diagram showing a method of managing event data in a conventional event schedule device. FIG. In Fig. 1: 3: Fan-out pipeline 5: Evaluation pipeline 6: Event scheduler 11: Input event buffer 12: Time management memory 13: Event list memory 14: Empty area management circuit 15: Output event ·buffer

Claims (1)

(57) [Claims] 1. A logic gate for changing an output value in response to a change in a given input value among logic gates of a logic circuit to be evaluated, and a change in the output value is defined as an event,
In addition, an evaluation pipeline that specifies the time at which the event is enabled by a relative time corresponding to the delay time, and a logic gate that changes the input value of the fan-out destination for each logic gate that changes the output value specified by the event Pipeline, net status memory that stores the output state value of each gate, and events output from the evaluation pipeline are scheduled at a specified time, and the specified time has arrived When the event simulation unit supplies the event to the fan-out pipeline and updates the value of the net status memory, the event schedule unit stores the event data at the same time. Event that stores a link to a chain A list memory and a time-corresponding address, and the addresses point to the start and end addresses of the chain of events in the event list memory in which the time corresponding to the address is a designated time. And a free space management circuit that manages the free space by using the free space in the event list memory as a chain and using the first and last addresses as pointers. Reading the pointers indicating the beginning and end of the event chain in the event list memory stored at the address corresponding to the time, and sequentially reading the event data linked to the corresponding chain from the event list memory After reading, pointers indicating the beginning and end of the chain are Notify space management circuit, a logic simulation apparatus for causing registered as an empty area in the free area management circuit.