JP2921563B2 - Method of forming memory cell using corrugated oxide spacer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing an IC DRAM, and more particularly to a method of manufacturing a stacked DRAM.
DRAM).

[0002]

2. Description of the Related Art A typical stacked DRAM includes a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor) on a silicon semiconductor wafer.
actor Field Effect Transi
Stor: MOSFET) and a capacitor, and a source electrode of the semiconductor field effect transistor is connected to a lower electrode (Storage Node) of the capacitor to form a DRAM memory cell (Memory Cell). Are collected to form a memory IC.

In recent years, the integration density of DRAMs (Pac
King Density is increasing rapidly, and already, memory cells are now 1.5 square microns (u).
m ² ) are to be mass-produced with a capacity of 64 million bits.
In 5 years, the company announced that it had developed a 1 billion bit (1 GB) DRAM prototype.

In order to achieve the purpose of the high integration of the DRAM, it is necessary to reduce the size of the memory cell.
There is a need to reduce the size of field effect transistors and capacitors. However, the reduction in the size of the capacitor causes a decrease in the capacitance value, and the ratio of the signal to the noise of the memory circuit (Si
(G / Noise; S / N) was reduced, and defects such as erroneous determination of the circuit and instability of the circuit were formed.

[0005] In order to maintain or increase the capacitance value of the capacitor when the size of the capacitor is reduced, a fin-shaped capacitor disclosed in US Pat. No. 5,021,357 by Masao Taguchi of Fujitsu Ltd. or the like is disclosed. The structure is most representative. However, this fin-type capacitor structure has the following disadvantages. That is, first, since the fins on both sides are formed by connecting different polysilicons, the lower electrode (Storage N) is used.
second, the geometry of the lower electrode is relatively sharp, especially at its edge locations, where local breakdown of the capacitor dielectric layer occurs.
Is easy to occur.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a stack capacitor (Stack Capaci) having a high capacitance.
(tor) manufacturing method.

[0007] The present invention next provides a highly integrated stack DR.
It is an object to provide a method for manufacturing an AM.

[0008]

According to the first aspect of the present invention, there is provided a silicon semiconductor substrate (Silicon Semiconductor).
field oxide layer (Oxi)
de) is formed to isolate the field effect transistor, to form a field effect transistor including a gate oxide layer (Gage Oxide), a gate electrode, and a source and drain electrode, and a word line (Word Line); One neutral silicon dioxide layer (Non-doped
A silicon nitride layer is formed, a silicon nitride layer is formed, plasma silicon dioxide (PE-Oxide) and thermal chemical vapor grown silicon dioxide (Thermal CVD O) are formed.
xide) is alternately deposited, and an alternate multilayer structure (Alt)
forming the active layers, and using a lithography technique to form a capacitor area (Capacito).
r Region) to form a photoresist pattern,
Utilizing an etching technique to etch the alternating multilayer structure described above, the etching terminating at the silicon nitride layer described above;
Lateral etching using hydrofluoric acid solution (Later
al Etch) to remove a portion of the above-mentioned plasma silicon dioxide and the thermal chemical vapor grown silicon dioxide, and between the above-mentioned silicon nitride layer and the thermal chemical vapor grown silicon dioxide, Cavities are formed between the phase-grown silicon dioxide, then the photoresist pattern is removed, the capacitor area is etched using an etching technique to remove the silicon nitride layer and the neutral silicon dioxide layer, A cell contact (Cell Contact) of the field-effect transistor is formed, one first polysilicon layer is formed, and the first polysilicon layer fills the above-mentioned cavity and straddles the above-mentioned cell contact. The first polysilicon layer is removed by etching the above capacitor area using a technique and an etching technique. Lower electrodes of the capacitor (Stor
Age Node), one capacitor dielectric layer (Capacitor Dielectric) is formed, and one second polysilicon is formed. The second polysilicon layer has conductivity through impurity introduction (Doped). By using the lithography technique and the etching technique, the above-described second polysilicon layer and the capacitor dielectric layer are etched to form a capacitor.

According to a second aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the neutral silicon dioxide layer in the stacked DRAM is an impurity-free silicon dioxide (Undoped Sd).
The method is a method of manufacturing a stacked DRAM having a composition of silicon dioxide and a thickness of 2,000 to 3,000 angstroms.

According to a third aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the silicon nitride layer includes:
Stacked DRAM formed using chemical vapor deposition and having a thickness of 500 to 1500 angstroms.
Manufacturing method.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the plasma silicon dioxide having an alternating multilayer structure is formed by a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition).
The stacked DRAM is formed using Vapor Deposition (PECVD), and each layer has a thickness of 200 to 400 Å.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect of the present invention, wherein the thermal chemical vapor deposition silicon dioxide having an alternate multilayer structure is formed by low pressure chemical vapor deposition or atmospheric pressure. It is formed using a chemical vapor deposition (APCVD), a sub-atmospheric pressure chemical vapor deposition (SACVD), or another chemical vapor deposition, and each layer has a thickness of 200.
DRAM from 400 Å to 400 Å
Manufacturing method.

According to a sixth aspect of the present invention, there is provided the method of manufacturing a stacked DRAM according to the first aspect, wherein the first polysilicon layer is formed by using a chemical vapor deposition method and has a thickness of 20 nm.
Stack D from 00 to 5000 Angstroms
This is a method for manufacturing a RAM.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the capacitor dielectric layer is composed of silicon oxynitride, silicon nitride and silicon dioxide, or This is a method for manufacturing a stacked DRAM composed of tantalum oxide (Ta ₂ O ₅ ).

According to an eighth aspect of the present invention, there is provided the method of manufacturing a stacked DRAM according to the first aspect, wherein the second polysilicon layer is formed by using a chemical vapor deposition method and has a thickness of 1: 1.
The manufacturing method of the stacked DRAM is set to 2,000 to 2,000 angstroms.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein a polysilicon layer (R) having a rough surface is formed before forming a capacitor dielectric layer.
ugged Surface Polysilico
n) to form a stacked DRAM.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacturing method of the present invention is as follows. First, a silicon semiconductor substrate (Silicon
A field oxide layer and a field-effect transistor are manufactured on a semiconductor substrate. Subsequently, one neutral silicon dioxide layer (Non-doped)
(Silicate Glass), followed by one silicon nitride layer (Silicon Nitride)
To an etch stop layer (Etch-Stop Layer).
r).

Thereafter, plasma-enhanced chemical vapor deposition (Plasma Enhanced Chemical Method)
A first plasma silicon dioxide (First) layer is formed using Vapor Deposition (PECVD).
PE-Oxide) is formed, followed by Thermal Chemical Vapor Deposition (Thermal Chemical VaporD)
using a first thermal chemical vapor deposition silicon dioxide (First Thermal C)
VD Oxide), and further forming a second plasma silicon dioxide, a second thermal chemical vapor deposition silicon dioxide, a third plasma silicon dioxide, and a third thermal chemical vapor deposition silicon dioxide, thereby forming an alternating multilayer structure. (Alternative
Layers).

Subsequently, a photoresist pattern is formed in the capacitor area using lithography technology, and the first plasma silicon dioxide, the first thermal chemical vapor deposition silicon dioxide, Etching is performed on the second plasma silicon dioxide, the second thermal chemical vapor deposition silicon dioxide, the third plasma silicon dioxide, and the third thermal chemical vapor deposition silicon dioxide. The plasma etch terminates at the silicon nitride layer described above. Then, using a hydrofluoric acid solution, a part of the first plasma silicon dioxide, the first thermal chemical vapor deposition silicon dioxide, the second plasma silicon dioxide, the second thermal chemical vapor deposition silicon dioxide, 3 plasma silicon dioxide, the third thermal chemical vapor deposition silicon dioxide is etched, and the etching rate of the plasma silicon dioxide is higher than that of the thermal chemical vapor deposition silicon dioxide. Cavity is formed between the second and third thermal chemical vapor deposition silicon dioxides during the second thermal chemical vapor deposition silicon dioxide.

Subsequently, the silicon nitride layer and the neutral silicon dioxide layer are removed from the capacitor area by using a plasma etching technique, thereby forming a cell contact of a field effect transistor. Thereafter, the above-mentioned photoresist pattern is removed. Thereafter, the lower electrode of the capacitor is electrically contacted with the source electrode of the field effect transistor via the cell contact.

Subsequently, a first polysilicon layer is deposited. The first polysilicon layer is made conductive by introducing impurities, and is provided so as to straddle the above-mentioned cell contact. Thereafter, the first polysilicon layer is removed from the capacitor area using a lithography technique and a plasma etching technique, thereby forming a lower electrode (Storage Node) of the capacitor. After that, a polysilicon layer having a rough surface (Rugged
Polysilicon), followed by a capacitor dielectric layer and a second polysilicon layer. The above-mentioned second polysilicon layer is also made conductive by introducing impurities. Finally, the second polysilicon layer, the capacitor dielectric layer, and the polysilicon layer having a rough surface are etched using a lithography technique and a plasma etching technique, thereby forming an upper electrode (Plate) of the capacitor.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. In the present invention, first, the p-type semiconductor substrate 10 (Sili) in the crystal lattice direction (100) is used.
con Semiconductor Substr
a), a field oxide layer 12 is formed thereon. In-situ oxidation layer 1
2 is usually to thermally oxidize the p-type semiconductor substrate 10 (T
thermal oxidized and has a thickness between 2000 Å and 6000 Å and is used to isolate field effect transistors. Thereafter, forming a metal oxide field effect transistor, the metal oxide field effect transistor described above includes a gate oxide layer 14, a gate pole 16, and source and drain poles 18.

As shown in FIG. 1, the above-mentioned gate oxide layer 14 is formed on the surface of the above-mentioned p-type semiconductor substrate 10 by thermal oxidation, has a thickness between 40 and 300 Å, and has the above-mentioned gate electrode. Reference numeral 16 denotes a low pressure chemical vapor deposition method (Low Pressure Chemical Vap).
or Deposition (LPCVD), and has a thickness of 1000 to 300.
0 angstrom. The above-mentioned source electrode and drain electrode 18 are formed using an ion layout technique, and the type of the ions is arsenic ion (As ⁷⁵ ).
The amount of the ion layout agent is from 1E15 to 5E16.
Atoms / square centimeter, and the ion layout energy is 40-100 kev.

Next, as shown in FIG. 2, a single neutral silicon dioxide layer 20 and a single silicon nitride layer 22
(Silicon Nitride). The neutral silicon dioxide layer 20 is usually formed using a low-pressure chemical vapor deposition method and is free from impurities.
n-doped silicon dioxide, and the reaction gas at the time of its formation is tetraethoxysilane (T
EtraEthOxySilane (TEOS) and oxygen gas, or silicon methane (monosilane) and oxygen gas at a reaction temperature of about 720 ° C. and a reaction pressure of 0.2
From 0.4 torr to 2000 to 30 tons
00 angstrom. The aforementioned silicon nitride layer 22
Is formed using a low pressure chemical vapor deposition, the reaction gas was set to SiH2Cl ₂ and NH _3, the reaction temperature is about 72
At 0 ° C., the reaction pressure is between 0.2 and 0.4 torr, and its thickness is between 500 and 1500 angstroms. The effect of the silicon nitride layer 22 described above is that it serves as an etch-stop layer for the subsequent etching.

Next, as shown in FIG. 3, the plasma-enhanced chemical vapor deposition (Plasma Enha)
nounced Chemical Vapor Depos
a first plasma silicon dioxide 24 (First PE-Oxide) using PECVD
Is formed, and then a first thermal chemical vapor deposition silicon dioxide layer 26 (First Th) is formed using a chemical vapor deposition method.
thermal CVD oxide). further,
Forming a second plasma silicon dioxide 28, a second thermal chemical vapor deposition silicon dioxide 30, a third plasma silicon dioxide 32, a third thermal chemical vapor deposition silicon dioxide 34,
The alternate multilayer structure (Alternative Layer)
rs). As shown in FIG. 3, the reaction gases used to form the first, second, and third plasma silicon dioxide using plasma enhanced chemical vapor deposition are SiH ₄ and N 2.
₂ O, the reaction temperature is from 300 ° C to 400 ° C,
As described above, when the first, second, and third thermal chemical vapor deposition silicon dioxides are formed using low pressure chemical vapor deposition,
The reaction gas is SiH ₂ Cl ₂ and N ₂ O or SiH _{4 and N}
And ₂ O, the reaction temperature is set to 900 ° C. from 750 ° C.. The first plasma silicon dioxide 24, the first thermal chemical vapor grown silicon dioxide 26, the second plasma silicon dioxide 28, the second thermal chemical vapor grown silicon dioxide 30, the third plasma silicon dioxide 32, the third thermal chemical The thickness of each layer of the multilayer structure composed of the phase-grown silicon dioxide 34 is 200 to 4
00 angstrom. Etch selectivity (Etch Se) of each of the above plasma silicon dioxide to thermochemical vapor grown silicon dioxide in hydrofluoric acid solution
The efficiency is approximately 4 to 1, i.e., the etch rate of plasma silicon dioxide is faster than the thermal chemical vapor deposition silicon dioxide described above. The method for forming the above-mentioned thermal chemical vapor deposition silicon dioxide includes low-pressure chemical vapor deposition,
Atmospheric pressure chemical vapor deposition, or subatmospheric pressure chemical vapor deposition (Sub: Atomsphere Chemical)
Various chemical vapor deposition methods such as Vapor Deposition (SACVD) can be used.

Next, please refer to FIGS. Subsequently, a photoresist pattern 36 is formed in a capacitor region using a lithography technique. This is as shown in FIG. Further, the first plasma silicon dioxide 24, the first thermal chemical vapor deposition silicon dioxide 26, the second plasma silicon dioxide 28, the second thermal chemical vapor deposition silicon dioxide 30, the third plasma silicon dioxide using the plasma etching technique. 32, etching the third thermal chemical vapor deposition silicon dioxide 34; The above-described plasma etching terminates at the silicon nitride layer 22. Then, hydrofluoric acid solution (HF)
Using lateral etching (lateral Etc)
h) and a portion of said first plasma silicon dioxide 2
4. Removal of first thermal chemical vapor grown silicon dioxide 26, second plasma silicon dioxide 28, second thermal chemical vapor grown silicon dioxide 30, third plasma silicon dioxide 32, third thermal chemical vapor grown silicon dioxide 34 I do. Since the etching rate of the above-mentioned plasma silicon dioxide is faster than that of the thermal chemical vapor grown silicon dioxide, the etching rate of the first thermal chemical vapor grown silicon dioxide between the silicon nitride layer 22 and the first thermal chemical vapor grown silicon dioxide 26 is increased. 26 and second thermochemical vapor grown silicon dioxide 30
Between the second thermal chemical vapor grown silicon dioxide 30 and the third thermal chemical vapor grown silicon dioxide 34, respectively.
(Cavity) is formed. As shown in FIG. 5, subsequently, the silicon nitride layer 22 and the neutral silicon dioxide layer 2 are removed from the capacitor area using a plasma etching technique.
0 is removed to expose the source electrode 18 of the field effect transistor.
9 is formed, and then the photoresist pattern 36 described above is formed.
Is removed to obtain the state shown in FIG. Later, the lower electrode of the capacitor is electrically contacted with the source electrode 18 of the field effect transistor via the cell contact 39 described above.

The first plasma silicon dioxide 24, the first thermal chemical vapor grown silicon dioxide 26, the second plasma silicon dioxide 28, the second thermal chemical vapor grown silicon dioxide 30,
The plasma etching of the third plasma silicon dioxide 32 and the third thermal chemical vapor deposition silicon dioxide 34 is generally performed by a magnetic field enhanced active ion plasma etching (Mag).
netic Enhanced Reactive I
on Etching; MERIE) or traditional active ion plasma etching (Reactive I
on Etching; RIE), and the plasma reaction gas is generally CF ₄ and CHF ₃ .

Next, please refer to FIG. 7 to FIG. Subsequently, a first polysilicon layer 40 is deposited. The first polysilicon layer 40 has conductivity through the introduction of impurities (Doped), fills the above-mentioned cavity 37, and bridges the above-mentioned cell contact 39, thereby forming the source electrode of the above-mentioned field-effect transistor. 18 and make electrical contact. This is as shown in FIG. Then, using lithography technology and plasma etching technology,
The first polysilicon layer 4 from the capacitor area
0 is removed, and the lower electrode 42 of the capacitor (Stor
age Node). This is as shown in FIG. Then, using a hydrofluoric acid solution, the remaining first plasma silicon dioxide 24, first thermal chemical vapor deposition silicon dioxide 26, second plasma silicon dioxide 28,
Second thermal chemical vapor grown silicon dioxide 30, third plasma silicon dioxide 32, third thermal chemical vapor grown silicon dioxide 34
Is removed. This is as shown in FIG. The above-mentioned first polysilicon layer 40 is usually formed by a low-pressure chemical vapor deposition method, and is formed by introducing an in-situ
The reaction proceeds in the manner of (Doped), the reaction impurity atom is a phosphorus atom, the reaction gas is a mixed gas of PH ₃ and SiH ₄ , the reaction temperature is 520 to 580 ° C. and the thickness is 200
It should be between 0 and 5000 angstroms. The plasma etching of the first polysilicon layer 40 described above usually includes
Magnetic field enhanced active ion plasma etching (Magn
etic Enhanced Reactive Io
n Etching (MERIE), and the plasma reaction gas is generally a gas containing chlorine such as CCl ₄ and Cl ₂ .

Finally, using a standard manufacturing process, one roughened polysilicon layer 44 (Rugged S) is formed.
(polysilicon), and then a capacitor dielectric layer 46 and a second polysilicon layer 48 are formed. This is as shown in FIG. It is assumed that the polysilicon layer 44 and the second polysilicon layer 48 having the rough surfaces have conductivity by being doped with impurities (Doped). Further, using the lithography technique and the plasma etching technique, the above-mentioned second polysilicon layer 48, capacitor dielectric layer 46 and polysilicon layer 4 having a rough surface are used.
4 is etched, thereby forming the upper electrode (Pla) of the capacitor.
te) to form the complete capacitor shown in FIG.

The aforementioned polysilicon layer 44 having a rough surface is formed by using a chemical vapor deposition method, and has a thickness of 300 to 1000 angstroms. The capacitor dielectric layer 46 described above is typically composed of silicon dioxide, silicon nitride, and silicon oxynitride. The silicon dioxide described above does not thermally oxidize the rough polysilicon layer 44 and has a thickness of 50 to 200 angstroms. The above-mentioned silicon nitride is formed by a low-pressure chemical vapor deposition method and has a thickness of 40 to 60 angstroms. The above-mentioned silicon oxynitride is obtained by oxidizing the above-mentioned silicon nitride and has a thickness of 20 to 50 angstroms. The above-mentioned second polysilicon layer 48 is usually formed by using a low-pressure chemical vapor deposition method and also by a method of introducing a synchronous impurity. The reactive impurity atoms are phosphorus atoms, and the reactive gases are PH ₃ and S _3.
iH ₄ gas mixture, the reaction temperature is 520 to 580 ° C,
Its thickness is between 1000 and 2000 angstroms.

[0031]

The present invention relates to a DRAM, particularly a stack DR.
The present invention relates to a method for manufacturing an AM, and relates to a plasma enhanced chemical vapor deposition method (Plasma Enhanced Ch).
electronic Vapor Deposition: P
Plasma silicon dioxide formed by ECVD and Thermal Chemical Vapor Deposition (Thermal Chemical Vap)
or Deposition) by alternately combining thermochemical vapor grown silicon dioxide to form an alternating multilayer structure.
Above the cell contact of the memory cell, a corrugated oxide space (Corrugated Oxide Space)
r), thereby forming the lower electrode (St) of the capacitor.
and increases the capacity of the capacitor significantly, and this high-capacity stacked capacitor can be applied to the production and manufacture of a high-density stacked DRAM of 16 million bits (16 MB) or more. It is.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a process of a manufacturing method according to the present invention.

FIG. 2 is a sectional view illustrating a process of a manufacturing method according to the present invention.

FIG. 3 is a cross-sectional view illustrating a process of a manufacturing method according to the present invention.

FIG. 4 is a cross-sectional view showing the process of the manufacturing method of the present invention.

FIG. 5 is a cross-sectional view showing the process of the manufacturing method of the present invention.

FIG. 6 is a cross-sectional view showing the process of the manufacturing method of the present invention.

FIG. 7 is a cross-sectional view showing the process of the manufacturing method of the present invention.

FIG. 8 is a cross-sectional view showing the process of the manufacturing method of the present invention.

FIG. 9 is a cross-sectional view showing the process of the manufacturing method of the present invention.

FIG. 10 is a cross-sectional view showing the process of the manufacturing method of the present invention.

FIG. 11 is a cross-sectional view showing the process of the manufacturing method of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... p-type semiconductor substrate 12 ... Field oxide layer 14
... Gate oxide layer 16 ... Gate electrode 18 ... Source and drain electrodes 20 ... Neutral silicon dioxide layer 22 ... Silicon nitride layer 24 ... First plasma silicon dioxide 26 ... First thermal chemical vapor grown silicon dioxide 28 ... second plasma silicon dioxide 30 ... second thermal chemical vapor grown silicon dioxide 32 ... third plasma silicon dioxide 34 ... third thermal chemical vapor Grown silicon dioxide 36 photoresist pattern 37 cavity 39 cell contact 40 first polysilicon layer 42 lower electrode of capacitor 44 polysilicon layer 46 with rough surface ..Capacitor dielectric layer 48... Second polysilicon layer

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-206400 (JP, A) JP-A-3-77365 (JP, A) JP-A-56-147451 (JP, A) JP-A-4- 340270 (JP, A) JP-A-7-307395 (JP, A) JP-A-6-151176 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/108 H01L 21 / 822 H01L 21/8242 H01L 27/04

Claims (9)

(57) [Claims] 1. A silicon semiconductor substrate (Silicon)
Forming a field oxide layer (Oxide) on the Semiconductor Substrate and using it to isolate the field effect transistor; a field effect transistor including a gate oxide layer (Gage Oxide), a gate electrode, and a source and drain electrode;
A word line is formed, and one neutral silicon dioxide layer (Non-doped Si) is formed.
silicate glass) and one silicon nitride layer (Silicon Nitrid).
e), plasma silicon dioxide (PE-Oxide) and thermal CVD silicon dioxide (Thermal CVD Oxi)
de) are alternately deposited (Alter).
native layers, and using lithography technology to form a capacitor area (Capa).
A photoresist pattern is formed on the C.T.R. (Citor Region), and the above-mentioned alternate multilayer structure is etched by using an etching technique. Later
al Etch) to remove a portion of the above-mentioned plasma silicon dioxide and the thermal chemical vapor grown silicon dioxide, and between the above-mentioned silicon nitride layer and the thermal chemical vapor grown silicon dioxide, Cavities are formed between the phase-grown silicon dioxide, then the photoresist pattern is removed, the capacitor area is etched using an etching technique to remove the silicon nitride layer and the neutral silicon dioxide layer, Field contact of a field effect transistor (Cell Co)
ntact) to form one first polysilicon layer, which fills the above-mentioned cavity and straddles the above-mentioned cell contact, and utilizes lithography technology and etching technology. The above-mentioned capacitor area is etched to remove the first polysilicon layer, thereby forming the lower electrode of the capacitor (Storage N).
mode) and one capacitor dielectric layer (Capacitor Die)
lectric), one second polysilicon layer is formed, the second polysilicon layer is made to have conductivity through impurity introduction (Doped), and the second polysilicon layer is formed using lithography technology and etching technology. A method of manufacturing a stacked DRAM, comprising the steps of etching a polysilicon layer and a capacitor dielectric layer to form a capacitor. 2. The method for manufacturing a stacked DRAM according to claim 1, wherein the neutral silicon dioxide layer in the stacked DRAM is an impurity-free silicon dioxide.
ioxide), and its thickness is from 2000 to 30
A method of manufacturing a stacked DRAM having a thickness of 00 Å. 3. The method of claim 1, wherein the silicon nitride layer is formed using a chemical vapor deposition method and has a thickness of 500 to 1500 Å. A method for manufacturing a DRAM. 4. The method according to claim 1, wherein the plasma silicon dioxide having an alternating multilayer structure is formed by plasma enhanced chemical vapor deposition (Plasma E).
enhanced Chemical Vapor De
A method of manufacturing a stacked DRAM, wherein the stacked DRAM is formed by using position (PECVD), and each layer has a thickness of 200 to 400 Å. 5. The method for manufacturing a stacked DRAM according to claim 1, wherein the alternating multi-layer structure thermal chemical vapor deposition silicon dioxide is formed by low pressure chemical vapor deposition or atmospheric pressure chemical vapor deposition. A method of manufacturing a stacked DRAM, wherein the thickness of each layer is 200 to 400 angstroms formed by using (APCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), or other chemical vapor deposition. 6. The method of claim 1, wherein the first polysilicon layer is formed by using a chemical vapor deposition method, and has a thickness of 2,000 to 5,000.
A method for manufacturing a stacked DRAM having an angle of Å. 7. The method of claim 1, wherein the dielectric layer of the capacitor comprises silicon oxynitride, silicon nitride and silicon dioxide, or tantalum pentoxide (Ta). ₂ O
₅ ) A method for manufacturing a stacked DRAM, comprising the method described in ₅ ). 8. The method of claim 1, wherein the second polysilicon layer is formed by using a chemical vapor deposition method, and has a thickness of 1000 to 200.
A method of manufacturing a stacked DRAM having 0 angstrom. 9. The method of claim 1, wherein the step of forming the capacitor dielectric layer comprises:
One rough surface polysilicon layer (Rugged Su)
(Face Polysilicon).