JP3172231B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a capacitor structure in a DRAM or the like.

[0002]

2. Description of the Related Art In recent years, so-called MOS type semiconductor memory devices (DRAMs) have been rapidly advanced in integration and capacity due to advances in semiconductor technology, especially in fine processing technology.

With the increase in integration, the area of a capacitor for storing information (charge) is reduced. As a result, a memory error is read out erroneously, or a soft error in which the memory content is destroyed by α rays or the like. Is in question.

As one of the methods for solving such a problem and achieving high integration and large capacity, a MOS capacitor is laminated on a memory cell region, and one electrode of the capacitor and one electrode of the capacitor are formed on a semiconductor substrate. A memory cell structure called a stacked memory cell in which the formed switching transistor is electrically connected to one electrode to substantially increase the area occupied by the capacitor and increase the capacitance of the MOS capacitor Has been proposed.

[0005] In such a structure, the storage node electrode can be extended to above the element isolation region.
Since the thickness of the storage node electrode is increased and the side wall thereof can be used as a capacitor, the capacitance of the capacitor can be increased several times or more than that of the planar structure. Further, the diffusion layer in the storage node portion is limited to the diffusion layer region below the storage node electrode, and the area of the diffusion layer for collecting the charge generated by the α-ray is extremely small, and the cell is resistant to soft errors. It has a structure.

However, even in such a DRAM having a stacked memory cell structure, the area occupied by the memory cell is reduced as the elements are miniaturized due to higher integration, and the flat portion of the storage node electrode is reduced. The area has been increasingly reduced, and it has become difficult to secure sufficient capacitor capacitance.

For this reason, in order to secure the accumulated charge amount, in order to effectively use the side surface of the storage node electrode,
Its thickness must be as thick as at least about 1 μm. It is difficult to finely process such a thick storage node electrode, which causes a short circuit between the storage node electrodes. Further, this thick storage node electrode imposes a heavy burden on fine processing of the wiring thereon. Furthermore, doping of impurities by ion implantation or the like becomes insufficient, and it has been difficult to form a good contact with a substrate or a pad.

Various capacitor structures have recently been proposed in order to reduce the level difference. In any case, it is an object of the present invention to secure a sufficient capacitor capacity as the degree of integration increases.

[0009]

As described above, even in a DRAM having a stacked memory cell structure, as the elements are further miniaturized due to the higher integration, the occupied area of the memory cell is further reduced, and the accumulated charge is reduced. In order to secure a sufficient amount, the thickness of the storage node electrode must be increased, which causes a problem that contact characteristics deteriorate.

[0010] The present invention has been made in view of the above-mentioned circumstances, and is intended to further reduce the area occupied by memory cells.
It is an object of the present invention to provide a memory cell structure having good contact characteristics and capable of securing a sufficient capacitor capacity.

[0011]

Accordingly, the first D of the present invention is described.
In the RAM, horizontal stripe-shaped undulations are formed on at least a part of the side surface of the storage node electrode.

Preferably, the storage node electrode comprises:
It is formed outside the contact surface with the source / drain region so as to project substantially perpendicularly to the contact surface and with a curved surface.

According to a second method of the present invention, a standing wave is formed by interfering an incident wave and a reflected wave of light passing through a resist by photolithography, and undulations in the form of horizontal stripes are formed on the side surface of the resist. The storage node electrode having the horizontal stripe-shaped undulations on the side surfaces is formed by pattern transfer of the horizontal stripe-shaped undulations to the electrode material.

In the third method of the present invention, a film having a glass transition temperature is used as a transfer film, and polycrystalline silicon is used as an etching stopper when forming a storage node contact with the film. In the step of oxidizing the crystalline silicon film, at the same time, the transfer film is melted, the edge is rounded, and the storage node electrode is formed so as to cover the edge to obtain a storage node electrode having a curved side wall portion, Thereafter, the transfer film is removed, and both surfaces of the side wall are used as capacitors.

More preferably, after forming the first polycrystalline silicon film, a film having a glass transition temperature is formed and used as a pattern transfer film, and the first polycrystalline silicon film is used as an etching stopper for this film. A reverse pattern of the storage node contact is formed using silicon, the transfer film is melted, the edge is rounded, and a second polycrystalline silicon film is formed so as to cover the edge. Is etched to obtain a storage node electrode having a curved side wall, and both surfaces of the side wall are used as capacitors.

In a fourth method of the present invention, two kinds of films are alternately laminated, openings are formed in these multilayer films, and etching is performed under conditions such that the etching rates of the two kinds of films are different.
After forming a storage node contact having irregularities on the side wall, forming an electrode material in the storage node contact, removing the multilayer film and performing pattern transfer, and forming a storage node electrode having a projection with irregularities on the side wall. Has formed.

[0017]

According to the above-mentioned first structure, a horizontal stripe-like undulation is formed on a part of the side surface of the storage node electrode.
This undulation can increase the capacitor area. Therefore, the capacity can be increased without increasing the area occupied by the capacitor. Moreover, storage-
Since the surface area of the storage node electrode can be increased without increasing the thickness of the gate electrode, the processing is facilitated and a highly reliable DRAM can be obtained.

Further, if the storage node electrode projects outwardly from the contact surface with the source / drain region so as to be substantially perpendicular to the contact surface and to have a curved surface, the storage node can be further stored. The surface area of the node electrode can be increased.

According to the second method, the incident wave and the reflected wave of the light passing through the resist are caused to interfere with each other by photolithography to form a standing wave, and the horizontal stripe-shaped undulation is formed. A storage node electrode having horizontal stripes on the side surface can be formed by forming the shape on the side surface and transferring this shape. Therefore, the electrode material has a single-layer structure and is easy to manufacture. In addition, the period of the undulation can be controlled by the wavelength of light and the dielectric constant of the resist pattern, and the magnitude of the undulation can be controlled by the reflectance on the upper and lower surfaces of the resist, the light absorption in the resist, and the sensitivity of the resist. Can be controlled.

Further, according to the third method, the polycrystalline silicon film used as the etching stopper is oxidized simultaneously with the oxidation of the polycrystalline silicon film.
Since a film having a glass transition temperature, such as a PSG film, is melted to form a storage node electrode with a rounded edge to form a curved protruding piece on the periphery of the storage node electrode, the number of steps is increased. The surface area of the storage node electrode can be easily increased without any problem.

Preferably, after forming the first polycrystalline silicon film, the first polycrystalline silicon film is used as an etching stopper to form a reverse pattern of the storage node contact.
A film having a glass transition temperature, such as a PSG film, is patterned, then melted by heat treatment to form a rounded edge, then a second polycrystalline silicon film is formed, and the film having the glass transition temperature is removed. If the first polycrystalline silicon film is used as a storage node electrode and the second polycrystalline silicon film is used as a projecting piece curved at the periphery of the storage node electrode, the storage node electrode can be easily formed without increasing the number of steps. Surface area can be increased.

According to the fourth aspect of the present invention, two types of films are alternately laminated, and the multilayer film is etched under conditions such that the etching rates of the two types of films are different to form storage node contacts having irregularities on the side walls. After the electrode material is formed in the storage node contact, the multilayer film is removed and pattern transfer is performed to form a storage node electrode having a projection having irregularities on the side wall, so that the storage node can be easily formed. The surface area of the electrode can be increased.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a cross-sectional view showing two bits adjacent to each other in the bit line direction of a DRAM having a stacked memory cell structure according to a first embodiment of the present invention, and FIGS. c) is a drawing of the manufacturing process.

In this DRAM, a MOSFET is formed in a region surrounded by an element isolation insulating film 2 of a p-type silicon substrate 1, and a storage node electrode 10 is connected to one of a source / drain region of the MOSFET. The capacitor is formed by laminating horizontal stripes on the side surface of the storage node electrode 10 to increase the capacitor area. The other parts are the same as those of the conventional DRAM having the stacked memory cell structure.

That is, in the MOSFET, a gate electrode 5 is formed in a region surrounded by an element isolation insulating film 2 on a p-type silicon substrate 1 via a gate insulating film 4, and the source is self-aligned with the gate electrode 5. -It is constituted by forming n-type diffusion layers 6a and 6b to be drain diffusion layers.

A storage node electrode 10 is formed on the n-type diffusion layers 6a and 6b connected to the capacitor via a storage node contact 8, and a bit line 14 is formed on the n-type diffusion layer 6a via a bit line contact.
Is formed. At the bottom of the element isolation insulating film 2, a p @-type diffusion layer 3 for punch through stopper is formed.
In this structure, the capacitance corresponding to the sum of the undulations on the side surface of the storage node electrode can be obtained from the side wall portion.

Next, a method of manufacturing the DRAM will be described with reference to the drawings.

First, as shown in FIG.
An element isolation insulating film 2 made of a silicon oxide layer having a film thickness of 700 nm is formed on a p-type silicon substrate 1 of cm by a normal LOCOS method. At this time, the p-type diffusion layer 16 for punch through stopper is formed by the oxidation step. Thereafter, ion implantation for threshold control is performed in the element region as needed. Then, a 10-nm-thick silicon oxide layer and a 300-nm-thick polycrystalline silicon layer are formed by a thermal oxidation method, and these are patterned by a photolithography method and a reactive ion etching method to form a gate insulating film 4 and a gate insulating film. The gate electrode 5 is formed. Then, using this gate electrode 5 as a mask, As ions are ion-implanted to form an n-type diffusion layer 6.
Source / drain regions a and 6b are formed, and a MOSFET as a switching transistor is formed. The depth of this diffusion layer is, for example, about 150 nm.
Thereafter, an interlayer insulating film 7 made of a flat silicon oxide film is formed on the entire surface. For example, this may be formed by depositing phosphorus glass and then melting it by a heat process, or by shaping the silicon oxide film from the upper side by lapping after depositing a thick silicon oxide film or the like Etc. may be appropriately selected. In addition, when the pattern of the gate electrode becomes finer due to the high integration, a considerable flattening can be achieved simply by depositing the insulating film having a thickness of 1/2 or more of the space between the gate electrodes by a method having a good step coverage such as an LPCVD method. Becomes possible. This flattening is important in terms of keeping the thickness of the resist constant when forming the capacitor.

Further, a silicon nitride film 7s is deposited as an etching stopper for etching the LPD film for transferring the horizontal stripe pattern of the resist.

Thereafter, after forming the storage node contact 8, a resist is applied, and exposure is performed by photolithography using a mask having a pattern slightly smaller than the pattern of the storage node electrode. If monochromatic light such as an excimer laser is used as a light source for this exposure, light incident on the photoresist and light reflected from the base interfere with each other, and a standing wave is generated in the resist. For this reason, the light intensity in the resist changes periodically in the depth direction, so that the side surface of the photoresist pattern R has a horizontal stripe-like undulation as shown in FIG. When the LPD film 9 is deposited on this upper layer, the LPD film 9 is not formed on the resist pattern, so that the pattern shape of the resist is transferred. Alternatively, a film may be deposited by a vapor deposition or sputtering method and etched back. Thereafter, when the storage node electrode is formed by removing the resist, the undulations in the form of horizontal stripes are transferred to the side surface of the LPD film as the pattern transfer film.

Then, as shown in FIG. 2B, for example, a polycrystalline silicon film is
After depositing 00 nm and doping this with arsenic or phosphorus, patterning is performed by photolithography and reactive ion etching to form a storage node electrode 10.

Here, the LPD film becomes a silicon oxide film by heating and can be used as it is as an interlayer insulating film. However, since the side surface of the storage node electrode is used as a capacitor, it is removed by etching using ammonium fluoride. I am trying to do it. At this time, the silicon nitride film 7s is used as an etching stopper.

After the LPD film 9 is removed by etching in this manner, a silicon nitride film is deposited on the entire surface by LPCVD to a thickness of about 10 nm and oxidized in a steam atmosphere at 950 ° C. for about 30 minutes to form a capacitor insulating film 11. . Thereafter, a polycrystalline silicon film is deposited on the entire surface, and doped with arsenic or phosphorus, and then a plate electrode 12 is formed by photolithography and dry etching (FIG. 2C).

Next, a CVD oxide film is deposited as an interlayer insulating film on the entire surface, a bit line contact is formed by photolithography and reactive ion etching, and a bit line 14 using an aluminum film or molybdenum polycide is formed. Thus, the DRAM shown in FIG. 1 is completed.

According to the above configuration, since horizontal stripes are formed on the side surface of the storage node electrode, as a result, a large capacitor capacity can be realized with a small occupied area.

Next, the principle of generating a standing wave for forming horizontal stripes will be described.

FIG. 3A shows that monochromatic light is incident on the photoresist from the atmosphere, passes through the () resist pattern and the underlying silicon oxide film, is reflected by the () silicon substrate, and passes through the resist again. Actually, it is shown that the light is reflected () at the interface between the resist and the atmosphere. The above steps are repeated. (b)
Indicates the intensity ε2 of the incident wave and the intensity ε3 of the reflected wave. The phase shifts when reflected on the silicon substrate surface. When the incident wave and the reflected wave having different phases are added together, a standing wave is generated in the resist film as shown in FIG. The standing wave has nodes of maximum intensity and nodes of minimum intensity, and is generated periodically through the membrane. This periodic light intensity distribution appears as undulations in the horizontal stripes of the resist pattern. This is because the solubility of the resist in the developing solution is proportional to the exposure intensity distribution. In this way, a resist pattern having lateral stripes can be obtained.

In the above embodiment, the pattern of the storage node electrode is formed to be larger than the resist pattern used for forming the undulations due to the standing wave.
After resist is deposited on the entire surface as shown in, the entire surface is exposed,
By controlling the exposure amount so that only the inside of the storage node contact is not exposed, only the resist buried in the storage node contact can be left. Then, by performing dry etching in this state to remove unnecessary portions of polycrystalline silicon, a storage node electrode can be formed in a self-aligned manner with respect to the storage node contact.

Embodiment 2 Next, a second embodiment of the present invention will be described.

In the above embodiment, when the wavelength of the stepper used for exposure becomes shorter, the period of the irregularities formed by the standing wave becomes λ / 4n, so the period of the irregularities also becomes shorter. Then, the unevenness is filled with the film thickness of the storage node electrode, and the unevenness on the side not facing the resist pattern is eliminated. Therefore, in order to further increase the surface area of the storage node electrode, the deposition conditions of polycrystalline silicon as a storage node electrode material are controlled to form irregularities on the surface of the polycrystalline silicon.

FIGS. 5A to 5E are process charts.

First, in the same manner as in the first embodiment,
After the formation of the resist pattern 8, a resist pattern 8 having horizontal stripes of standing waves is formed on the side surface. Before this, the gate electrode 5 and the side walls are covered with a silicon nitride film or the like, and a storage node contact with the gate electrode is formed. The present invention is characterized in that there is no need to provide a margin for matching the bit line contact with the gate electrode, and irregularities are formed on the surface of the polycrystalline silicon film as the storage node electrode 10.

First, a silicon oxide film to be a gate insulating film 4 is formed on a p-type silicon substrate 1 and a gate electrode 5 is formed.
After forming a polycrystalline silicon film to be formed and a silicon nitride film 5s to be an insulating film on the gate, these are patterned,
A source / drain region composed of n-type diffusion layers 6a and 6b is formed, and a MOSF as a switching transistor is formed.
Form ET. The surface is further lightly oxidized to form a silicon oxide film 7a. Further, as in the first embodiment, the silicon nitride film 7s is used as an etching stopper for etching the LPD film for transferring the horizontal stripe pattern of the resist.
Is deposited.

Thereafter, a resist is applied, and exposure is performed by photolithography using a mask. A monochromatic light such as an excimer laser is used as a light source for this exposure, and the incident light to the photoresist and the reflected light from the base interfere with each other to generate a standing wave in the resist. The side is made to have horizontal stripes as shown in FIG. 5 (a). Then, the LPD film 9 is deposited.

When the resist is removed, horizontal stripe-shaped undulations are transferred to the side surface of the LPD film as the pattern transfer film. Thereafter, the thin silicon nitride and silicon oxide below the resist pattern are etched by RIE to form a storage node contact 8, and a storage node electrode is formed in the contact.

Then, as shown in FIG. 5B, for example, a polycrystalline silicon film is
After depositing 400 nm and doping this with arsenic or phosphorus, patterning is performed by photolithography and reactive ion etching to form a storage node electrode 10. At this time, the deposition temperature of the polycrystalline silicon film is set to 55
By lowering the temperature to about 0 ° C., irregularities are formed on the surface of the storage node electrode (M. Sakao et al., IEDM).
Tech. Dig. , P. 655 IEDM199
0).

Further, the LPD film 9 is etched away by etching using ammonium fluoride. At this time, the silicon nitride film 7s is used as an etching stopper.

After the LPD film 9 is removed by etching in this manner, a silicon nitride film is deposited on the entire surface by LPCVD to a thickness of about 10 nm and oxidized in a water vapor atmosphere at 950 ° C. for about 30 minutes to form a capacitor insulating film 11. . Thereafter, a polycrystalline silicon film is deposited on the entire surface, and this is doped with arsenic or phosphorus, and then a plate electrode 12 is formed by photolithography and dry etching. Then, a silicon oxide film 16 for protection is formed on the surface of the plate electrode by surface oxidation (FIG. 5C).

Thereafter, as in the first embodiment, a BPSG film 13S is deposited on the entire surface as an interlayer insulating film, and a bit line contact is formed by photolithography and reactive ion etching. By using the polycrystalline silicon film 17 as an etching stopper when forming this bit line contact, it is possible to prevent the bit line contact from shorting with the gate or plate electrode.

Further, the polycrystalline silicon film 17 is etched using the underlying silicon nitride film 7s as a stopper,
The remaining polycrystalline silicon film 17 is oxidized into a silicon oxide film 20 by thermal oxidation to firmly protect the plate electrode. This heat treatment melts the BPSG film and rounds the corners. Then, the contact is formed by removing the silicon oxide film and the silicon nitride film.

Then, bit lines such as an aluminum film and molybdenum polycide are formed, and the DRAM is completed.

In this method, a decrease in the capacitance of the capacitor can be prevented, and further miniaturization can be achieved.

In the first and second embodiments, the undulation of the side wall of the resist pattern formed by the standing wave is once determined by LPD.
This LP is transferred to a film to form a storage node electrode.
Although the capacitor insulating film is formed after removing the D film, when the capacitor area is sufficient, the LPD film may be used as it is as the insulating film. Also, it is possible to obtain a storage node electrode having horizontal stripe-shaped undulations directly by filling the electrode material directly into the grooves without using a medium for transferring the undulations of the resist pattern side wall formed by the standing wave. is there. In this case, a groove may be formed in which both side walls are surrounded by cylindrical walls having horizontal stripes, and a conductor film may be formed in the groove by the LPD method or the like.

Embodiment 3 Next, a third embodiment of the present invention will be described.

In this method, the transfer mask is melted at the same time as the oxidation of the polycrystalline silicon film used as the etching stopper, instead of using the standing wave, to form a rounded edge, and the curved surface of the arm is transferred to the surface of the storage node electrode. In addition, the present invention is characterized in that the area of the capacitor is increased.

FIGS. 6A to 6C are views showing a part of the manufacturing process. In the second embodiment, the surface and side surfaces of the gate electrode 5 are covered with silicon nitride films 5s and 7a.
After a silicon oxide film 7b and a silicon nitride film 7s are formed on the surface, a polycrystalline silicon film 21 is formed as an etching stopper, and a BPSG film 23 is formed thereon, and a storage node is formed as shown in FIG. The contact 8 is formed.

After the polycrystalline silicon film 21 in the contact 8 is removed by etching, the polysilicon film 21 is removed in a water vapor atmosphere.
A heat treatment of 0 to 900 ° C. is performed to oxidize the polycrystalline silicon film 21 serving as an etching stopper and to form a silicon oxide film 20.
And the gate electrode is firmly insulated and protected. This heat treatment melts the BPSG film and rounds the corners. Then, the silicon oxide film and the silicon nitride film are removed to form a contact.

The BPSG film 2 thus curved in a round shape
If the storage node electrode 10 is formed on the surface of FIG.
As shown in (b), the curved shape is transferred to the storage node electrode.

Then, as shown in FIG. 6C, after the BPSG film 23 is removed by etching, a silicon nitride film is deposited on the entire surface by LPCVD to a thickness of about 10 nm and oxidized in a water vapor atmosphere at 950 ° C. for about 30 minutes. The capacitor insulating film 11 is formed. Thereafter, a polycrystalline silicon film is deposited on the entire surface, and this is doped with arsenic or phosphorus, and then a plate electrode 12 is formed by photolithography and dry etching. Then, a silicon oxide film 16 for protection is formed on the surface of the plate electrode by surface oxidation.

Thereafter, as in the second embodiment, an interlayer insulating film is deposited on the entire surface, and a bit line contact is formed by photolithography and reactive ion etching.

Then, bit lines such as an aluminum film and molybdenum polycide are formed, and the DRAM is completed.

In the case of the DRAM formed in this manner, the surface area of the storage node electrode can be increased, and the capacitance of the capacitor can be increased.

Embodiment 4 Next, a fourth embodiment of the present invention will be described.

In this method, the bending direction of the storage node electrode is reversed from that of the third embodiment. Similar to the third embodiment, the transfer mask is melted to form a rounded edge, and the curved surface of the arm is transferred to the surface of the storage node electrode. In addition, the present invention is characterized in that the area of the capacitor is increased.

FIGS. 7A to 7C show a part of the manufacturing process. In the third embodiment, the surface and side surfaces of the gate electrode 5 are covered with silicon nitride films 5s and 7a. Silicon oxide film 7b and silicon nitride film 7
Although s was formed, here, the silicon nitride film covering the gate electrode side wall is used as it is instead of the thin silicon nitride film. Then, the silicon nitride film 27 is patterned to form a storage node contact. Then, after depositing a first polycrystalline silicon film 10a below the storage node electrode, a BPSG film 33 is deposited.
Is patterned using the polycrystalline silicon film 10a of FIG.
The SG film 33 is left (FIG. 7A).
As shown in (b), a second polycrystalline silicon film 10b to be on the storage node electrode is deposited.

Then, as shown in FIG. 7C, the flat portion of the polycrystalline silicon film 10 is removed by reactive ion etching on the entire surface, and the BPSG film 33 is etched to obtain a curved storage node electrode 10. And Example 3
Similarly, the capacitor insulating film 11 and the plate electrode 12
Is formed to form a capacitor. Reference numeral 16 denotes a silicon oxide film for protecting a plate electrode.

The rest is formed in the same manner as in Examples 2 and 3,
The DRAM is completed.

Embodiment 5 Next, a fifth embodiment of the present invention will be described.

FIGS. 8A to 8C are a part of the process chart.

In this example, the transfer mask of the storage node electrode is used as the BPSG film 37a and the CVD silicon oxide film 37.
The storage node electrode 40 is formed in a fin shape by forming a multilayer structure in which b and b are alternately stacked, etching under conditions where the etching rates are different from each other, and forming irregularities on the side walls.

In this method, as in the third embodiment, the surfaces and side surfaces of gate electrode 5 are covered with silicon nitride films 5s and 7a.
After forming a silicon oxide film 7b and a silicon nitride film 7s on the surface, a polycrystalline silicon film 21 is formed as an etching stopper, and a BPSG film 37a and a CVD silicon oxide film 37b are alternately formed on the polysilicon film 21. The storage node contact region is formed with a multilayer having a multilayer structure in which the layers are laminated one by one, and wet etching is performed under the condition that the etching rates are different from each other to form a hole having unevenness on the side wall (FIG. 8A). Alternatively, after a contact hole is opened by RIE using the polycrystalline silicon film as a stopper, etching may be performed in a lateral direction by wet etching.

After the polysilicon film 21 in the contact 8 is removed by etching, a polysilicon film 10 as a storage node electrode is formed (FIG. 8B).
).

Thereafter, similarly, BPSG films 37a and C
After the VD silicon oxide film 37b is removed by etching, LP
A capacitor insulating film 11 is formed by depositing a silicon nitride film to a thickness of about 10 nm on the entire surface by a CVD method and oxidizing the film in a steam atmosphere at 950 ° C. for about 30 minutes. Thereafter, a polycrystalline silicon film is deposited on the entire surface, and this is doped with arsenic or phosphorus, and then a plate electrode 12 is formed by photolithography and dry etching. Then, a silicon oxide film 1 for protection is formed on the surface of the plate electrode by surface oxidation.
6 is formed.

In this manner, a storage node electrode having a single-layer structure and a fin shape can be easily formed.

In the above embodiment, when forming the mask for transferring the storage node electrode, a multilayer structure film in which two layers of the BPSG film 37a and the CVD silicon oxide film 37b are alternately laminated is used. If it is a laminated body of the above film, it can be appropriately changed.

[0077]

As described above, according to the semiconductor memory device of the present invention, it is easy to manufacture, and a sufficient capacitor capacity can be secured even when the occupied area of the memory cell is further reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a DRAM having a stacked memory cell structure according to a first embodiment of the present invention;

FIG. 2 is a manufacturing process diagram of the DRAM.

FIG. 3 is a diagram showing the principle of generation of a standing wave.

FIG. 4 is a diagram showing a modification of the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the DRAM according to the second embodiment of the present invention;

FIG. 6 is a manufacturing process diagram of a DRAM according to a third embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of a DRAM according to a fourth embodiment of the present invention.

FIG. 8 is a manufacturing process diagram of a DRAM according to a fifth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 p-type silicon substrate 2 element isolation insulating film 3 channel stopper 4 gate insulating film 5 gate electrode 6 source / drain region 7 insulating film 7 s silicon nitride film 8 storage node contact 10 storage node electrode 11 capacitor insulation Film 12 plate electrode electrode 14 bit line

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (1)

(57) [Claims] A step of forming a MOSFET in a semiconductor substrate; a step of forming an insulating film covering an upper part and a side wall of a gate electrode of the MOSFET with an insulating film; and forming a first film on the insulating film. A first film forming step of selectively removing a part of the first film to determine a storage node contact region; and heating the first film, A heating step of melting the first film and rounding an edge; a storage node electrode forming step of forming a storage node electrode so as to cover the storage node contact region and reach an upper edge of the first film; Forming a capacitor insulating film around the storage node electrode; and forming a plate electrode on the capacitor insulating film. A semiconductor, comprising: a plate electrode forming step of forming; an interlayer insulating film forming step of forming an interlayer insulating film; and a bit line forming step of forming a bit line contact and forming a bit line in the interlayer insulating film. A method for manufacturing a storage device.