JP2891358B2 - Non-volatile storage integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory integrated circuit that uses an electrically rewritable semiconductor nonvolatile memory element and has a short rewrite time and good storage characteristics.

[Conventional technology and its problems]

MNOS (Metal-Nitride-Oxide-Sem) as an electrically rewritable semiconductor nonvolatile memory element having an insulated gate field effect transistor structure (hereinafter referred to as a memory element)
iconductor) type memory device and the second type of MNOS type memory device
MONOS (Metal-Oxide-Nitri), a silicon oxide film formed by thermally oxidizing the surface of a silicon nitride film
de-Oxide-Semiconductor) type memory elements. this
Since the MONOS type memory device has a silicon oxide film with a barrier height sufficient to prevent carrier injection from the gate insulating side as the third layer gate insulating film, the total thickness of the gate insulating film is reduced to 10 nm or less. It has a feature that it can be made thinner and can be rewritten at 10 V or less. In the MNOS type, traps in the silicon nitride film (hereinafter referred to as traps) are used for trapping carriers, whereas in the MONOS type, traps at the interface between different insulating films are further used for trapping carriers. Then, by injecting charges into the trap, the threshold voltage Vth of the memory element is varied. Information is stored.

The memory retention and the rewriting speed mainly depend on the thickness of a first-layer gate insulating film formed on a semiconductor substrate called a tunnel insulating film, and their characteristics are contradictory. That is, when the thickness of the tunnel insulating film is increased, the memory retention is improved, but the rewriting speed is reduced. When the thickness of the tunnel insulating film is reduced, the reverse tendency is obtained. Therefore, there is a limit to long-term memory retention and high-speed rewriting. In the MONOS type memory device (Japanese Patent Application Laid-Open No. 62-14474) proposed by the present applicants and using a silicon nitride film having a composition excessively silicon as the second layer gate insulating film, the memory retention is improved. However, it was not sufficient, and no response was made to the rewriting speed. Similarly, the composition of the silicon nitride film, which is the second-layer gate insulating film proposed by the present applicant, is made excessive in the silicon near the center of the film thickness, and the composition near the interface with the tunnel insulating film, which is the first-layer gate insulating film. MONOS type memory device having a composition close to the stoichiometric value in
No. 62), the rewriting speed was considerably improved, but it still required about 10 milliseconds for erasing, and a higher speed was desired. Further, in this method, it is difficult to control a silicon nitride film, and the method is not sufficiently compatible with mass productivity.

The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a nonvolatile memory integrated circuit in which a rewriting speed and a memory retention characteristic are significantly improved.

[Means for solving the problem]

The present invention is a non-volatile storage integrated circuit including a semiconductor non-volatile storage element, a detection circuit, and a reference signal generation element, and has the following configuration to achieve the above object.

The semiconductor non-volatile memory element includes a source / drain region of a conductivity type opposite to the semiconductor region provided in the semiconductor region of the first conductivity type, and a first gate insulating film on a surface of a channel region between the source / drain regions. An insulating film layer in which a charge-injectable tunnel insulating film as a film, a silicon nitride film as a second gate insulating film, and a silicon oxide film as a third gate insulating film are sequentially stacked; and a conductive film provided on the insulating film layer. The impurity concentration and the type of the impurity in the channel region are configured such that the threshold voltage at the time of completion of the semiconductor non-volatile memory element is of a depletion type. A threshold voltage which is on the enhancement side of the threshold voltage at the time of completion or on the depletion side of the threshold voltage. This is a conductive nonvolatile storage element.

The detection circuit is a circuit that detects information by comparing a reference signal supplied from the reference signal generation element with an output current from the semiconductor non-volatile storage element or a signal generated using the output current. The reference signal generating element has the same configuration as the semiconductor non-volatile memory element and is a non-volatile memory element in which writing is not performed, and has a gate electrode set to the ground potential.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a sectional structure of a semiconductor nonvolatile memory element used in a nonvolatile memory integrated circuit of the present invention, and is an embodiment in which a P-type silicon substrate 11 is used as a semiconductor region.
For example, a low concentration of n-type impurities such as phosphorus is implanted into the silicon substrate 11 by ion implantation, and a P-type or slightly n-type channel dope layer 13 having a lower concentration than the silicon substrate 11 is formed near the surface of the silicon substrate 11. Form. Further, a tunnel insulating film 14 as a first gate insulating film and a silicon nitride film as a second gate insulating film are formed on the surface of the silicon substrate 11.
15, a silicon oxide film 16 obtained by thermally oxidizing the silicon nitride film as a third gate insulating film, and a polycrystalline silicon film 17 as a conductive gate electrode are laminated in this order, and are etched using a known photoetching technique. After the gate of the device is formed, an n-type impurity such as arsenic or phosphorus is implanted by an ion implantation technique to form a source / drain region 12. In this example, a silicon nitride film having a composition excessively high in silicon and having a thickness of about 14 nm was used as the second-layer gate insulating film of the memory element. The impurity concentration and the type of impurity in the channel region of the memory, which is the semiconductor nonvolatile memory element, are configured such that AsVth, which is the threshold voltage at the time of completion of the memory element, is a depletion type. In this embodiment, the memory element As
As a method of depleting Vth, a method of forming a channel dope layer 13 using so-called channel doping is used. The reason will be described.

Generally, when memory elements are integrated in an array, it is necessary to add an address selection transistor to each of the memory elements in order to prevent a malfunction. Usually, an address selection transistor is a MOS (Metal-Oxide-Semiconductor) field effect transistor. Yes, they share the same semiconductor substrate as the memory element. In order for the address selection transistor to have a function of preventing malfunction, it is necessary that the transistor is an enhancement type transistor, so that the semiconductor substrate concentration must be increased to some extent. As a result, the AsVth
Are often of the enhanced type. Therefore, by performing channel doping after forming the gate of the address selection transistor, only the AsVth of the memory element among the address selection transistor and the memory element in the same semiconductor substrate can be depleted.

An example of this manufacturing method will be described with reference to FIG. Second
As shown in FIG. 1A, a surface of a P-type silicon substrate 11 is oxidized to form a silicon dioxide film 19 having a thickness of about 35 nm, and further, is formed by a chemical vapor deposition method (hereinafter referred to as a CVD method). After forming a polysilicon film 18 having a thickness of about 450 nm, the polysilicon film 18 is formed by a known photo-etching technique.
The gate of the address selection transistor is formed by etching 18, and an n-type impurity such as phosphorus is implanted in the vicinity of the surface of the silicon substrate 11 by using a polysilicon film 18 as a mask by a well-known ion implantation technique.
Then, the silicon dioxide film 19 is etched using the polysilicon film 18 as a mask.

Next, as shown in FIG.
A tunnel insulating film 14 having a thickness of about 1 nm is formed, a silicon nitride film 15 having a thickness of about 14 nm is formed by CVD, and a silicon oxide film 16 having a thickness of about 5 nm is formed by subjecting the surface of the silicon nitride film 15 to steam oxidation treatment. Is formed, and a film thickness of 4
A polycrystalline silicon film 17 of about 50 nm is formed. The channel dope layer is heated by the high temperature during the steam oxidation process during this time.
13 diffuses into the silicon substrate 11.

Next, as shown in FIG. 2 (c), the polycrystalline silicon film 17, the silicon oxide film 16,
The silicon nitride film 15 and the tunnel insulating film 14 are sequentially etched to form a gate of the memory element, and an n-type impurity such as arsenic or phosphorus is added to the polycrystalline silicon film 17 and the polysilicon film 18 by a known ion implantation technique. A high concentration source / drain region 12 is formed by implanting into the silicon substrate 11 as a mask and performing a heat treatment in, for example, a nitrogen atmosphere. At this time, the channel dope layer 13 other than under the gate of the memory element is converted into the source / drain region by the high concentration impurity layer.

Next, as shown in FIG. 2D, an interlayer insulating film 20 is formed, and a contact window 22 is formed by photoetching to form a wiring metal 21 such as aluminum. At this time, in the source / drain region 12, the source / drain region sandwiched between the address selection transistor and the memory element does not need to be provided with wiring, and may be in an electrically floating state. In this way, the effective impurity concentration of the semiconductor region under the gate of the memory element of the address selecting transistor and the memory element formed in the same silicon substrate 11 is compensated by channel doping to reduce the concentration, or By using the type, only AsVth of the memory element can be depleted. Needless to say, the impurity surface concentration of the silicon substrate 11 is configured such that Vth of the address selection transistor is enhanced.

In the above embodiment, the semiconductor region is the silicon substrate itself, but the semiconductor region may be an island-shaped semiconductor region formed on a well of the opposite conductivity type to the substrate formed on the surface portion of the silicon substrate or on an insulating substrate. I can't do anything.
Of course, even if channel doping is not performed,
It is possible to deplete only AsVth, for example, a method of increasing the gate oxide film thickness of an address selection MOS transistor so that Vth is enhanced even at a semiconductor substrate concentration at which AsVth of a memory element is depleted, A method in which the Vth of the address selection MOS transistor is enhanced and the AsVth of the memory element is depleted using the work function difference between the gate and the substrate depending on the material selection (for example, the memory element is an n ⁺ silicon gate in a P-type silicon substrate). And the address selection transistor is a p ⁺ type silicon gate), but this is not practical because of the drawbacks such as the inability to cope with miniaturization of element dimensions and the complicated process. The above is the reason for performing channel doping in the present invention.

Next, a description will be given of how the memory retention is improved by depletion of the memory element with reference to FIG. FIG. 3 is a diagram comparing the memory retention of the memory device having the structure according to the present invention shown in FIG. 1 with the conventional memory device without channel doping. Here, as a conventional memory element, a silicon nitride film having a uniform silicon excess composition having a thickness of about 14 nm is used for the second layer gate insulating film,
The layer gate insulating film is a tunnel insulating film having a thickness of 2.1 nm.
The memory device using a silicon oxide film formed by thermally oxidizing a silicon nitride film as a second layer gate insulating film having a thickness of about 5 nm is referred to as a layer silicon insulating film. The memory device of the present invention has an AsVth of about −1.0 V, and the memory device of the prior art has an AsVth of approximately −1.0 V.
Is about 0.1 V, in both the present invention 31 and the conventional example 32, the write Vth and the erase Vth
The initial values of are obtained by examining the memory retention with the same value. That is, as can be seen from FIG. 3, the initial value of the write Vh of the memory element of the present invention is AsVth (about -1.0 V).
On the enhancement side (upper side in the figure), the initial value of the erase Vh is further on the depletion side (lower side in the figure) than AsVth. The dashed line in FIG. 3 is the expected line, and the Vth at the intersection of the Vth decay curve is about -0.5 V in the present invention and about 0.2 V in the conventional example, which is almost the same as the relationship of AsVth of the memory element. The stored information (Normally on) (Normally off) is determined by the Vth of the memory element
Is determined on the enhancement side or the depletion side of a reference called a sense level, and the sense level is usually slightly lower than zero V at Vth, and is often around -0.5 V. The absolute lifetime of the memory retention is the time to the intersection of the Vth decay curves, but the substantial lifetime is the time until the Vth decay curves cross the sense level. In FIG. 3, the time required for the Vth attenuation local line on the erase side of the present invention to cross the sense level is considerably longer than that of the conventional example, and the absolute memory retention life and the substantial memory retention life are almost equal. Are equal. That is, the depletion of AsVth of the memory element can substantially improve the storage retention.

FIG. 4 shows hysteresis curves of a memory device according to the present invention and a conventional memory device without channel doping. There is not much difference on the writing side,
On the erase side, the hysteresis curve of the present invention is large. This is because the degree to which the charge induced on the substrate surface under the memory gate by the charge injected into the memory element affects the effective substrate concentration is large when the original substrate concentration is low,
This is because it appears remarkably on the erase side. As can be seen from FIG. 4, in the memory element according to the present invention indicated by the solid line 41, the Vth change during erasing is large, and the Vth change per unit time during the erasing operation is large. In comparison with the above, the time required for setting the same Vth after erasing can be reduced. This means that the erasing speed is increased. For example, when the erasing voltage is -9V, the erasing time of the conventional memory device is 10 to 50 msec, and the erasing time of the memory device of the present invention is about 5 msec, so that the erasing speed can be greatly increased. Here, the erasing time is a time required to lower the threshold voltage of the memory element from a sufficiently written state to a sense level or less.

Although the n-channel type has been described in the above embodiment, an n-type silicon substrate may be used and a p-type impurity such as boron may be used as an impurity for channel doping in order to obtain a p-channel type.

Next, an embodiment of a nonvolatile memory integration circuit using a memory element whose AsVth is depletion according to the present invention will be described with reference to FIGS. 5 and 6. FIG.

FIG. 5 is a schematic diagram of a nonvolatile memory integrated circuit including a memory matrix including memory cells 54, 55, 56, and 57, a detection circuit 43, and a reference signal generating element 48, and constitutes a memory cell 57. The information that the storage transistor 53 has Or This is a diagram illustrating a system for detecting whether or not the image is detected. In FIG. 5, the element marked with M is a memory element according to the present invention in which AsVth is depleted, and the element marked with n is an n-channel MOS transistor. Reference signal generator 48
Is a memory element according to the present invention in which writing is not performed at all and the threshold value is always maintained at AsVth.
3, 58, 59 and 60 are memory elements according to the present invention in which writing is freely performed. In FIG. 5, a high-level potential and a selected word line 45 are connected to the gate of the transistor 51 for selecting an address in the Y direction.
A high-level potential is applied to the non-selected word line 46, a low-level potential is also applied to the blocking line 62, a low-level potential is applied to the write line 44, and a low-level potential is applied to the gate of the reference signal generating element 48. A low level (fixed earth potential) is applied, and a high level potential is applied to the gate of the load transistor 49. Here, the load transistor 49 is composed of the Y-direction address selection transistor 51 and X
This is equivalent to combining the direction selection transistor 50.
Therefore, the magnitude of the current level at points A and B or the potential level determined by the current level is determined by the difference between the threshold voltage of the storage transistor 53 and the threshold voltage of the reference signal generating element 48. Since the value is always a constant value of depletion, the memory transistor 53
The current level at points A and B or the magnitude relationship between the potential levels determined by this current level is determined depending on whether the threshold value is more enhanced or depleted than the threshold value of reference signal generating element 48. Then, the detection circuit 43 determines the current level at the points A and B or the magnitude relationship between the potential levels determined by the current level, and if necessary, amplifies the determination result to generate an output 52. Information can be read.

As shown in FIG. In the detection system, the reason that the information of the storage transistor 53 cannot be read correctly is that the electric charge accumulated in the storage transistor 53 gradually disappears with time, and the threshold voltage of the storage transistor 53 becomes This is when the threshold voltage of the reference signal generating element 48 becomes equal to AsVth. The time required for the threshold voltage of the storage transistor 53 to become equal to AsVth due to aging is the intersection of the decay curves of the write-side Vth and the erase-side Vth, that is, the absolute storage retention life. Therefore, a memory element whose AsVth is depletion according to the present invention is used as a reference signal generation element and a storage transistor, and a detection circuit uses a current level based on a difference between threshold voltages of the storage transistor and the reference signal generation element or a current level based on the current level. A nonvolatile memory integrated circuit using a system for detecting a determined potential level can make the storage time equal to the absolute storage life of the storage transistor, and can have the maximum storage time. In the information detection system as shown in FIG. 5, the storage transistor 53 and the reference signal generation element 48 are composed of the same type of memory element, and the storage transistor 53 and the reference signal generation element 48 are compared. Therefore, it is characterized in that it is not affected by variations at the time of manufacturing and changes in temperature.

FIG. 6 shows a case where the memory element according to the present invention shown in FIG. 5 in which AsVth is depleted is used for the storage transistor and the reference signal generation element, and the reference signal supplied from the reference signal generation element and the output current from the storage transistor. Alternatively, in a nonvolatile memory integrated circuit including a detection circuit having a function of detecting information by comparing a signal generated using an output current, a current mirror type differential amplifier is used as the detection circuit. . The element marked P in FIG. 6 is a P-channel MOS transistor. Sixth
The non-volatile memory integrated circuit shown in the figure detects information by comparing potentials at points C and D and generates an output. In FIG. 6, when a high-level potential is applied to the gates of the X-direction address selection transistor 50, the Y-direction address selection transistor 51, and the load transistor 49 to make them conductive, the threshold voltage of the reference signal generating element 48 Is always As
Since it is Vth, the potential at point D is always constant. on the other hand,
The potential at the point C varies depending on whether the threshold voltage of the storage transistor 53 is enhanced or depleted, and the threshold voltage of the reference signal generating element 48, ie, AsVt
When the threshold voltage of the storage transistor 53 is more than h, the potential at the point C becomes lower than the potential at the point D, and the threshold voltage of the storage transistor 53 becomes AsVth.
In the case of enhancement, the potential at the point C becomes higher than the potential at the point D. The detection circuit 61 amplifies and outputs the difference between the potentials at the points C and D. The output value is high when the potential at the point C is lower than the point D, and the potential at the point C is higher than the potential at the point D. When high, outputs low level.

The storage retention time of the nonvolatile storage integrated circuit shown in FIG. 6 is equal to the absolute storage retention life of the storage transistor 53 in the same manner as the storage retention time of the nonvolatile storage integrated circuit shown in FIG. Needless to say, it is not affected by variation in time or temperature change during use.

〔The invention's effect〕

As described above, according to the present invention, the storage retention of the semiconductor nonvolatile memory element can be substantially improved as compared with the related art, and the erasing speed can be increased. By using the same nonvolatile semiconductor memory element as the memory element and the reference signal generating element, the storage retention time is equal to the absolute storage retention life of the memory element. A nonvolatile storage integrated circuit which is not affected by the change can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor nonvolatile memory element used in the present invention. 2 (a) to 2 (d) are cross-sectional views showing manufacturing steps in the case where the semiconductor nonvolatile memory element used in the present invention is manufactured on the same substrate as the address selecting transistor. FIG. 3 is a diagram showing a comparison of storage retention characteristics between a semiconductor nonvolatile memory element used in the present invention and a conventional semiconductor nonvolatile memory element without channel doping. FIG. 4 is a diagram showing a comparison between hysteresis curves of a semiconductor nonvolatile memory element used in the present invention and a conventional semiconductor nonvolatile memory element. FIG. 5 is a circuit diagram showing one embodiment of the nonvolatile memory integrated circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the nonvolatile memory integrated circuit according to the present invention. 12 source / drain regions, 13 channel doped layers, 14 tunnel insulating films, 15 silicon nitride films, 16 silicon oxide films, 17 polycrystalline silicon films, 48 reference signal generation Element, 49: Transistor for load, 50: Transistor for selecting address in X direction, 51: Transistor for selecting address in Y direction, 61: Detection circuit.

Continued on the front page (72) Tatsuo Tsuchiya, Inventor Tatsuo Tachio, Tokorozawa-shi, Saitama 840 Shimotomi Takeno Technical Research Institute (72) Inventor Koshiro Kinsutani Koshiro, Tokorozawa-shi, Saitama 840 Shichitomi, Takeno-shi Takeshi Asahi Masayama, Examiner, Dune Watch Co., Ltd. Technical Research Institute (56) References JP-A-59-58868 (JP, A) JP-A-62-14474 (JP, A) JP-A-59-99760 (JP, A) JP-A-57-135495 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/792 H01L 21/8247 H01L 27/115

Claims (1)

(57) [Claims] 1. A nonvolatile memory integrated circuit comprising a semiconductor nonvolatile memory element, a detection circuit, and a reference signal generating element, wherein the semiconductor nonvolatile memory element is provided in a semiconductor region of a first conductivity type. A source / drain region of the opposite conductivity type to the semiconductor region; a tunnel insulating film capable of injecting a charge as a first gate insulating film on a surface of a channel region between the source / drain region; and a nitride film as a second gate insulating film Silicon membrane,
An insulating film layer in which a silicon oxide film is sequentially stacked as a third gate insulating film; and a conductive gate electrode provided on the insulating film layer.
The semiconductor non-volatile memory element is configured so that the threshold voltage at the time of completion is of a depression type, and the threshold voltage at the time of completion or enhancement is higher than the threshold voltage at the time of completion at the time of writing or erasing of information. A semiconductor non-volatile storage element configured to be more depleted than a threshold voltage, wherein the detection circuit includes a reference signal supplied from the reference signal generation element and an output current from the semiconductor non-volatile storage element or A circuit for detecting information by comparing a signal generated using an output current, wherein the reference signal generating element has the same configuration as the semiconductor non-volatile memory element, and is a non-volatile memory element in which writing is not performed. Wherein the gate electrode is set to the ground potential.