JPH06334192A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To enhance multi-values of accumulated electric charges by installing a floating gate electrode whose thickness is different from that of an insulation film to the upper part of a pair of high-doped region over a range thinner than an insulation film in the upper part of a semiconductor substrate between high dopants in paired vertically laminated structure. CONSTITUTION:A high doped region or an insulation film in the upper part of a source 24 and a drain 25 is etched in such a fashion that it may become a thermal oxide film whose specific thickness is extremely thin. Then, after having formed a thin floating gate layer, a thin floating gate electrode 17 is formed on a side wall of a control gate electrode 14. Then, a thin thermal oxide film 16 is formed on the whole surfaces and the thin thermal oxide film 16 in the upper parts of the source 24 and the drain 25 is etched so that its thickness may be thinner than that of the gate oxidation film as a result. Then, after having formed a thick floating gate layer, a thick floating gate electrode 18 is formed on the side wall of the control gate electrode 14. This construction makes it possible to attain enhanced multi-values of a semiconductor memory.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a non-volatile semiconductor memory.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 5 (a sectional view in a direction orthogonal to the channel width), a sidewall storage type nonvolatile semiconductor memory has a thin gate oxide film on a source 40 and a drain 41 above a P-type silicon substrate 42. Floating gate electrode 38 is formed via 39, source 40 and drain 4
The control electrode 37 is formed between the two via the P-type silicon substrate 42 and the gate oxide film 39. (Patent application No. 4-264518)

[0003]

The conventional side wall storage type non-volatile semiconductor memory is formed for the purpose of writing, reading and erasing to the floating gate electrode 38 above the source / drain. There is no attempt to make the memory cell multi-valued by utilizing the difference in thickness. When multi-valued write injection amount into the nonvolatile semiconductor memory is attempted by utilizing the sidewall storage type structure, the injected charge is changed by changing the voltage of the control electrode 37 above the gate oxide film 39. It is possible to do so. In order to control this write injection amount, it is necessary to greatly change the voltage applied from the control electrode 37. However, when the gate oxide film 39 is thinned, a slight change in the voltage applied from the control electrode 37 causes a large variation in the write injection amount, and there is a limit to the control by only the injection amount voltage. Therefore, in the conventional sidewall storage type non-volatile semiconductor memory, there is a problem in that it is not accurate to achieve a multi-valued write injection amount due to a change in the voltage applied from the control electrode 37.

The present invention provides a non-volatile semiconductor memory capable of solving the above problems.

[0005]

According to the present invention, a pair of high-concentration impurity regions of a second conductivity type formed in a semiconductor substrate of a first conductivity type, that is, a source and a drain, and a source and a drain,
A thin floating gate electrode is provided above the drain via a pair of extremely thin insulating films, and a thick floating gate electrode is provided above the thin floating gate electrode via a pair of thin insulating films. Further sauce,
A non-volatile semiconductor memory in which a control electrode is formed between drains via the extremely thin insulating film and an insulating film thicker than the thin insulating film, wherein a source and a drain having an extremely thin insulating film are connected to the control electrode. By applying a voltage of about 10V, the source and drain are made extremely thin to allow tunneling current to flow, and the source and drain having a thin insulating film above the thin floating gate electrode are applied by applying a voltage of about 15V from the control electrode. It is formed thin enough to allow the tunnel current from the drain to flow.

The thicknesses of the extremely thin insulating film and the thin insulating film are preferably about 10 nm and 15 nm, respectively.
At least by applying a voltage of about 10 V to the control electrode,
The thickness is set so that the tunnel current flows from the source / drain to the thin floating gate electrode. Further, by applying a voltage of about 15 V to the control electrode, the thickness is set so that the tunnel current flows from both the source and the drain to the floating gate electrode through the thin insulating film. Further, the thickness of the gate insulating film is set to a thickness at which channel electrons flow from the source to the drain by applying a voltage to the control electrode and the drain, for example, about 20 nm.

[0007]

In the nonvolatile semiconductor memory of the present invention, it is extremely possible that a tunnel current flows through the pair of high-concentration impurity regions through the insulating film and the thin floating gate electrode above the thin insulating film due to voltages having different critical points. Since the electrodes are thin and have different thicknesses, 10
At the time of writing applying a voltage of about V, charges are injected from the source and drain of this high-concentration impurity region into the thin floating gate electrode, and at the time of writing applying a voltage of about 15 V, both of these high-concentration impurity regions, that is, the source and drain. Charge is injected from the drain into both the thin floating gate electrode and the thick floating gate electrode. Further, since the oxide film is formed thick between the pair of high-concentration impurity regions so that at least the channel current flows, the data is written in the floating gate electrode at the time of reading by applying a voltage of 5V to the control electrode and 1V to the drain. The necessary and sufficient channel current flows from the source to the drain while holding the stored charge.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A non-volatile memory cell according to an embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1 (A) (B) (C) (D) are an example of a method for manufacturing a non-volatile semiconductor memory according to an embodiment of the present invention, and FIGS. 2 (A) (B) (C) (D).
(E) shows the operation of the semiconductor memory from the relationship between the control of the electrodes and the charge at the time of writing, reading and erasing the nonvolatile semiconductor memory. FIG. 3 is a channel current characteristic diagram at the time of reading of the nonvolatile memory cell in the example of the present invention. FIG. 4 shows the relationship between changes in the applied voltage from the control electrode during writing and changes in the injected charge at that time in the nonvolatile semiconductor memory according to the example of the present invention.

1 (A) (B) (C) (D), FIG. 2 (A) (B) (C) (D) (E)
1 is a non-volatile semiconductor memory, 11 is a P-type silicon substrate, 12 is a thick thermal oxide film, 14 is a control gate electrode, 15 is an extremely thin thermal oxide film, 16 is a thin thermal oxide film, 17 is a thin floating gate electrode, 18 is a thick floating gate electrode, 19 is an interlayer film, 20S is a source electrode, 20D is a drain electrode, 24 is a source, 25
Is a drain, 28 and 33 are channels, 29 is a small amount of electrons, 30 is a large amount of electrons, 31 is a small parasitic resistance, and 32 is a large parasitic resistance.

An embodiment of the present invention will be described together with a manufacturing method example. First, a method of manufacturing this nonvolatile semiconductor memory will be described with reference to FIG. First, as shown in Fig. 1 (A),
After forming a gate oxide film, that is, a thick thermal oxide film 12 on the entire surface of a conductive type, eg, P type silicon substrate 11, polysilicon is grown by a CVD method to form a control gate layer, and then a photoetching method is used. The control gate electrode 14 is etched into a predetermined pattern by using. Then, arsenic ions As + are implanted using the control gate electrode 14 as a mask to form a high concentration impurity region, that is, a source 24 and a drain 25.

Next, as shown in FIG. 1B, a thermal oxide film is formed on the entire surface, and the insulating film above the source 24 and the drain 25 is formed into an extremely thin thermal oxide film having a predetermined thickness by photolithography. 1
Etch to 5. Continuously CV polysilicon
The thin floating gate electrode 1 is formed on the side wall of the control gate electrode 14 by anisotropic etching after being grown by the D method to form a thin floating gate layer.
Form 7. Next, as shown in FIG. 1C, a thin thermal oxide film 16 is formed on the entire surface, and the source 24,
The thin thermal oxide film 16 above the drain 25 is etched, and as a result, formed to be thinner than the gate oxide film. Subsequently, polysilicon is grown by the CVD method to form a thick floating gate layer, and then a thick floating gate electrode 18 is formed on the sidewall of the control gate electrode 14 by anisotropic etching.

Next, as shown in FIG. 1D, an interlayer film 19, a source electrode 20S and a drain electrode 20D are formed to obtain the structure of the non-volatile memory cell 1 according to the present invention. Next, the operation of this nonvolatile semiconductor memory will be described with reference to FIG.

As shown in FIG. 2A, the control gate electrode 14 and the source 2 of the non-volatile semiconductor memory 1 (source and drain electrodes are not shown) obtained by the above manufacturing method.
When a voltage of, for example, about 10 volts, 0 volts, or 0 volts is applied to each of 4 and the drain 25, the source 24,
The energy barrier to electrons of the gate oxide film toward the control gate electrode 14 viewed from the drain 25, that is, the extremely thin thermal oxide film 15, is effectively lowered, and the thin floating gate electrode 17 and the source 24,
Electrons tunnel between the drains 25, and a small amount of electrons 29 are injected into the thin floating gate electrode 17 as shown in FIG.

Next, as shown in FIG. 2C, when a voltage of, for example, about 15 volts, 0 volts, or 0 volts is applied to the control gate electrode 14, the source 24, and the drain 25, the source 24 and the drain 25 see. The energy barrier to electrons of the gate oxide film in the direction of the control gate electrode 14, that is, the thin thermal oxide film 16 is effectively lowered, and the thin floating gate electrode 1
Electrons tunnel between the source 7 and the source 24, the drain 25, and the thick floating gate electrode 18 and the source 24 and the drain 25, respectively, and a small amount of electrons 29 and a large amount of electrons 30 are supplied to the thin floating gate electrode 17 and the thick floating gate electrode 18. Is injected, and binary information is written in the semiconductor memory.

Next, as shown in FIGS. 2B and 2C, the control gate electrode 14 of the non-volatile semiconductor memory 1 has, for example, 5
Channels 28 and 33 are formed by applying a voltage of about 1 volt to the volt and drain 24, respectively. As shown in FIG. 3, the channel current value is a small parasitic resistance of the drain 25 and the source 24 due to the small amount of electrons 29 and the large amount of electrons 30 injected into the thin floating gate electrode 17 and the thick floating gate electrode 18. 31, controlled by a large parasitic resistance 32,
Based on this value, the states of "2", "1" and "0" of the nonvolatile semiconductor memory 1 are read.

Next, as shown in FIG. 2 (E), when a voltage of about -15 V is applied to the control gate electrode 14 of the non-volatile memory cell 1, a small amount of electrons are emitted from the thin floating gate electrode 17 and the thick floating gate electrode 18. 29, a large amount of electrons 30 is the source 24
And emitted to the drain 25 by tunneling and erased from the semiconductor memory 1.

FIG. 4 shows the relationship between the voltage applied from the control gate electrode and the binary charge injected into the floating gate electrode.

[0019]

As described above, according to the present invention, an insulating film having a different thickness in a pair of vertically stacked structures is formed on a pair of high-concentration impurity regions in an area thinner than the insulating film on a high-concentration impurity semiconductor substrate. By providing the floating gate electrodes having different thicknesses, the semiconductor memory can be easily multi-valued. Further, at this time, electrical control for writing, reading and erasing of the nonvolatile semiconductor memory is extremely simplified, and injection and emission charges to the floating gate electrode can be controlled with high accuracy. Further, the tunnel current from the high concentration impurity region is not injected into the control electrode,
MOSFET characteristics do not deteriorate.

[Brief description of drawings]

FIG. 1 is a process chart showing a manufacturing method example of a nonvolatile semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing write, read, and erase operations of a nonvolatile semiconductor memory according to an embodiment of the present invention.

FIG. 3 is a drain current characteristic diagram during reading of the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 4 is a diagram showing the relationship between the applied voltage from the control electrode and the amount of injected charges during writing in the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view of a sidewall storage type nonvolatile semiconductor memory showing a conventional example.

[Explanation of symbols]

 1 Non-volatile semiconductor memory 11 P-type silicon substrate 12 Thick thermal oxide film 14 Control gate electrode 15 Extremely thin thermal oxide film 16 Thin thermal oxide film 17 Thin floating gate electrode 18 Thick floating gate electrode 19 Interlayer film

Claims (1)

[Claims] 1. A pair of high-concentration impurity regions of the second conductivity type are formed on a first conductivity type semiconductor substrate, and a thin floating gate electrode is provided above the impurity regions via a pair of extremely thin insulating films. A thick floating gate electrode is provided above the gate electrode via a pair of thin insulating films, and the extremely thin insulating film and the thin insulating film are provided between the pair of high-concentration impurity regions on the first conductivity type semiconductor substrate. A nonvolatile semiconductor memory in which a control electrode is formed via a thick insulating film.