JP2875303B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a substrate back bias voltage generation circuit included in the semiconductor integrated circuit.
The present invention relates to a technology effective when applied to a RAM, a pseudo static RAM, and the like.

(Prior art)

In a semiconductor integrated circuit composed of MOSFETs (insulated gate type field effect transistors), a substrate back bias voltage is built in to reduce the parasitic capacitance between a circuit element such as a MOSFET and the semiconductor substrate, etc. There is a technology to generate in. According to this technique, the power supply voltage to be supplied to the semiconductor integrated circuit can be reduced to a single voltage such as 5 V, and the malfunction can be prevented by increasing the gate threshold voltage of the parasitic MOS transistor.

A conventional substrate bias generation circuit includes an oscillation circuit such as a ring oscillator, and a charge pump circuit that rectifies a periodic signal formed by the oscillation circuit, and generates a substrate back bias voltage according to the oscillation frequency of the oscillation circuit. Occur.

By the way, the current flowing through the substrate is greatly different between the chip selection state in which the internal circuits start operating simultaneously and the chip non-selection state or the standby state in which the internal circuits hardly operate. Regardless of this, if the common substrate bias generation circuit is operated, the same operation as in the chip selection state is performed even in the chip non-selection state, and the power consumption increases.

Therefore, as described in JP-A-61-59688, a technique for intermittently controlling the start / stop of the operation of the oscillation circuit according to the level of the substrate back bias voltage has been proposed.

[Problems to be Solved by the Invention] However, in the related art of performing intermittent control of completely stopping or restarting the operation of the oscillation circuit according to the substrate back bias voltage, the substrate is not connected when intermittent operation is resumed. The present inventor has found that since the charge must be supplied rapidly, the circuit constants must be set in advance so that the operation cycle of the oscillation circuit is relatively short. Alternatively, even in the standby state, relatively large power consumption is required. In particular, a semiconductor integrated circuit that is backed up by a battery, such as a pseudo SRAM, is required to reduce power consumption during standby.

It is an object of the present invention to provide a semiconductor integrated circuit that can control an oscillation frequency steplessly according to a substrate back bias voltage, thereby reducing power consumption when a chip is not selected or in a standby state. is there.

The above and other objects and novel features will become apparent from the description and the accompanying drawings of this specification.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor integrated circuit including a substrate back bias circuit including an oscillation circuit whose oscillation cycle is determined according to a time constant of a charge path or a discharge path of a predetermined node, and a charge pump circuit, A discharge path or a charge path is connected to a resistor circuit in which MOSFETs whose transconductance is reduced in series with an increase in the absolute value of the generated substrate back bias voltage are connected in series in multiple stages.

(Operation)

According to the above means, a large number of MOs included in the resistance circuit
The threshold voltage of the SFET is controlled steplessly according to the level of the back bias voltage due to its body effect. As the absolute value of the back bias voltage increases, the threshold voltage of the MOSFET increases, and the CR of charge path or discharge path
The time constant increases, which causes the oscillation cycle of the oscillation circuit to become longer, thereby acting to reduce the absolute value of the back bias voltage, and conversely, the threshold value of the MOSFET decreases as the absolute value of the back bias voltage decreases. As the voltage decreases, the CR time constant of the charge path or the discharge path of the oscillation circuit decreases, thereby shortening the oscillation cycle of the oscillation circuit and increasing the absolute value of the back bias voltage. As described above, since the substrate back bias circuit attempts to converge the substrate back bias voltage to a predetermined value without intermittently stopping / restarting the operation, it is necessary to rapidly supply charges to the substrate as in the related art. As a result, there is no need to set circuit constants in advance so that the operation cycle of the oscillation circuit is relatively short. As a result, reduction in power consumption in a chip non-selection state or a standby state is achieved.

Here, the MOSFET included in the resistor circuit is an N-channel type MO
When using an SFET, it is desirable to increase the fluctuation of the threshold voltage due to the body effect on the MOSFET. In that case, separate the N-channel MOSFET from the other N-channel MOSFETs and introduce the impurity at a high concentration. It is desirable to form it in the dedicated P-type well region. When the resistor circuit is arranged in the charging path, it is preferable to form the resistor circuit in a dedicated N-type well region into which impurities are introduced at a high concentration separately from other P-channel MOSFETs.

In order to simplify the configuration of the substrate back bias circuit including such a resistance circuit, it is desirable to bias the gate electrode of the MOSFET included in the resistance circuit with a constant voltage.

〔Example〕

FIG. 2 is a circuit block diagram showing an embodiment of a pseudo-static RAM to which the present invention is applied. The circuit elements that make up each block in the figure are CMOS (complementary MO
S) It is formed on one semiconductor substrate such as single crystal silicon by a manufacturing technique. In the following figures, MOSFETs with arrows added to the channel (back gate) part are P
N-channel type with no arrows
Displayed separately from MOSFET.

In the pseudo-static RAM of this embodiment, the memory array is composed of so-called one-element type dynamic memory cells, so that high integration and low power consumption of the circuit are achieved. Also, X address signals AXO to AXi and Y
Address signals AYO to AYj are input via respective external terminals, and a chip enable signal
By providing ▼, write enable signal ▲ ▼, and output enable signal ▲ ▼, input / output interface conditions compatible with ordinary static RAMs are provided. The pseudo-static RAM further includes a refresh control circuit RFC, and has a self-refresh function for autonomously executing a refresh operation unique to a dynamic memory cell. As a result, the pseudo-static RAM of this embodiment can be replaced with a relatively expensive bipolar RAM or CMOS static RAM as long as the access time does not matter.

In the pseudo-static RAM of this embodiment, the refresh control circuit RFC includes a refresh address counter RCTR and a refresh timer circuit RT as described later.
M and a refresh timing generator RTG. A refresh control signal RFC is supplied to the refresh control circuit RFC via an external terminal. When the refresh control signal ▼ is repeatedly changed from a high level to a low level in a predetermined cycle, the pseudo static RAM is set to an auto refresh cycle. In this auto-refresh cycle, the refresh control circuit RFC increments the refresh address counter RCTR one by one according to the refresh control signal ▲, and executes a refresh operation for each word line. On the other hand, when the refresh control signal ▼ is continuously at the low level for a predetermined period or more, the pseudo static RAM is in a self-refresh cycle.
In this self-refresh cycle, the refresh control circuit RFC periodically executes a series of refresh operations on all the word lines according to a start timing signal supplied from the refresh timer circuit RTM.

In FIG. 2, although not particularly limited, the memory array M-ARY is of a two-intersection (folded bit line) type, and has n + 1 sets of complementary data lines D0.
▲ ▼ to Dn ・ ▲ ▼ and m + arranged vertically
(N + 1) × (m +) arranged in a grid at the intersection of one word line W0 to Wm and their complementary data line and word line
1) memory cells.

Each memory cell of the memory cell array M-ARY is a so-called one-element type dynamic memory cell, and includes an information storage capacitor Cs and an address selection MOSFET Qm, respectively.
It consists of. MOSF for address selection of m + 1 memory cells arranged in the same column of memory array M-ARY
The drain of ETQm is connected to the corresponding complementary data line D0
DDnn ▲▲ are alternately coupled to a non-inverted signal line or an inverted signal line with a predetermined regularity. Further, the gates of the address selection MOSFETs Qm of the (n + 1) memory cells arranged in the same row of the memory array M-ARY are commonly coupled to the corresponding word lines W0 to Wm, respectively. A predetermined self-plate voltage is commonly supplied to the other electrode of the information storage capacitor Cs of each memory cell, that is, the cell plate.

Word lines W0 to Wm constituting the memory array M-ARY are:
It is coupled to the row address decoder RDCR, and is alternatively selected.

The row address decoder RDCR receives, from a row address buffer RADB to be described later, i + 1-bit complementary internal address signals a x0 to a xi (here, for example,
ax0 and the inverted internal address signal ▼ are combined and represented as a complementary internal address signal ax0. The same applies hereinafter), and the timing signal φ is supplied from the timing generation circuit TG.
x is supplied. The timing signal φx is normally set to a low level, and is set to a high level at a predetermined timing when the pseudo static RAM is selected in a normal operation mode or a refresh mode.

The row address decoder RDCR outputs the timing signal φ
When x is set to a high level, it is selectively activated. In this operation state, the row address decoder RD
CR decodes the complementary internal address signals a x0~ a xi, the corresponding one word line to a selected state of alternatively high level.

The row address buffer RADB receives and holds a row address signal transmitted from the address multiplexer AMX. Further, based on these row address signals, forming the complementary internal address signals a x0~ a xi.

To one input terminal of the address multiplexer AMX,
I + 1-bit X input through external terminals AX0 to AXi
Address signals AX0 to AXi are supplied. The other input terminal of the address multiplexer AMX is not particularly limited, but a refresh control circuit RFC (described later) outputs i + 1
Bit refresh address signals rx0 to rxi are supplied. The address multiplexer AMX is further supplied with a timing signal φref from the timing generation circuit TG. The timing signal φref is at a low level when the pseudo-static RAM is in a normal write or read operation mode, and is at a high level when the auto-refresh or self-refresh mode is set.

The address multiplexer AMX selects the X address signals AX0 to AXi supplied via the external terminals A0 to Ai in a normal memory access in which the timing signal φref is set to the low level, and selects the row address buffer as the row address signal. Communicate to RADB. In each refresh mode in which the timing signal φref is at a high level, the refresh address signals rx0 to rxi supplied from the refresh control circuit RFC are selected and transmitted to the row address buffer RADB as row address signals.

On the other hand, the complementary data lines D constituting the memory array M-ARY
On the other hand, 0 • ▲ ▼ to Dn • ▲ ▼ are coupled to the corresponding unit amplifier circuit USA of the sense amplifier SA.

The sense amplifier SA includes n + 1 unit amplifier circuits USA. Each unit amplifier circuit of sense amplifier SA USA
Is a P-channel MO, as exemplarily shown in FIG.
CM consisting of SFET Q10, Q11 and N-channel MOSFET Q30, Q31
An OS latch circuit has a basic configuration. The input / output nodes of these latch circuits are connected to the corresponding complementary data lines D0.
It is coupled to the non-inverting signal line and the inverting signal line of Dn. The unit circuit of the sense amplifier SA is not particularly limited, but may be a P-channel type drive MOSFET.
The power supply voltage Vcc of the circuit is supplied via Q9, and the ground potential of the circuit is supplied via an N-channel drive MOSFET Q29.

The gate of the drive MOSFET Q29 has a timing generator TG
Supplies a timing signal φpa. Also, drive MO
The gate of the SFET Q9 is supplied with an inverted signal of the timing signal φpa by the inverter circuit N5. The timing signal φpa is normally at a low level, and this pseudo-static type RAM is set to a selected state and a minute read signal output from a memory cell coupled to a selected word line is established to a corresponding complementary data line. At the high level. When the timing signal φpa is set to the high level,
Both the drive MOSFETs Q9 and Q29 are turned on, and the (n + 1) unit amplifier circuits USA of the sense amplifier SA are simultaneously operated.

In the operation state, each unit amplifier circuit USA of the sense amplifier SA operates from the (n + 1) memory cells coupled to the selected word line to the corresponding complementary data line D0.
The small read signals output via Dn and ▲ ▼ are respectively amplified to be high level or low level binary read signals. These binary read signals are rewritten to the corresponding memory cells when the pseudo-static RAM is set to the read mode or each refresh cycle, and the stored data is refreshed. In other words,
Alternatively, the word lines W0 to Wm are selectively set to a high level,
By bringing the unit amplifier circuits USA of the sense amplifier SA into the operating state all at once, a refresh operation of the dynamic memory cell can be realized.

Complementary data lines D0 and ▲ constituting the memory array M-ARY
▼ to Dn • ▲ ▼ are coupled on the other side to the corresponding switch MOSFETs of the column switch CSW. The column switch CSW is connected to the complementary data lines D0
N + 1 pairs of switch MOSFs provided corresponding to ▲ ▼
ETQ36, Q37 to Q38, Q39. One of these switch MOSFETs is coupled to a corresponding complementary data line, and the other is commonly connected to a non-inverted signal line CD and an inverted signal line ▼ of the complementary common data line. The gates of each pair of switch MOSFETs are commonly connected, and corresponding data line selection signals Y0 to Yn are supplied from the column address decoder CDCR. As a result, each pair of switch MOSFETs constituting the column switch CSW is turned on when the corresponding data line selection signal Y0 to Yn is alternatively set to a high level, and a set of designated complementary data Line and the common complementary data line CD • ▲ ▼ are selectively connected.

The column address decoder CDCR is supplied with complementary internal address signals a y0 to a yj of j + 1 bits from a column address buffer CADB described later.
The timing signal φy is supplied from the TG. The timing signal φy is normally at a low level,
When the RAM is set to the selected state and the amplification operation by the sense amplifier SA ends, the level is set to the high level.

The column address decoder CDCR is selectively turned on when the timing signal φy is set to a high level. In this operating state, the column address decoder CDCR decodes the complementary internal address signals a y0 to a yj and selectively sets the corresponding data line selection signals Y 0 to Yn to a high level.

The column address buffer CADB is provided with j + 1-bit Y address signals AY0 to AY0 supplied via external terminals AY0 to AYj.
Capture and hold Yj. In addition, these Y address signals
Based on AY0 to AYj, the complementary internal address signals a y0 to a yj
To form

The complementary common data line CD
Input terminals are connected and the data input buffer
DIB output terminals are coupled. The output terminal of the main amplifier MA is further coupled to the input terminal of the data output buffer DOB, and the output terminal of the data output buffer DOB is coupled to the data input / output terminal DIO. The input terminal of the data input buffer DIB is also commonly connected to the data input / output terminal DIO.

Main amplifier MA is selectively activated according to timing signal φma supplied from timing generation circuit TG. In this operation state, the main amplifier MA further amplifies the binary read signal output from the selected memory cell of the memory array M-ARY via the corresponding complementary data line and complementary common data line CD ・. , To the data output buffer DOB.

When the pseudo-static type RAM is set to the read operation mode, the data output buffer DOB is used for the timing generation circuit TG.
Is selectively activated according to a timing signal φr supplied from. In this operation state, data output buffer DOB sends a read signal of a memory cell transmitted from main amplifier MA to an external device via data input / output terminal DIO.

When the dynamic RAM is set to the write operation mode, the data input buffer DIO is selectively activated by the timing generation circuit TG. In this operation state, the data input buffer DIO uses the write data supplied via the data input / output terminal DIO as a complementary write signal and supplies it to the complementary common data line CD.

As described above, the refresh control circuit RFC includes the refresh timer circuit RTM, the refresh address counter RCTR, and the refresh timing generation circuit RTG. The refresh control circuit RFC includes a refresh control signal ▲ supplied through an external terminal, as described later.
According to ▼, an auto refresh cycle or a self refresh cycle is selectively executed.

In each refresh cycle, the refresh control circuit RFC supplies the timing signal φrs for starting the refresh operation to the timing generation circuit TG. The timing generation circuit TG forms various timing signals necessary for the refresh operation according to the timing signal φrs, and supplies the timing signals to the respective circuits. Each time the refresh operation for one word line is completed, the timing signal φ
re is supplied to the refresh control circuit RFC. The timing signal φre is a count pulse for incrementing the refresh address counter RCTR.

The timing generation circuit TG outputs the chip enable signal ▲
Based on ▼, write enable signal ▲, and output enable signal ▲ ▼, the above various timing signals are formed and supplied to each circuit. Further, according to the timing signal φrs supplied from the refresh control circuit RFC, various timing signals necessary for the refresh operation are formed and supplied to each circuit. Further, when the refresh operation for one word line is completed, the timing generation circuit TG forms a timing signal φre and supplies it to the refresh control circuit RFC.

A substrate back bias circuit (hereinafter simply referred to as a substrate bias generation circuit) Vbb-G is a + 5V voltage applied between a power supply terminal Vcc constituting an external terminal of the integrated circuit and a reference potential terminal (or ground terminal) GND. It is operated by a positive power supply voltage and outputs a negative bias voltage.

The bias voltage output from the substrate bias generation circuit Vbb-G is supplied to the MOSFET Qm in the memory array and a semiconductor region as a base gate of the MOSFET constituting the illustrated circuit block.

Although not particularly limited, the CMOS integrated circuit of this embodiment is
It is formed on a semiconductor substrate made of single crystal P-type silicon.
An N-channel MOSFET such as the MOSFET Qm in the memory array M-ARY includes a source region, a drain region formed on the surface of the semiconductor substrate, and a thin gate insulating film on the surface of the semiconductor substrate between the source region and the drain region. And a gate electrode made of polysilicon formed through the gate electrode. The P-channel MOSFET is formed in an N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes the base gates of the plurality of N-channel MOSFETs formed thereon. The N-type well region forms a base gate of the P-channel MOSFET formed thereon. The base gate of the P-channel MOSFET, that is, the N-type well region is connected to the power supply terminal Vcc of FIG.

Although the CMOS integrated circuit of this embodiment is not shown,
Of the main surface of the semiconductor substrate, a surface portion other than a surface portion to be an active region, that is, a surface portion other than a surface portion where a MOSFET, a MOS capacitor, a semiconductor wiring region, etc. are to be formed, has a relatively thick field. Covered by an insulating film. The required wiring layer is extended over the field insulating film or over the active region via the insulating film.

According to this structure, the back bias voltage -Vbb output from the substrate bias generation circuit Vbb-G is supplied to the base gate of the N-channel MOSFET formed on the surface of the semiconductor substrate.

The back bias voltage reduces the junction capacitance formed by the PN junction between the source / drain region of the N-channel MOSFET and the semiconductor substrate and the junction capacitance formed by the PN junction between the semiconductor wiring region and the semiconductor substrate. .
Accordingly, the integrated circuit can operate at high speed because the parasitic capacitance that limits the operation speed of the integrated circuit is reduced.

MOSFETs, such as address selection MOSFETs, often cause leakage current, even when they are turned off. The threshold voltage of this MOSFET is appropriately increased by the substrate bias effect when the back bias voltage -Vbb is applied, thereby reducing such a leakage current. As a result of the reduction in the leak current in the address selection MOSFET, the charge held in the information storage capacitor Cs is held for a relatively long time.

In an integrated circuit, a structure consisting of a field insulating film and a wiring such as a signal wiring extending thereon is formed by a parasitic MOSF.
It is considered to form part of the ET structure. The back bias voltage -Vbb increases the threshold voltage of the parasitic MOSFET,
Make the parasitic MOSFET inoperable.

The substrate bias generation circuit Vbb-G periodically generates a bias voltage by a charge pump function using a capacitor, as will be apparent from the description below. The back bias voltage is smoothed by a parasitic capacitance and a stray capacitance existing between the semiconductor substrate to which the back bias voltage is applied and the power supply wiring and the semiconductor region.

The back bias voltage is reduced by a leak current generated between the source / drain region of the MOSFET and the semiconductor substrate.

Here, the leak current to the semiconductor substrate is not always constant and is affected by the circuit operation. This leak current is relatively small if the switch state of the MOSFET is fixed or stationary without changing the switch state as in the chip non-selection state or the standby state. On the other hand, when the switching state of the MOSFET is changed as in the chip selection state, the leakage current increases accordingly. As for the mechanism of the generation of the leak current to the substrate, if necessary, the Physics of semiconductor ds.
evices) pp. 480-487.

In the pseudo SRAM shown in FIG. 2, the substrate leakage current is calculated based on the chip enable signal ▲ ▼ and the output enable signal ▲ ▼, etc.
When a circuit such as an address buffer, a decoder, or a sense amplifier is operated, the value is increased accordingly.

According to this embodiment, the substrate bias generation circuit Vbb-G
Is a first generation circuit Vbb having a relatively large current driving capability so that the substrate bias potential can be maintained at an appropriate value even when the substrate leakage current is increased in the chip selection state. -G1 and a second generation circuit Vbb-G2 having a minimum necessary current driving capability in a chip non-selection state or a standby state. Thus, low power consumption is achieved by selectively using both circuits according to the operation state of the pseudo SRAM.

Although not particularly limited, according to this embodiment, the operation states of the first generation circuit Vbb-G1 and the second generation circuit Vbb-G2 in the substrate bias generation circuit Vbb-G are determined by the timing control circuit based on the chip enable signal ▲ ▼. Control is performed based on a control signal φce and a refresh control signal φref output from the TG. That is, the chip enable signal ▲
When ▼ is asserted to a low level to be in a chip state, and when a refresh operation is instructed by the refresh control signal φref, the first generation circuit Vbb
The operation of -G1 is selected, and the operation of the second generation circuit Vbb-G2 is selected when other chips are not selected or in standby.

FIG. 1 shows an example of the second generation circuit Vbb-G2 included in the substrate bias generation circuit Vbb-G.

The second generation circuit VBB-G2 shown in FIG.
And an amplifier circuit AMP composed of a CMOS inverter circuit INVa for shaping and amplifying the output waveform, and a charge pump circuit PUMP functioning as a rectifier circuit.

The oscillation circuit OSC is operated by the power supply voltage Vcc, and is configured as a ring oscillator configured by, for example, coupling odd-numbered stages of CMOS inverter circuits INV1 to INVi in a ring shape.

The charge pump circuit PUMP is different from the charge pump capacitor C1 in that its gate electrode acts as a drain electrode (depending on the applied voltage polarity as a drain electrode or a source electrode) so as to operate as a rectifying element. N-channel MOSFETs Q40 and Q41 coupled to a drain electrode for convenience. Although not particularly limited, the capacitor C1 is an N-channel MOSF
By adopting a configuration similar to ET, a MOS capacitor structure is obtained. One electrode of the capacitor C1, that is, the electrode corresponding to the gate electrode of the MOSFT,
It is coupled to the output terminal of the CMOS inverter circuit INVa. The other electrode of capacitor C1, that is, the electrode corresponding to the source or drain electrode of the MOSFET, is connected to MOSFETs Q40 and Q41.
Are connected to a common connection point.

A MOSFET Q40 as a rectifier is provided between the other electrode of the capacitor C1 and the ground point GND of the circuit.
Is provided between the other electrode and the substrate bias electrode pad PAD. This electrode pad PAD is electrically connected to a semiconductor substrate or the like, and has a substrate bias voltage −Vbb
Supply. Note that a parasitic capacitance Cb (not shown) that substantially holds the back bias voltage exists between the substrate and the like and the ground potential point of the circuit.

The diode-type MOSFET Q40 is turned on when the oscillation pulse is at a high level (power supply voltage Vcc). Thus, the capacitor C1 is precharged by the output high level. When the oscillation pulse is set to a low level (ground potential of the circuit), the other electrode of the capacitor C1 has a negative voltage of-(Vcc-Vth). Where Vth is MOS
This is the threshold voltage of FETQ40. The diode-type MOSFET Q41 is turned on by this negative potential, and the parasitic capacitance C
Apply a negative potential to b. As a result, a substrate bias voltage of -Vbb is applied to the substrate and the like.

The current supply capability of the second generation circuit Vbb-G2 is substantially determined by the capacitance of the capacitor C1 and the oscillation frequency of the oscillation circuit OSC. That is, the amount of charge injected into the semiconductor substrate or the like in response to one oscillation output pulse increases as the capacitance of the capacitor C1 increases. In addition, the number of times that electric charges are injected into a semiconductor substrate or the like per unit time increases as the oscillation frequency of the oscillation circuit OSC increases.

According to this embodiment, the second generation circuit Vbb-G2 only needs to have a relatively small current supply capability that can compensate for a leakage current flowing to the substrate in a chip non-selection state or a standby state. Has become. In other words, the configuration is such that the required power supply capability is relatively small while exhibiting low power consumption characteristics. The oscillation frequency of the oscillation circuit OSC depends on the CMO that constitutes the oscillation circuit.
By setting an appropriate number of S-inverter circuits and an appropriate setting of the respective signal delay characteristics, a relatively low value such as, for example, 1 to 2 MHz is obtained. The capacitance of the capacitor C1 is set to a relatively small value.

Here, the power consumption in the oscillation circuit OSC is proportional to the oscillation frequency. In other words, the operating current or current consumption of each CMOS inverter circuit that constitutes the oscillation circuit OSC is the same as that of the well-known CMOS inverter circuit, and the load capacitance (wiring capacitance and subsequent stage) coupled to each output. (Which consists of the input capacitance of the inverter circuit, etc.) is proportional to the so-called transient current required for charging and discharging, and is substantially in a stationary state where each input or output is at a high level or a low level. 0. Since the transient current of each CMOS inverter circuit is proportional to the operating frequency, the power consumption of the low-frequency oscillation circuit OSC is originally smaller than that of the first generation circuit Vbb-G1.

Further, this oscillation circuit OSC can autonomously control its oscillation frequency according to the back bias voltage level,
As a result, the power consumption is further reduced. Hereinafter, this will be described in detail.

The CMOS inverter circuit INV2 included in the oscillation circuit OSC
A capacitor C2 as a capacitive element having a predetermined capacitance is arranged between the output terminal of the CMOS inverter circuit INV3 and the input terminal of the CMOS inverter circuit INV3. Although not particularly limited, the capacitor C2 is constituted by a gate capacitance of an N-channel MOSFET or a capacitance having a structure in which a metal electrode is covered on a thin oxide film formed on a silicon substrate. One electrode of the capacitor C2 is coupled to the ground potential of the circuit, and the other electrode is coupled as a node N1 to the output terminal of the CMOS inverter circuit INV2 and the input terminal of the CMOS inverter circuit INV3. N constituting the CMOS inverter circuit INV2
An N-channel MOSFET connected in series and multiple stages between the source electrode of the channel MOSFET Q42 and the ground potential of the circuit.
A resistance circuit REG including Qr1 to Qrn is arranged.

P-channel type in the CMOS inverter circuit INV2
The MOSFET Q43 forms a charging path for charging the capacitor C2 to the power supply voltage Vcc.
The FETs Qr1 to Qrn form a discharge path of the capacitor C2. CMOS inverter circuit having an input terminal coupled to the node N1
INV3 functions as a level determination circuit that determines the level of the node N1 with a predetermined logical threshold. And
CMOS inverter circuits INV4 to INV1 coupled between the output terminal of the CMOS inverter circuit INV3 and the input terminal of the CMOS inverter circuit INV2 charge the capacitor C2 and
It functions as a reset circuit for initializing the voltage level of N1 to the power supply voltage Vcc. The CMOS inverter circuit
The N-channel type MOSFET Q44 having a gate electrode coupled to the output terminal of INV3 discharges the charge of the capacitor C2 rapidly after the output level of the CMOS inverter circuit INV3 is inverted to a high level to prevent malfunction due to power supply noise or the like. It is provided to increase the noise margin.

Here, before proceeding with the description of the resistance circuit REG, a basic operation of the oscillation circuit OSC will be described.

When the output of the CMOS inverter circuit INV1 is set to low level, the MOSFET Q43 is turned on in synchronization with this, and the node N1 is charged to high level via the capacitor C2. This state inverts the output signal of the inverter circuit INV1 to a high level. As a result, the node N1 is gradually discharged through the MOSFET Q42 in the ON state and the resistance circuit REG,
When the level N1 is lowered below the logical threshold voltage of the CMOS inverter circuit INV3, the output of the CMOS inverter circuit INV3 detecting this is inverted. This output change is sequentially fed back to the CMOS inverter circuit INV2, and the node N1 is charged to the initial level again. Oscillation is caused by repeating the charging / discharging operation for the node N1, and a pulse signal having a cycle corresponding to the oscillation cycle is output from the amplifier circuit AMP.
To the charge pump circuit PUMP.

The cycle of this pulse signal is determined exclusively by the CR time constant τ when the initial potential of the node N1 is discharged and the logical threshold voltage of the CMOS inverter circuit INV3, and the resistance component of the CR time constant τ is the MOSFET Q42. And the resistance value of the resistor circuit REG.

Here, the gate electrodes of the MOSFETs Qr1 to Qrn included in the resistance circuit REG are biased by the bias circuit VB, and the conductance based on them is set.
Furthermore, the MOSFETs Qr1 to Qrn included in the resistance circuit REG and the MOS
The back gate of the FET Q42 is supplied with a back bias voltage -Vbb. Thereby, the conductance of these MOSFETs is controlled autonomously by the body effect according to the back bias voltage -Vbb. That is, the threshold voltages of a number of MOSFETs Qr1 to Qrn included in the resistance circuit REG are steplessly controlled according to the level of the back bias voltage −Vbb due to the body effect, and the back bias voltage −Vb
As the absolute value of b increases, the threshold voltage of the MOSFETs Qr1 to Qrn increases, and the CR time constant of the discharge path of the oscillation circuit OSC increases, which increases the oscillation cycle of the oscillation circuit OSC and increases the back bias voltage. Acts to reduce the absolute value of -Vbb. Conversely, as the absolute value of the back bias voltage −Vbb decreases, the threshold voltage of the MOSFETs Qr1 to Qrn decreases, and the CR time constant of the discharge path of the oscillation circuit OSC decreases, thereby shortening the oscillation cycle of the OSC. This acts to increase the absolute value of the back bias voltage -Vbb. As described above, the second generation circuit Vbb-G2 of the substrate bias generation circuit Vbb-G attempts to converge the substrate back bias voltage -Vbb to a predetermined value without intermittently stopping / restarting its operation. Since there is no need to rapidly supply electric charges to the substrate as in the above, there is no need to set circuit constants in advance so that the operation cycle of the oscillation circuit is relatively short, and as a result, the chip is not selected. Reduction of power consumption in the state or the standby state can be achieved.

Here, one N-channel type M included in the resistance circuit REG
The variation of the threshold voltage due to the substrate effect in the OSFET is relatively small. Resistor circuit REG obtained by the substrate effect
In order to increase the change amount of the whole resistance value to several times or about ten times, a large number of MOSFETs may be connected in series according to the magnification. In order to increase the variation of the threshold voltage of each MOSFET due to the body effect, the MOSFET is separated from other N-channel MOSFETs as shown in FIG.
ETQr1 to Qrn may be formed in a P-type well region P-WELL dedicated to the resistance circuit RGE into which impurities are introduced at a high concentration. In this case, a double-well CMOS process is required, the other typical N-channel MOSFET Qn is formed on a P-type semiconductor substrate P-SUB, and the representative P-channel MOSFET Qp is an N-type MOSFET. It is formed in the well region N-WELL. The N-type well region N-WELL is coupled to the power supply terminal Vcc, and the P-type well region P-WELL and the semiconductor substrate P-WELL.
SUB is supplied with a back bias voltage -Vbb. In FIG. 3, 1 is a field oxide film, 2 is a source / drain region of a MOSFET, and 3 is a MOSFET made of polysilicon or the like.
, A gate oxide film, 5 an insulating layer, 6 an aluminum wiring layer, and the structure of the upper layer is omitted.

Although FIG. 1 does not show a circuit configuration for selecting the operation of the second generation circuit Vbb-G2, for example, the oscillation circuit OS
Instead of at least one CMOS inverter circuit included in the C loop, or a 2-input NAND gate circuit having an output terminal coupled to the loop may be arranged.
A control signal for selecting an operation is supplied to one input terminal of the NAND gate circuit. When this control signal is set to the high level, the oscillating operation is enabled, and when set to the low level, the operation of the oscillating circuit OSC is deselected.
Although the first generation circuit Vbb-G1 is not shown in the figure, it has the necessary current driving capability as in FIG.
Alternatively, it can be configured without providing the resistor circuit REG.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited thereto, and various modifications can be made without departing from the gist of the invention.

For example, in the above-described embodiment, the description has been given of the oscillation circuit in which the node N1 is charged and then discharged in the initial state.On the contrary, the operation of discharging the node N1 in the initial state and then charging the node N1 is repeated. A transmission format may be adopted. In this case, the resistor circuit is arranged on the power supply terminal Vcc side with respect to the node N1.

In addition, as shown in FIG.
An N-channel MOSFET Q46 that receives a back bias voltage −Vbb at the back gate may be inserted between the output terminal of Va and the capacitor C1. Such a MOSFET Q46 applies a voltage lower by the threshold voltage to the capacitor C1, so that the power supply voltage actually used in the internal circuit is lower than the power supply voltage supplied from the outside due to miniaturization of the MOSFET. In such a case, the absolute value of the back bias voltage −Vbb can be easily reduced. Further, in the above embodiment, the level determination circuit for detecting a level change due to charging / discharging of the node N1 is constituted by a CMOS inverter. However, an inverter having another circuit form, or another circuit form may be employed. In addition, the discharge path and the charge path to the node N1 are defined by an N-channel MOSFET and a P-channel
Although basically constituted by MOSFETs, this circuit type can be changed as appropriate.

In the circuit block of FIG. 2, the memory array M-ARY may be constituted by a plurality of memory mats. However, in this case, a refresh operation for a plurality of word lines may be performed simultaneously by selecting one word line in each memory mat. Further, the pseudo-static RAM may be capable of simultaneously inputting and outputting a plurality of bits of information, or each of the plurality of memory mats may share each address decoder. Pseudo static type
The RAM circuit block configuration, control signals, address signals, and the like can take various other forms.

In the above description, the case where the invention made by the inventor is mainly applied to a pseudo-static RAM as a background of application has been described. However, the present invention is not limited thereto.
It can be widely applied to semiconductor storage devices such as M and various semiconductor integrated circuits such as microcomputers. The present invention can be widely applied to at least a condition requiring a substrate back bias.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, a resistor circuit in which MOSFETs whose transconductance is reduced in series according to an increase in the absolute value of the substrate back bias voltage are connected in series and multiple stages to a discharge path or a charge path of an oscillation circuit whose oscillation cycle is determined by a charge / discharge time of a predetermined node. To form a substrate back bias circuit together with the charge pump circuit, so that the threshold voltage of many MOSFETs included in the resistance circuit can be controlled steplessly according to the level of the back bias voltage due to the substrate effect. Therefore, the substrate back bias circuit can try to converge the substrate back bias voltage to a predetermined value without intermittently stopping / restarting the operation. Since it is not necessary to supply electric charges rapidly to the circuit, the circuit constant must be set in advance so that the operation cycle of the oscillation circuit is relatively short. Away from constraint that must be kept constant, there is an effect that it is possible to achieve a reduction in power consumption in the chip non-selection state or a standby state as a result.

In addition, by separating the MOSFET included in the resistance circuit from other N-channel MOSFETs and forming the MOSFET in a dedicated well region into which impurities are introduced at a high concentration, the MOSFET included in the resistance circuit itself is caused by a body effect. The fluctuation of the threshold voltage can be increased. Therefore, the control range of the CR time constant of the charging path or the discharging path can be easily increased without unnecessarily increasing the number of series stages of MOSFETs included in the resistance circuit.

By biasing the gate electrode of the MOSFET included in the resistance circuit with a constant voltage, the configuration of the resistance circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a back bias voltage generation circuit included in a pseudo SRAM according to one embodiment of the present invention. FIG. 2 is a circuit block diagram of the whole pseudo SRAM according to one embodiment of the present invention. FIG. 3 is a partial cross-sectional view of a device structure of the pseudo SRAM, and FIG. 4 is a diagram showing a state in which a back bias voltage is received between an oscillation circuit and a charge pump circuit in a back bias voltage generation circuit to control its threshold voltage. FIG. 4 is a circuit diagram in the case where MOSFETs are arranged. M-ARY: Memory array, Qm: MOSFET for selection, Cs ...
... Capacitor for information storage, TG ... Timing generator, Vbb-G ... Substrate back bias generation circuit, Vbb-G1
... First generation circuit, Vbb-G2... Second generation circuit, -Vbb
… Substrate back bias voltage, OSC …… Oscillation circuit, AMP ……
Amplifier circuit, PUMP ... Charge pump circuit, INV2 ... CMOS
Inverter, C2 …… Capacitor, REG …… Resistance circuit, Qr1
~ Qrn N-channel MOSFET, VB Gate bias circuit, P-WELL P-well region, N-WELL N
Mold well region, P-SUB ..... semiconductor substrate.

──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Toshio Nosaka 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra LSE Engineering Co., Ltd. (56) References JP-A-56- 94654 (JP, A) JP-A-61-263145 (JP, A) JP-A-62-156853 (JP, A) JP-A-3-69153 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/04 H01L 21/822

Claims (5)

(57) [Claims] 1. A semiconductor integrated circuit comprising: an oscillation circuit; and a charge pump circuit for rectifying a periodic signal formed by the oscillation circuit, the semiconductor integrated circuit including a substrate back bias circuit for generating a substrate back bias voltage. An oscillation cycle is determined according to a time constant of a charging path or a discharging path of a predetermined node included therein, and the transconductance is set in the discharging path or the charging path in accordance with an increase in the absolute value of the substrate back bias voltage. A resistance circuit in which multiple MOSFETs are connected in series is connected to each other, and the MOSFET included in the resistance circuit is formed in a well region independent of other MOSFETs, and the substrate back bias voltage is applied to the well region. A semiconductor integrated circuit characterized by: 2. A circuit block operable in response to a control signal, and a first current driving capability when the circuit block is selected to supply a substrate bias voltage to the circuit block. A first substrate bias voltage generating circuit for generating a substrate bias voltage, and a second substrate bias voltage generating circuit for generating the substrate bias voltage with a second current driving capability smaller than the first current driving capability when the circuit block is in a non-selected state. A semiconductor integrated circuit including a two-substrate bias voltage generation circuit, wherein the second substrate bias voltage generation circuit generates an oscillation circuit and the substrate bias voltage based on a periodic signal output from the oscillation circuit. The oscillation circuit includes an MO for determining an oscillation cycle according to a time constant of a charging path or a discharging path of a predetermined node included therein. It has a resistance circuit in which SFETs are connected in multiple stages in series, wherein the MOSFET included in the resistance circuit is formed in a well region independent of other MOSFETs, and the substrate back bias voltage is applied to the well region. Semiconductor integrated circuit. 3. The circuit block is a memory array having a plurality of memory cells each including an information storage capacitor and an address selection MOSFET, wherein the substrate bias voltage is a well in which the address selection MOSFET is formed. 3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is supplied to a region. 4. The other MOSFET is the address selection MOSFET, and the address selection MOSFET is included in the resistance circuit.
4. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is formed in a well region independent of the MOSFET. 5. The semiconductor integrated circuit according to claim 1, wherein a gate electrode of a MOSFET included in said resistance circuit is biased at a predetermined voltage.