JP2505163B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a dynamic RAM type semiconductor integrated circuit incorporating a multi-bit counter circuit using a CMOS inverter circuit. The present invention relates to a technique effectively used for a device.

[Conventional technology]

A dynamic RAM (random access memory) is a typical example of a semiconductor integrated circuit device incorporating a multi-bit counter circuit. That is, in the dynamic RAM, it is necessary to refresh the data stored in the memory cell within a predetermined cycle, and an automatic refresh mode (for example, ▲ ▼ before
▼ Refresh mode) is provided. Also, ▲
A refresh address counter is provided for detecting a signal change and sequentially designating a word line to be refreshed. Various types of dynamic RAMs incorporating such refresh address counters are described, for example, in "Hitachi IC Memory Data Book" published by Hitachi, Ltd. in September 1985.

[Problems to be solved by the invention]

In the dynamic RAM as described above, its memory array is composed of memory cells using N-channel MOSFETs, but the peripheral circuits such as the refresh address counter are CMOS in order to speed up the operation and reduce the power consumption. Is often used.

FIG. 4 shows a circuit diagram of a refresh address counter developed by the inventors of the present invention prior to the present invention. This refresh address counter is composed of i + 1-bit unit circuits UREFC0 to UREFCi corresponding to the number of word lines of the dynamic RAM, and each unit circuit has two units as illustrated in the inverter circuits N6 and N7 of FIG. 4, respectively. It includes two flip-flop circuits formed by crossing one CMOS inverter circuit. Dynamic type
The RAM refresh address counter only needs to be able to specify all the word lines by counting in a circulating manner. By omitting the functions for initial setting and reset, the circuit configuration is simple and consumes less power. It

However, the present inventors have found that such a refresh address counter has the following problems. That is, as shown in FIG. 5, the relationship between the consumption current in the non-selected state of the dynamic RAM including the refresh address counter, that is, the standby current Iccs and the voltage fluctuation of the power supply voltage Vcc is A relatively large peak current Ip will flow at the voltage Vp. Such a peak current is generated when the power supply voltage Vcc exceeds the specific voltage Vp when the power supply voltage is turned on, so that the operation of the device when the power is turned on becomes unstable and the rise of the operation is delayed. At the same time, undesired current consumption occurs.

The inventors of the present application have found that such a peak current is caused by the CMOS inverter circuit forming the flip-flop of the refresh address counter at the intermediate level of the power supply voltage Vcc, which is caused by two CMOS inverter circuits which are cross-connected. Focusing on the fact that the stable state continues for a while, we devised a method to eliminate the peak current and stabilize the operation when the power of the device is turned on.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a counter circuit that stabilizes and speeds up the operation when power is turned on, and a semiconductor integrated circuit device including such a counter circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
The flip-flop of the counter circuit is configured by a clocked inverter circuit controlled according to a control signal formed by detecting that the power supply voltage of the circuit has reached a predetermined voltage.

[Action]

According to the above means, the two CMOS inverter circuits in the latch form which form the flip-flop for each bit of the counter circuit are not brought into the latched state until the power supply voltage reaches a predetermined voltage. Undesired peak current can be eliminated and operation can be stabilized.

〔Example〕

FIG. 1 shows a dynamic RA to which the present invention is applied.
A circuit diagram showing one embodiment of the M refresh address counter is shown. Each circuit element in the figure is a well-known CMOS
It is formed on one semiconductor substrate such as single crystal P-type silicon, though not particularly limited, depending on the manufacturing technique of the integrated circuit. In the figure, the MOSFET with an arrow added to the channel (back gate) portion is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow.

The N-channel MOSFET is made of polysilicon formed on the surface of the semiconductor substrate such as the source region, the drain region, and the surface of the semiconductor substrate between the source region and the drain region via a thin gate insulating film. It is composed of such a gate electrode. P-channel MOSFET
Are formed in the N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate of the plurality of N-channel MOSFETs formed thereon. The N-type well region has a P formed on it.
It constitutes the substrate gate of the channel MOSFET. A power supply voltage Vcc is supplied to the substrate gate of the P-channel MOSFET, that is, the N-type well region, and a negative substrate generated by a substrate back bias voltage generating circuit (not shown) is supplied to the substrate gate of the P-channel MOSFET, that is, the N-type substrate. The back bias voltage −Vbb is supplied.

The refresh address counter of this embodiment is used for designating the address of the word line to be refreshed in the dynamic RAM automatic refresh mode. The refresh address counter is a control signal column address strobe signal (not shown) supplied from an external device to the dynamic RAM.
Is activated by a start signal CEN generated in a so-called “before-refresh” refresh mode, which is changed from a high level to a low level prior to the row address strobe signal. Further, thereafter, the stepping clock signal φc formed by detecting that the row address strobe signal () is repeatedly changed from the high level to the low level is counted and the stepping is performed.
The initial state of the refresh address counter when the power is turned on varies depending on the characteristics of the CMOS inverter circuit that configures each flip-flop of the refresh address counter, but since the so-called circulation count is automatically returned from the final address to the start address, By inputting a predetermined number of stepping clock signals φc, it is possible to sequentially specify all the word lines of the dynamic RAM by making a round.

In FIG. 1, the refresh address counter has i + 1 unit circuits UR provided corresponding to the respective bits.
It consists of EFC0-UREFCi. All of these unit circuits have the same configuration, and the specific circuit configuration of the unit circuit UREFC0 is exemplarily shown in FIG.

Unit circuit UREFC0 is a CMOS clocked inverter circuit CN
Two flip-flops FF1 and FF2 configured by cross-connecting 1 and a CMOS inverter circuit N2 and a CMOS clocked inverter circuit CN2 and a CMOS inverter circuit N3, respectively.
Is the main constituent element. The clocked inverter circuit CN1 is composed of series-type P-channel MOSFETs Q2, Q3 and N-channel MOSFETs Q7, Q8 provided between the power supply voltage Vcc of the circuit and the ground potential. It is composed of channel MOSFETs Q4, Q5 and N-channel MOSFETs Q9, Q10. P channel
The commonly connected gates of the MOSFET Q2 and the N-channel MOSFET Q8 serve as an input terminal of the clocked inverter circuit CN1 and are coupled to an output terminal of the CMOS inverter circuit N2. The drains of the P-channel MOSFET Q3 and the N-channel MOSFET Q7, which are commonly connected, are connected to the clocked inverter circuit CN1.
Is connected to the input terminal of the CMOS inverter circuit N2. These clocked inverter circuits CN
1 and the inverter circuit N2 form a flip-flop FF1.

On the other hand, P-channel MOSFET Q4 and N-channel MOSFET Q1
The commonly connected gates of 0 serve as the input terminal of the clocked inverter circuit CN2 and are coupled to the output terminal of the CMOS inverter circuit N3. The commonly connected drains of the P-channel MOSFET Q5 and the N-channel MOSFET Q9 serve as the output terminal of the clocked inverter circuit CN2 and are coupled to the input terminal of the CMOS inverter circuit N3. The clocked inverter circuit CN2 and the inverter circuit N3 form a flip-flop FF2.

The clocked inverter circuits CN1 and CN2 forming the above flip-flops FF1 and FF2 are designed so that the driving ability, that is, the current supply ability, is larger than the current supply ability of the inverter circuits N2 and N3.

The gates of the N-channel MOSFETs Q7 and Q9 are supplied with a control signal WK which is set to a high level when the absolute values of the power supply voltage Vcc and the substrate back bias voltage −Vbb reach a predetermined level from a level detection circuit described later. It The control signal WK is applied to the gates of the P-channel MOSFETs Q3 and Q5.
The inverted signal of the inverter circuit N4 is supplied. As a result, in the clocked inverter circuits CN1 and CN2, the N-channel MOSFETs Q3 and Q5 are turned off in the initial stage of starting the dynamic RAM in which the control signal WK is at low level, and the inverted signal of the control signal WK by the inverter circuit N4 is high. Depending on the level, the P-channel MOSFET and Q7 and Q9 are turned off, so both are inactive. Also,
When the absolute values of the power supply voltage Vcc and the substrate back bias voltage −Vbb reach a predetermined level, the control signal WK becomes high level, the N-channel MOSFETs Q7 and Q9 are turned on, and the low level of the inverted signal of the control signal WK by the inverter circuit N4. As a result, P-channel MOSFETs Q3 and Q5 are turned on, and both clocked inverter circuits CN1 and CN2 are activated. The control signal WK is commonly supplied to the clocked inverter circuits of all the unit circuits of the refresh address counter.

An N-channel MOSFET Q11 that receives the output signal of the NAND gate circuit NAG1 at its gate is provided between the output terminal of the clocked inverter circuit CN1 and the input terminal of the clocked inverter circuit CN2. In addition, the output terminal of the clocked inverter circuit CN2 and the clocked inverter circuit CN1
A series inverter circuit N1 and a P-channel MOSFET Q1 are provided between the input terminal and the input terminal. The gate of this P-channel MOSFET Q1 is also provided with a NAND gate circuit NAG1.
Output signal is supplied.

A column address strobe signal ▲ ▼ externally supplied as a control signal is applied to one input terminal of the NAND gate circuit NAG1 as a row address strobe signal ▲.
The activation signal CEN of the refresh address counter is supplied which is formed by changing from the high level to the low level prior to (3), that is, by being identified as (2) before (3) refresh mode. Further, the other input terminal of the NAND gate circuit NAG1 is supplied with a stepping clock signal φc formed by detecting that the row address strobe signal RAS is repeatedly changed from the high level to the low level.
As a result, the output signal of the NAND gate circuit NAG1 becomes low level when both the activation signal CEN and the stepping clock signal φc become high level, and becomes high level when either one of them is low level. The start signal CE
N is supplied to the NAND gate circuits NAG1 of all the unit circuits of the refresh address counter.

From the above, when the output signal of the NAND gate circuit NAG1 is at the high level, that is, when the refresh address counter is in the non-operating state or the stepping clock signal φc is at the low level in the operating state of the refresh address counter, the NAND gate circuit NAG1 The output signal of becomes high level, and the N-channel MOSFET Q11 is turned on, so that the flip-flops FF1 and FF2 are connected via the MOSFET Q11. As described above, the current supply capacity of the clocked inverter circuit CN1 is designed to be larger than the current supply capacity of the inverter circuit N3.
FF2 is set to the state held by flip-flop FF1 until then. On the other hand, when the output signal of the NAND gate circuit NAG1 becomes low level, that is, both the activation signal CEN and the stepping clock signal φc become high level, the N-channel MOSFET Q11 is turned off and the P-channel M
OSFETQ1 is turned on. Therefore, the flip-flops FF1 and FF2 are connected via the inverter circuit N1 and the MOSFET Q1, and the flip-flop FF1 is set to the inverted state of the state held by the flip-flop FF2.

As described above, the flip-flops FF1 and FF2 of the unit circuit UREFC0 of the refresh address counter are
In the automatic refresh mode in which CEN is set to the high level, each time the stepping clock signal φc is set to the high level, the hold state is inverted and the counter operates as a 1-bit binary counter.

Although not particularly limited, the clocked inverter circuit CN2
The output signal of is the non-inverted output signal CX0 of this unit circuit UREFC0.
Further, the inversion signal from the inverter circuit N1 is supplied to the row address selection circuit for selecting the word line as the inversion output signal CX0 of the unit circuit UREFC0.

On the other hand, the output signal of the clocked inverter circuit CN2, that is, the non-inverted output signal CX0 of the unit circuit UREFC0 is also supplied to one input terminal of the AND gate circuit AG1. The stepping clock signal φc is supplied to the other input terminal of the AND gate circuit AG1. As a result, the output signal of the AND gate circuit AG1 becomes the clocked inverter circuit CN2.
When the output signal of is high level and the stepping clock signal φc is high level, it is made high level. That is, at the output terminal of the AND gate circuit AG1, the stepping clock signal φc1 having a frequency half that of the stepping clock signal φc is obtained. The stepping clock signal φc1 is supplied to the unit circuit UREF.
It is used as a stepping clock signal for the unit circuit UREEFC1 connected next to C0. Similarly, the top unit circuit
UREFCi is supplied with a stepping clock signal φci formed by the unit circuit UREFCi-1 at the preceding stage. From the above, each unit circuit of the refresh address counter is divided by 2 in accordance with the stepping clock signal φc which is divided by 1/2 and supplied by the unit circuit of the preceding stage.
It performs a binary counting operation, and functions as an i + 1-bit binary counter circuit as a whole.

FIG. 2 shows a circuit diagram of an embodiment of the level detection circuit for forming the control signal WK.

In the figure, a series P-channel MOSFE is provided between the power supply voltage Vcc of the circuit and the substrate back bias voltage −Vbb.
TQ6 and N-channel MOSFETs Q12 and Q13 are provided. N
The gates of the channel MOSFETs Q13 are commonly connected to their drains, and have a diode form. The gates of the P-channel MOSFET Q6 and N-channel MOSFET Q12 are
Both are supplied with the ground potential of the circuit. P channel MOSF
The commonly connected drains of the ETQ6 and the N-channel MOSFET Q12 are coupled to the input terminal of the inverter circuit N5. The output signal of the inverter circuit N5 is supplied to the refresh address counter as the control signal WK.

FIG. 3 is a timing chart for explaining the operation of the level detection circuit shown in FIG. Although not particularly limited, the substrate back bias voltage −Vbb is generated by a substrate back bias voltage generation circuit (not shown) based on the power supply voltage Vcc supplied from the outside as the power supply voltage for operating the circuit, and the Unification is achieved. Therefore, when the power is turned on, the substrate back bias voltage −Vbb is generated with a slight delay from the rise of the power supply voltage Vcc.
The absolute value increases toward a predetermined negative voltage.

In the initial stage when the power is turned on, the inverter circuit that becomes the control signal WK when the power supply voltage Vcc rises
The output signal of N5 and the input signal of the inverter circuit N5, that is, the inverted signal ▲ ▼ of the control signal WK both rise. However, when the power supply voltage Vcc reaches a certain level, the substrate back bias voltage −Vbb is not formed, so N
Both channel MOSFETs Q12 and Q13 are turned off,
The P-channel MOSFET Q6 is turned on. This MOSFET Q6
To the input terminal of the inverter circuit N5 via
A high level such as c is supplied, and the output signal of the inverter circuit N5 is set to low level.

Next, when the power supply voltage Vcc rises, a substrate back bias voltage −Vbb is formed, and its absolute value is 2 × Vth.
When (Vth exceeds the threshold voltage of N-channel MOSFETs Q12 and Q13), both N-channel MOSFETs Q12 and Q13 are turned on. Therefore, the potential of the input terminal of the inverter circuit N5 becomes a relatively low voltage determined by the conductance ratio of the MOSFETs Q6, Q12, and Q13, and the output signal of the inverter circuit N5, that is, the control signal WK is inverted and becomes high level.

From the above, the control signal WK detects not only the power supply voltage Vcc but also the level of the substrate back bias voltage −Vbb generated by the built-in substrate back bias voltage generation circuit based on the power supply voltage Vcc. It is formed. Therefore, the two flip-flops of each unit circuit of the refresh address counter, which is composed of a clocked inverter circuit whose operation is controlled by the control signal WK, causes the power supply voltage Vcc to be a specific voltage as shown in FIG. V
It is not in the latched form when p has passed. Therefore, when the power is turned on, an abnormal peak current does not occur, and the operation at the time of start-up of the device is stabilized,
It will be faster.

When the present invention is applied to a semiconductor integrated circuit device such as a dynamic RAM incorporating a multi-bit counter circuit by using a CMOS inverter circuit as shown in the above embodiment, the following effects can be obtained. . That is, (1) by configuring the flip-flop of the counter circuit by a CMOS clocked inverter circuit controlled according to a control signal formed by detecting that the power supply voltage of the circuit has reached a predetermined voltage, By not holding the two clocked inverter circuits forming the flip-flop in the latched state until the power supply voltage reaches a predetermined voltage, it is possible to eliminate an undesired peak current at power-on. .

(2) According to the above item (1), it is possible to stabilize the startup operation of the semiconductor integrated circuit device such as the dynamic RAM having the refresh address counter using the CMOS inverter circuit when the power is turned on and increase the speed. Is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, in the embodiment shown in FIG. 1, a CM that constitutes flip-flops FF1 and FF2.
Although one of the OS inverter circuits is a clocked inverter circuit, both may be a clocked inverter circuit including the inverter circuits N2 and N3. The detection level of the level forming circuit in FIG. 2 may be another level instead of −2 × Vth, or may detect only the rising edge of the power supply voltage Vcc. Further, various embodiments can be adopted as specific circuit configurations of the unit circuit of the refresh address counter and the level detection circuit.

In the above description, the invention of the invention made mainly by the present inventor is a dynamic RA which is the field of application behind the invention.
Although the description has been given of the case where the present invention is applied to the M refresh address counter, the present invention is not limited to this and can be applied to, for example, a counter circuit included in various other semiconductor integrated circuit devices. The invention is at least CMOS
It can be applied to a multi-bit counter circuit using an inverter circuit and a semiconductor integrated circuit device incorporating such a counter circuit.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application. That is, the flip-flop of the counter circuit
The two CMOS inverter circuits that form these flip-flops are configured by a clocked inverter circuit that is controlled according to a control signal that is generated when the power supply voltage of the circuit reaches a predetermined voltage. By not holding the latched state until the voltage reaches a predetermined voltage, an undesired peak power supply at power-on can be eliminated, and a semiconductor integrated circuit device having a multi-bit counter circuit using a CMOS inverter circuit. It is possible to stabilize the start-up operation when the power is turned on and to increase the speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a refresh address counter of a dynamic RAM to which the invention is applied, and FIG. 2 is an embodiment of a level detection circuit of a dynamic RAM to which the invention is applied. FIG. 3 is a circuit diagram, FIG. 3 is a timing diagram for explaining the operation of the level detection circuit of FIG. 2, and FIG. 4 is a refresh address counter of a dynamic RAM developed by the inventors of the present application prior to the present invention. 5 is a characteristic diagram showing the relationship between the power supply voltage Vcc and the standby current Iccs of the dynamic RAM shown in FIG. UREFC0 to UREFCi …… Refresh address counter unit circuit, Q1 to Q6 …… P-channel MOSFET, Q7 to Q13 …… N
Channel MOSFET, N1 to N7 ... CMOS inverter circuit, CN
1, CN2 …… CMOS clocked inverter circuit, NAG1 …… Nand gate circuit, AG1 …… And gate circuit.

Claims (3)

(57) [Claims] 1. A plurality of flip-flops each composed of two CMOS inverter circuits each having an input terminal and an output terminal cross-connected and having no initial setting, and a power supply voltage of the circuit has reached a predetermined voltage. And a level detection circuit for detecting the above, wherein one of the two CMOS inverter circuits in each of the flip-flops has an input point, an output point, and the level detection circuit. First and second control signals that are formed based on the outputs of the
The CMOS clocked inverter circuit has a control input point, and the CMOS clocked inverter circuit includes a first P-channel MOSFET and a first P-channel MOSFET whose gates are commonly connected to the input point.
A first N-channel MOSFET and a gate connected to the first control input point, the source drain of which is connected in series with the source drain of the first P-channel MOSFET, and connected between the power supply terminal and the output point of the circuit; 2P channel MOSF
ET is connected between the output point of the circuit and the ground potential point of the circuit with the gate connected to the second control input point and its source drain connected in series with the source drain of the first N-channel MOSFET. And a second N-channel MOSFET, which is made into a non-operating state by a control signal based on the detection output of the level detection circuit applied to the first and second control input points before the power supply voltage of the circuit reaches the predetermined voltage. A semiconductor integrated circuit device having the above structure. 2. The level detecting circuit detects that a substrate back bias voltage formed by a voltage generating circuit incorporated based on a power supply voltage of a circuit supplied from the outside has reached a predetermined voltage. The semiconductor integrated circuit device according to claim 1, wherein 3. The semiconductor integrated circuit device is a dynamic type
A RAM, wherein the flip-flop is a flip-flop that constitutes a refresh address counter that generates an address for sequentially specifying a word line to be refreshed in the automatic refresh mode of the dynamic RAM. The semiconductor integrated circuit device according to item 1 or 2.