JP2874695B1 - Stacked electronic component array - Google Patents

Abstract

A laminated electronic component array capable of reducing crosstalk between electronic component elements is provided. SOLUTION: An insulator sheet 4 having a common ground internal conductor pattern 3 formed on its surface, a plurality of element internal conductor patterns 5 and an inter-element ground internal conductor pattern 6 for preventing crosstalk are formed on the same surface. The stacked insulator sheets 7 are alternately stacked to form a laminate, and external electrodes for devices and ground external electrodes are formed on side surfaces of the laminate. Further, the insulator sheet 7 is divided into a plurality of areas by the longitudinal pattern portions 6a and the orthogonal pattern portions 6b of the inter-element ground internal conductor patterns 6, and the element internal conductor patterns 5 are provided in each area. , The number of elements can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer electronic component array in which a plurality of electronic component elements are arranged in parallel, and more particularly, to a multilayer electronic component array capable of reducing crosstalk between electronic component elements. The present invention relates to an electronic component array.

[0002]

2. Description of the Related Art One of conventional stacked electronic component arrays is, for example, shown in FIGS.
As shown in FIG. 5, there is a laminated varistor array (hereinafter abbreviated as “varistor array” as appropriate) used for absorbing a surge voltage. FIG. 13 is an external perspective view showing the entire varistor array, FIG. 14 is a perspective view of an insulator (resistor) sheet constituting a laminated body of the varistor array, and FIG. 15 is an equivalent circuit diagram of the varistor array.

In this varistor array 60 (FIG. 13), as shown in FIG. 14A, an insulator sheet 62 in which linear element internal conductor patterns 61 of six varistor elements are formed on the same surface. As shown in FIG. 14 (b), insulator sheets 64 each having a common ground internal conductor pattern 63 of six varistor elements formed on the surface thereof are alternately laminated. Each element internal conductor pattern 61 is opposed to the common ground internal conductor pattern 63 so that one varistor element is formed for each element internal conductor pattern 61. Note that a plurality of the insulator sheets 62 and 64 are laminated as necessary.

[0004] Then, as shown in FIG.
Six element external electrodes 66 and 67 of each varistor element are disposed on both sides on the long side, and ground external electrodes 68 and 69 are disposed on the short side of the laminated body 65. ing. One end of the element internal conductor pattern 61 is connected to each element external electrode 66, the other end is connected to each element external electrode 67, and both ends of the common ground internal conductor pattern 63 are connected to the ground. It is connected to external electrodes 68 and 69. As a result, the varistor array 60 has a configuration in which a total of six varistor elements Ba (FIG. 15) are independently arranged in parallel on the stacked body 65.

The varistor array 60 has a feature that six varistor elements Ba can be collectively mounted on the board in a compact manner by mounting one array on the board. When a surge voltage exceeding the rating is input from the element external electrodes 66 and 67 of
A conduction state is established between the element internal conductor pattern 61 and the common ground internal conductor pattern 63, and the surge absorbing function is exhibited.

As another conventional varistor array, there is a varistor array 70 as shown in FIG. In the varistor array 70, as shown in the equivalent circuit diagram of FIG. 17, the number of varistor elements Ba installed in parallel in the laminate 71 (FIG. 16) is three, and each varistor element Ba is The varistor array 70 has substantially the same configuration as that of the varistor array 70 except that one element external electrode 72 is provided on the long side of the stacked body 71.

In recent years, the varistor arrays 60 and 70 have been required to be further reduced in size. However, the conventional varistor arrays 60, 70
However, since the distance between the varistor elements becomes smaller with the miniaturization, crosstalk between the elements increases, and there is a problem that a malfunction of the circuit easily occurs.

An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a laminated electronic component array capable of reducing crosstalk between electronic component elements arranged in parallel.

[0009]

In order to achieve the above-mentioned object, a laminated electronic component array according to the present invention has a plurality of electronic component element internal conductor patterns formed on a surface thereof, and each of the element internal conductor patterns has a different shape. An insulator sheet having an inter-element ground internal conductor pattern formed between the internal conductor patterns and an insulator sheet having a common ground internal conductor pattern of the plurality of electronic component elements formed on the surface thereof are alternately laminated. Accordingly, a laminate in which a plurality of electronic component elements are installed in parallel is formed, and on the side surface of the laminate, an element external electrode and a ground external electrode of each electronic component element are formed, and The element internal conductor patterns are connected to the individual element external electrodes, and the common ground internal conductor pattern and the inter-element ground internal conductor pattern are It is characterized in that it is connected to the de external electrodes.

An inter-element ground internal conductor pattern is formed between the plurality of element internal conductor patterns formed on the surface of the insulator sheet, and the adjacent element internal conductor patterns are formed by the inter-element ground internal conductor pattern. Since the electromagnetic / electrostatic coupling between the conductor patterns is weakened, it is possible to suppress crosstalk between electronic component elements.

According to a second aspect of the present invention, the insulator sheet has a substantially rectangular shape,
The shape of the laminate is a substantially rectangular parallelepiped, and the inter-element ground internal conductor pattern is divided into two by dividing the surface of the insulator sheet along the longitudinal direction, and a direction orthogonal to the longitudinal direction. And an orthogonal pattern portion divided into a plurality of sections by dividing the element along each of the divided areas defined by the inter-element ground internal conductor pattern on the surface of the insulator sheet. Wherein one internal conductor pattern is formed, and the element external electrode and the ground external electrode are formed on the long side surface of the laminate.

The surface of the insulator sheet on which the element internal conductor pattern is formed is divided into a plurality of areas by the longitudinal pattern portion and the orthogonal pattern portion, and one element internal conductor is provided for each of the divided areas. In the case where the pattern is formed, the electronic component elements are arranged in two rows in parallel along the long side direction of the insulator sheet. Therefore, the number of electronic component elements per array is increased, and It is possible to reduce the size.

According to a third aspect of the present invention, there is provided a multilayer electronic component array, wherein the inter-element ground internal conductor pattern is formed at both short side ends of the insulator sheet over substantially the entire length of the end portion. A short side ground external electrode is provided on both short side surfaces of the laminate, and the short side ground external electrode has a short side. An outer edge of the side pattern portion and both end edges of the longitudinal pattern portion are connected.

The inter-element ground internal conductor pattern has short side pattern portions at both short side ends of the insulator sheet,
Separate short-side ground external electrodes are provided on both short side surfaces of the laminated body, and the short-side ground external electrode is connected to the outer edge of the short-side pattern portion and both end edges of the long-side pattern portion. In such a case, the electromagnetic component and the electrostatic coupling on the short side of the laminate are weakened by the short-side pattern portion and the short-side ground external electrode, and thus the electronic components facing each other on the short side of the laminate. Crosstalk between elements can be suppressed, and the present invention can be made more effective.

Further, according to the laminated electronic component array of the present invention, the distance L1 between the external electrode for the element and the ground external electrode, and the distance L between the internal conductor pattern for the element and the longitudinal pattern portion.
2, and the distance L3 between the element internal conductor pattern and the orthogonal pattern portion is made larger than the thickness of the insulator sheet.

By making the distances L1, L2, L3 larger than the thickness of the insulator sheet, it is possible to secure the withstand voltage required for the multilayer electronic component array, thereby making the present invention more effective. it can.

Further, the laminated electronic component array according to a fifth aspect is characterized in that the electronic component element is a varistor element and has a varistor array configuration. By applying the present invention to a varistor, a varistor array in which a plurality of varistor elements are arranged in parallel and which can surely avoid crosstalk can be reliably configured.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be shown and features thereof will be described in more detail. In the following embodiments, a varistor array will be described as an example of a multilayer electronic component array.

[First Embodiment] FIG. 1 is a perspective view showing an entire varistor array (stacked electronic component array) according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram thereof, and FIG. FIG. 2 is an exploded perspective view of a laminated body to be formed.

As shown in FIG. 3, the laminated body 2 constituting the varistor array 1 shown in FIG. 1 includes an insulator (resistor) sheet 4 having a common ground internal conductor pattern 3 of a varistor element formed on the surface thereof. An insulator (resistor) sheet 7 in which the element internal conductor patterns 5 of the six varistor elements and the inter-element ground internal conductor patterns 6 are formed on the same surface is laminated, and no pattern is formed on both upper and lower surfaces thereof. It is formed by disposing an insulator (resistor) sheet 8 for dummy (for protection).

Each of the insulator sheets 4 and 7 has a substantially rectangular planar shape, and the laminate 2 has a substantially rectangular parallelepiped shape as shown in FIG. On each of the long side surfaces 2a and 2b on the long side of the laminated body 2, three element external electrodes 9 and two ground external electrodes 10 are alternately formed in the lateral direction. As shown in FIG. 3, the common ground internal conductor pattern 3 has a rectangular pattern shape, and four lead-out ends 3a are connected to the ground external electrodes 10 (FIG. 1).

The element-to-element ground internal conductor pattern 6
Is formed by partitioning a substantially central portion of the surface of the insulator sheet 7 along the longitudinal direction, thereby dividing the insulator sheet 7 into two in a longitudinal direction pattern portion 6a, and dividing the insulator sheet 7 in a direction perpendicular to the longitudinal direction. And a pattern shape having an orthogonal pattern portion 6b for dividing the sheet 7 into a plurality of sections. The surface of the insulator sheet 7 is divided into six areas in two rows by the inter-element ground internal conductor pattern 6. It is partitioned. Then, one substantially square element internal conductor pattern 5 is formed for each section area.
It is preferable that the end of the longitudinal pattern portion 6a is formed to the shorter side edge of the insulator sheet 7 than the element internal conductor pattern 25. Each element internal conductor pattern 5 is connected to an individual element external electrode 9 (FIG. 1) by a leading end 5a.

Therefore, in the laminated body 2, the internal conductor patterns 5 for each element and the common ground internal conductor patterns 3 face each other via the insulator sheets 4 and 7, so that
A varistor element is formed for each element internal conductor pattern 5, and has a structure in which a total of six varistor elements Ba are arranged in two rows. The element internal conductor patterns 5 which are vertically overlapped and are connected in parallel to the same element external electrode 9 are the same varistor element B
a.

The distance L1 (FIG. 1) between the element external electrode 9 and the ground external electrode 10 and the element internal conductor pattern 5
L2 (FIG. 3) between the inner conductor pattern 5 and the longitudinal pattern portion 6a, and L3 (FIG. 3) between the element internal conductor pattern 5 and the orthogonal pattern portion 6b are both larger than the thickness of the insulator sheets 4 and 7. It is set to be large, and is configured such that a required withstand voltage is secured.

In the varistor array 1 of the first embodiment, if one array is mounted on a substrate, six varistor elements Ba
Can be collectively mounted on the substrate in a compact manner. If a surge voltage higher than the rated voltage is input from the element external electrode 9 of each varistor element Ba, the varistor element Ba is shared with the element internal conductor pattern 5. A conduction state is established between the ground inner conductor patterns 3, and a surge absorbing function is exhibited.

An element-to-element ground internal conductor pattern 6 is formed between each of the element internal conductor patterns 5, and an electromagnetic / electrostatic coupling between adjacent element internal conductor patterns 5 is formed. Is weakened, so that crosstalk between the varistor elements Ba can be suppressed.

[Second Embodiment] Next, a varistor array according to another embodiment (Embodiment 2) of the present invention will be described. FIG. 4 is a perspective view showing the entire varistor array according to the second embodiment, and FIG. 5 is a perspective view showing an insulator sheet on which element internal conductor patterns and inter-element ground internal conductor patterns are formed in the varistor array according to the second embodiment. FIG. 6 and FIG. 6 are equivalent circuit diagrams of the varistor array of the second embodiment.

In the varistor array 11 of the second embodiment, as shown in FIG. 5, the inter-element ground internal conductor pattern 12 is formed of the insulating sheet 13 in addition to the longitudinal pattern portion 12a and the orthogonal pattern portion 12b. It has a short side pattern portion 12c formed along substantially the entire length of both ends on the short side. In addition, as shown in FIG. 4, short side ground external electrodes 15 are arranged on both side surfaces on the short side of the laminate 14. The outer edges of the short-side pattern portion 12c and both end edges of the longitudinal-direction pattern portion 12a are connected to the short-side ground external electrodes 15 and 15, respectively.

The other parts have the same configuration as that of the first embodiment, so that illustration and description are omitted to avoid duplication.

In the varistor array 11 of the second embodiment, the short-side pattern portion 12c of the inter-element ground internal conductor pattern 12 and the ground external electrode 15 also provide electromagnetic and electrostatic characteristics on the short side of the laminate 14. Since the coupling is sufficiently weakened, crosstalk between varistor elements facing each other on the short side of the stacked body 14 can be sufficiently suppressed.

[Third Embodiment] Next, a varistor array according to still another embodiment (third embodiment) of the present invention will be described. FIG. 7 is a perspective view showing the entire varistor array according to the third embodiment, and FIG. 8 is a perspective view showing an insulator sheet on which the element internal conductor pattern and the inter-element ground internal conductor pattern in the varistor array according to the third embodiment are formed. FIG. 9 and FIG. 9 are equivalent circuit diagrams of the varistor array according to the third embodiment.

Varistor array 16 of Embodiment 3 (FIG. 7)
As shown in FIG. 8, the longitudinal pattern portion 17a of the inter-element ground internal conductor pattern 17 has a shape which reaches both short edges of the insulator sheet 28, but the orthogonal pattern portion 17b Is the insulator sheet 28
Ends on the front side without reaching the edges of both long sides. Therefore, as shown in FIG. 7, only the element external electrodes 9 are provided on both long side surfaces of the varistor array 16 on the long side, and no ground external electrodes are provided. Ground external electrodes 15 are provided only on both side surfaces on the side. In addition,
Other configurations are the same as those in the first embodiment, and thus illustration and description are omitted to avoid duplication.
It is preferable that the orthogonal pattern portion 17b is formed to extend beyond the lead end 5a of the element internal conductor pattern 5.

As described above, in the varistor array 16, it is not necessary to form the ground external electrodes on both long sides of the laminated body 18. It can be used as a region where the electrode 9 is formed, and the degree of freedom in design can be improved.

Embodiment 4 Next, a varistor array according to still another embodiment (Embodiment 4) of the present invention will be described. FIG. 10 is a perspective view showing the entire varistor array according to the fourth embodiment, FIG. 11 is an equivalent circuit diagram of the varistor array according to the fourth embodiment, and FIG.
FIG. 4 is an exploded perspective view of a laminate constituting the varistor array of FIG.

In the case of the varistor array 19 of the fourth embodiment, as shown in FIG. 12, the insulator sheet 4 on the surface of which the common ground internal conductor pattern 3 of the varistor element is formed.
As for the dummy (protection) sheet 8 on which no pattern is formed, the same one as in the first embodiment is used.
As the insulator sheet 20 on which the element internal conductor pattern and the inter-element ground internal conductor pattern are formed, three linear element internal conductor patterns 21 are provided on the same surface, and each element Internal conductor pattern 21
Between them, a linear inter-element ground internal conductor pattern 22 is formed.

Then, as shown in FIG. 10, on the both sides on the long side of the laminate 23 formed by stacking the insulator sheets 4, 8, 20 as shown in FIG. 24, 25 and ground external electrodes 26, 27 are provided. Further, one end of each element internal conductor pattern 21 (FIG. 12) is connected to an element external electrode 24 (FIGS. 10 and 11).
The other end is connected to the element external electrode 25 (FIG. 1).
0, FIG. 11). One end of each element internal ground conductor pattern 22 (FIG. 12) is connected to a ground external electrode 26 (FIGS. 10 and 11), and the other end is connected to a ground external electrode 27 (FIGS. 10 and 11). And has a circuit configuration shown in FIG.

Therefore, in the laminated body 23, the varistors are provided for each element internal conductor pattern 21 by opposing the element internal conductor patterns 21 and the common ground internal conductor pattern 3 via the insulator sheets 4 and 20. An element is configured. In the case of the varistor array according to the fourth embodiment, a total of three varistor elements Ba are arranged in parallel in one row. Note that the other parts have the same configuration as that of the first embodiment, and thus illustration and description are omitted.

In the varistor array according to the fourth embodiment, as shown in FIG.
Two element external electrodes are provided, and one can be used as an input electrode and the other as an output electrode.

In each of the above embodiments, the case where the number of varistor elements Ba is three or six has been described. However, the number of varistor elements provided in the array may be appropriately increased or decreased according to the application. Is possible.

In the above embodiment, the case where the electronic component element is a varistor element has been described as an example. However, the case where the electronic component element is a capacitor element, an LC element, or an inductance element is also described. The present invention can be applied.

The present invention is not limited to the above-described embodiment in other respects. The internal electrode pattern for the device, the internal electrode pattern for the ground, the specific shapes of the external electrodes, the constituent material of each pattern, Various applications and modifications can be made within the scope of the invention with respect to the number and form of sheets laminated in the laminate, the material of the sheets (dielectric, magnetic material, resistor, semiconductor, etc.) and the like. .

[0042]

The present invention (each invention of claims 1 to 5)
In the multilayer electronic component array of the above, an inter-element ground internal conductor pattern is formed between element internal conductor patterns of a plurality of electronic component elements arranged in parallel on the same surface inside the multilayer body. Since the electromagnetic / electrostatic coupling between the internal conductor patterns for use is weakened, crosstalk between electronic component elements can be suppressed.

Further, as in the multilayer electronic component array according to the second aspect, the surface of the insulator sheet on which the internal conductor pattern for the element is formed is formed by connecting the surface of the inter-element ground internal conductor pattern with the longitudinal pattern and the orthogonal pattern. When a plurality of areas are defined by the above, and one internal conductor pattern for the element is formed for each of the divided areas, the electronic component elements are arranged in two rows in parallel along the long side direction of the insulator sheet. By increasing the number of electronic component elements per array, it is possible to reduce the size of the product.

Further, as in the multilayer electronic component array of claim 3, the inter-element ground internal conductor pattern has a short side pattern portion, and another short side ground is provided on both short side surfaces of the laminate. When the external electrode is provided, and the outer edge of the short-side pattern portion and both end edges of the longitudinal pattern portion are connected to the short-side ground external electrode, the short-side pattern portion and the short-side ground Since the external electrodes weaken the electromagnetic and electrostatic coupling on the short side of the laminate, it is possible to sufficiently suppress crosstalk between electronic component elements facing each other on the short side of the laminate, The present invention can be made more effective.

Further, as in the multilayer electronic component array according to the fourth aspect, the distance L between the external electrode for element and the ground external electrode is set.
1. When the interval L2 between the element internal conductor pattern and the longitudinal pattern portion and the interval L3 between the element internal conductor pattern and the orthogonal pattern portion are larger than the thickness of the insulator sheet, the laminated electronic component array is required. A high withstand voltage can be ensured, and the present invention can be made more effective.

Further, when the present invention is applied to a varistor like the laminated electronic component array of the fifth aspect, a varistor array which is small and can surely avoid crosstalk can be surely constructed. .

[Brief description of the drawings]

FIG. 1 is a perspective view showing an entire varistor array according to an embodiment (Embodiment 1) of the present invention.

FIG. 2 is an equivalent circuit diagram of a varistor array according to an embodiment (Embodiment 1) of the present invention.

FIG. 3 is an exploded perspective view of a laminate constituting a varistor array according to one embodiment (Embodiment 1) of the present invention.

FIG. 4 is a perspective view showing the entire varistor array according to an embodiment (Embodiment 2) of the present invention.

FIG. 5 is a perspective view of an insulator sheet constituting a varistor array laminate according to an embodiment (Embodiment 2) of the present invention.

FIG. 6 is an equivalent circuit diagram of a varistor array according to an embodiment (Embodiment 2) of the present invention.

FIG. 7 is a perspective view showing the entire varistor array according to an embodiment (Embodiment 3) of the present invention.

FIG. 8 is a perspective view of an insulator sheet constituting a stacked body of a varistor array according to an embodiment (Embodiment 3) of the present invention.

FIG. 9 is an equivalent circuit diagram of a varistor array according to an embodiment (Embodiment 3) of the present invention.

FIG. 10 is a perspective view showing the entire varistor array according to an embodiment (Embodiment 4) of the present invention.

FIG. 11 is an equivalent circuit diagram of a varistor array according to an embodiment (Embodiment 4) of the present invention.

FIG. 12 is an exploded perspective view of a laminate constituting a varistor array according to an embodiment (Embodiment 4) of the present invention.

FIG. 13 is a perspective view showing an entire conventional varistor array.

FIG. 14 is a perspective view of an insulator sheet constituting a laminated body of a conventional varistor array.

FIG. 15 is an equivalent circuit diagram of a conventional varistor array.

FIG. 16 is a perspective view showing the whole of another conventional varistor array.

FIG. 17 is an equivalent circuit diagram of another conventional varistor array.

[Explanation of symbols]

1,11,16,19 Varistor array 2,14,18,23 Laminated body 2a, 2b Both side surfaces on long side of laminated body 3 Common ground internal conductor pattern 3a, 5a Lead-out end 4,7,13,20, 28 Insulator sheet 5, 21 Element internal conductor pattern 6, 12, 17, 22 Inter-element ground internal conductor pattern 6a, 12a, 17a Longitudinal pattern portion 6b, 12b, 17b Orthogonal pattern portion 8 Dummy (for protection) Insulator sheet 9, 24, 25 External electrode for element 10, 15, 26, 27 Ground external electrode 12c Short side pattern portion 15 Ground external electrode Ba Varistor element L1 Distance between external electrode for element and ground external electrode L2 For element Distance between internal conductor pattern and longitudinal pattern portion L3 Internal conductor pattern for element and orthogonal pattern portion Interval

Claims (5)

(57) [Claims] 1. An insulator sheet having a plurality of element internal conductor patterns formed on a surface thereof, and an inter-element ground internal conductor pattern formed between each of the element internal conductor patterns. By alternately laminating an insulator sheet on which a common ground internal conductor pattern of the plurality of electronic component elements is formed, a laminate in which a plurality of electronic component elements are installed in parallel is formed, A device external electrode and a ground external electrode of each electronic component device are formed on a side surface of the laminate, and the device internal conductor patterns are connected to individual device external electrodes, and the common ground is provided. A multilayer electronic component array, wherein the internal conductor pattern and the inter-element ground internal conductor pattern are connected to a ground external electrode. 2. The insulator sheet has a substantially rectangular shape, and the laminate has a substantially rectangular parallelepiped shape. The inter-element ground internal conductor pattern extends the surface of the insulator sheet in a longitudinal direction. A longitudinal pattern portion divided into two by partitioning along, and a shape provided with a perpendicular pattern portion divided into a plurality by dividing along a direction perpendicular to the longitudinal direction, and a surface of the insulating sheet. One internal conductor pattern for the element is formed for each section area defined by the inter-element ground internal conductor pattern, and the element external electrode and the ground external electrode are on the long side of the laminate. 2. The multilayer electronic component array according to claim 1, wherein the array is formed on a side surface of the electronic component. 3. The inter-element ground internal conductor pattern,
At both ends of the short side of the insulator sheet, a short side pattern portion formed over substantially the entire length of the end is provided. A side-side ground external electrode is provided, and the outer edge of the short-side pattern portion and both end edges of the longitudinal pattern portion are connected to the short-side ground external electrode. 3. The laminated electronic component array according to 2. 4. A distance L1 between the element external electrode and the ground external electrode, a distance L2 between the element internal conductor pattern and the longitudinal pattern part, and a distance L2 between the element internal conductor pattern and the orthogonal pattern part. The interval L3 is
4. The multilayer electronic component array according to claim 2, wherein the thickness of the insulator sheet is larger than the thickness of the insulator sheet. 5. The multilayer electronic component array according to claim 1, wherein said electronic component element is a varistor element and has a varistor array configuration.